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My Project
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Macros | |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint32_t)0x000000FF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V2 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_2V3 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_2V4 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2V5 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_2V6 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | BKP_DR1_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR2_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR3_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR4_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR5_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR6_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR7_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR8_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR9_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR10_D ((uint32_t)0x0000FFFF) |
| #define | RTC_BKP_NUMBER 10 |
| #define | BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
| #define | BKP_RTCCR_CCO ((uint32_t)0x00000080) |
| #define | BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
| #define | BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
| #define | BKP_CR_TPE ((uint32_t)0x00000001) |
| #define | BKP_CR_TPAL ((uint32_t)0x00000002) |
| #define | BKP_CSR_CTE ((uint32_t)0x00000001) |
| #define | BKP_CSR_CTI ((uint32_t)0x00000002) |
| #define | BKP_CSR_TPIE ((uint32_t)0x00000004) |
| #define | BKP_CSR_TEF ((uint32_t)0x00000100) |
| #define | BKP_CSR_TIF ((uint32_t)0x00000200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) |
| #define | RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) |
| #define | RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) |
| #define | RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) |
| #define | RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) |
| #define | RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) |
| #define | RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_CECEN ((uint32_t)0x40000000) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) |
| #define | RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) |
| #define | RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) |
| #define | RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) |
| #define | RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) |
| #define | RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) |
| #define | RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) |
| #define | RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) |
| #define | RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) |
| #define | RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) |
| #define | RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) |
| #define | RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) |
| #define | RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) |
| #define | RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) |
| #define | RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) |
| #define | RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) |
| #define | RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) |
| #define | RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint32_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint32_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint32_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint32_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint32_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint32_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint32_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint32_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint32_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint32_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint32_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint32_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint32_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint32_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint32_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint32_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint32_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint32_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint32_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint32_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint32_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint32_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint32_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint32_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint32_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint32_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint32_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint32_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint32_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint32_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint32_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint32_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint32_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint32_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint32_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint32_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint32_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint32_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint32_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint32_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint32_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint32_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint32_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint32_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint32_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint32_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint32_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint32_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
| #define | AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
| #define | AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
| #define | AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
| #define | AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
| #define | AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PORT ((uint32_t)0x00000070) |
| #define | AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
| #define | AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
| #define | AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
| #define | AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) |
| #define | AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) |
| #define | SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) |
| #define | SCB_SCR_SEVONPEND ((uint32_t)0x00000010) |
| #define | SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) |
| #define | SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) |
| #define | SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) |
| #define | SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) |
| #define | SCB_CCR_STKALIGN ((uint32_t)0x00000200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint32_t)0x00000001) |
| #define | SCB_DFSR_BKPT ((uint32_t)0x00000002) |
| #define | SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) |
| #define | SCB_DFSR_VCATCH ((uint32_t)0x00000008) |
| #define | SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) |
| #define | DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) |
| #define | DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) |
| #define | DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) |
| #define | DAC_SR_DMAUDR1 ((uint32_t)0x00002000) |
| #define | DAC_SR_DMAUDR2 ((uint32_t)0x20000000) |
| #define | CEC_CFGR_PE ((uint32_t)0x00000001) |
| #define | CEC_CFGR_IE ((uint32_t)0x00000002) |
| #define | CEC_CFGR_BTEM ((uint32_t)0x00000004) |
| #define | CEC_CFGR_BPEM ((uint32_t)0x00000008) |
| #define | CEC_OAR_OA ((uint32_t)0x0000000F) |
| #define | CEC_OAR_OA_0 ((uint32_t)0x00000001) |
| #define | CEC_OAR_OA_1 ((uint32_t)0x00000002) |
| #define | CEC_OAR_OA_2 ((uint32_t)0x00000004) |
| #define | CEC_OAR_OA_3 ((uint32_t)0x00000008) |
| #define | CEC_PRES_PRES ((uint32_t)0x00003FFF) |
| #define | CEC_ESR_BTE ((uint32_t)0x00000001) |
| #define | CEC_ESR_BPE ((uint32_t)0x00000002) |
| #define | CEC_ESR_RBTFE ((uint32_t)0x00000004) |
| #define | CEC_ESR_SBE ((uint32_t)0x00000008) |
| #define | CEC_ESR_ACKE ((uint32_t)0x00000010) |
| #define | CEC_ESR_LINE ((uint32_t)0x00000020) |
| #define | CEC_ESR_TBTFE ((uint32_t)0x00000040) |
| #define | CEC_CSR_TSOM ((uint32_t)0x00000001) |
| #define | CEC_CSR_TEOM ((uint32_t)0x00000002) |
| #define | CEC_CSR_TERR ((uint32_t)0x00000004) |
| #define | CEC_CSR_TBTRF ((uint32_t)0x00000008) |
| #define | CEC_CSR_RSOM ((uint32_t)0x00000010) |
| #define | CEC_CSR_REOM ((uint32_t)0x00000020) |
| #define | CEC_CSR_RERR ((uint32_t)0x00000040) |
| #define | CEC_CSR_RBTF ((uint32_t)0x00000080) |
| #define | CEC_TXD_TXD ((uint32_t)0x000000FF) |
| #define | CEC_RXD_RXD ((uint32_t)0x000000FF) |
| #define | TIM_CR1_CEN ((uint32_t)0x00000001) |
| #define | TIM_CR1_UDIS ((uint32_t)0x00000002) |
| #define | TIM_CR1_URS ((uint32_t)0x00000004) |
| #define | TIM_CR1_OPM ((uint32_t)0x00000008) |
| #define | TIM_CR1_DIR ((uint32_t)0x00000010) |
| #define | TIM_CR1_CMS ((uint32_t)0x00000060) |
| #define | TIM_CR1_CMS_0 ((uint32_t)0x00000020) |
| #define | TIM_CR1_CMS_1 ((uint32_t)0x00000040) |
| #define | TIM_CR1_ARPE ((uint32_t)0x00000080) |
| #define | TIM_CR1_CKD ((uint32_t)0x00000300) |
| #define | TIM_CR1_CKD_0 ((uint32_t)0x00000100) |
| #define | TIM_CR1_CKD_1 ((uint32_t)0x00000200) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00000007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint32_t)0x00000001) |
| #define | TIM_DIER_CC1IE ((uint32_t)0x00000002) |
| #define | TIM_DIER_CC2IE ((uint32_t)0x00000004) |
| #define | TIM_DIER_CC3IE ((uint32_t)0x00000008) |
| #define | TIM_DIER_CC4IE ((uint32_t)0x00000010) |
| #define | TIM_DIER_COMIE ((uint32_t)0x00000020) |
| #define | TIM_DIER_TIE ((uint32_t)0x00000040) |
| #define | TIM_DIER_BIE ((uint32_t)0x00000080) |
| #define | TIM_DIER_UDE ((uint32_t)0x00000100) |
| #define | TIM_DIER_CC1DE ((uint32_t)0x00000200) |
| #define | TIM_DIER_CC2DE ((uint32_t)0x00000400) |
| #define | TIM_DIER_CC3DE ((uint32_t)0x00000800) |
| #define | TIM_DIER_CC4DE ((uint32_t)0x00001000) |
| #define | TIM_DIER_COMDE ((uint32_t)0x00002000) |
| #define | TIM_DIER_TDE ((uint32_t)0x00004000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_EGR_UG ((uint32_t)0x00000001) |
| #define | TIM_EGR_CC1G ((uint32_t)0x00000002) |
| #define | TIM_EGR_CC2G ((uint32_t)0x00000004) |
| #define | TIM_EGR_CC3G ((uint32_t)0x00000008) |
| #define | TIM_EGR_CC4G ((uint32_t)0x00000010) |
| #define | TIM_EGR_COMG ((uint32_t)0x00000020) |
| #define | TIM_EGR_TG ((uint32_t)0x00000040) |
| #define | TIM_EGR_BG ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00000070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x00007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_PSC_PSC ((uint32_t)0x0000FFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint32_t)0x000000FF) |
| #define | TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_DCR_DBA ((uint32_t)0x0000001F) |
| #define | TIM_DCR_DBA_0 ((uint32_t)0x00000001) |
| #define | TIM_DCR_DBA_1 ((uint32_t)0x00000002) |
| #define | TIM_DCR_DBA_2 ((uint32_t)0x00000004) |
| #define | TIM_DCR_DBA_3 ((uint32_t)0x00000008) |
| #define | TIM_DCR_DBA_4 ((uint32_t)0x00000010) |
| #define | TIM_DCR_DBL ((uint32_t)0x00001F00) |
| #define | TIM_DCR_DBL_0 ((uint32_t)0x00000100) |
| #define | TIM_DCR_DBL_1 ((uint32_t)0x00000200) |
| #define | TIM_DCR_DBL_2 ((uint32_t)0x00000400) |
| #define | TIM_DCR_DBL_3 ((uint32_t)0x00000800) |
| #define | TIM_DCR_DBL_4 ((uint32_t)0x00001000) |
| #define | TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) |
| #define | RTC_CRH_SECIE ((uint32_t)0x00000001) |
| #define | RTC_CRH_ALRIE ((uint32_t)0x00000002) |
| #define | RTC_CRH_OWIE ((uint32_t)0x00000004) |
| #define | RTC_CRL_SECF ((uint32_t)0x00000001) |
| #define | RTC_CRL_ALRF ((uint32_t)0x00000002) |
| #define | RTC_CRL_OWF ((uint32_t)0x00000004) |
| #define | RTC_CRL_RSF ((uint32_t)0x00000008) |
| #define | RTC_CRL_CNF ((uint32_t)0x00000010) |
| #define | RTC_CRL_RTOFF ((uint32_t)0x00000020) |
| #define | RTC_PRLH_PRL ((uint32_t)0x0000000F) |
| #define | RTC_PRLL_PRL ((uint32_t)0x0000FFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) |
| #define | RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | IWDG_KR_KEY ((uint32_t)0x0000FFFF) |
| #define | IWDG_PR_PR ((uint32_t)0x00000007) |
| #define | IWDG_PR_PR_0 ((uint32_t)0x00000001) |
| #define | IWDG_PR_PR_1 ((uint32_t)0x00000002) |
| #define | IWDG_PR_PR_2 ((uint32_t)0x00000004) |
| #define | IWDG_RLR_RL ((uint32_t)0x00000FFF) |
| #define | IWDG_SR_PVU ((uint32_t)0x00000001) |
| #define | IWDG_SR_RVU ((uint32_t)0x00000002) |
| #define | WWDG_CR_T ((uint32_t)0x0000007F) |
| #define | WWDG_CR_T0 ((uint32_t)0x00000001) |
| #define | WWDG_CR_T1 ((uint32_t)0x00000002) |
| #define | WWDG_CR_T2 ((uint32_t)0x00000004) |
| #define | WWDG_CR_T3 ((uint32_t)0x00000008) |
| #define | WWDG_CR_T4 ((uint32_t)0x00000010) |
| #define | WWDG_CR_T5 ((uint32_t)0x00000020) |
| #define | WWDG_CR_T6 ((uint32_t)0x00000040) |
| #define | WWDG_CR_WDGA ((uint32_t)0x00000080) |
| #define | WWDG_CFR_W ((uint32_t)0x0000007F) |
| #define | WWDG_CFR_W0 ((uint32_t)0x00000001) |
| #define | WWDG_CFR_W1 ((uint32_t)0x00000002) |
| #define | WWDG_CFR_W2 ((uint32_t)0x00000004) |
| #define | WWDG_CFR_W3 ((uint32_t)0x00000008) |
| #define | WWDG_CFR_W4 ((uint32_t)0x00000010) |
| #define | WWDG_CFR_W5 ((uint32_t)0x00000020) |
| #define | WWDG_CFR_W6 ((uint32_t)0x00000040) |
| #define | WWDG_CFR_WDGTB ((uint32_t)0x00000180) |
| #define | WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) |
| #define | WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) |
| #define | WWDG_CFR_EWI ((uint32_t)0x00000200) |
| #define | WWDG_SR_EWIF ((uint32_t)0x00000001) |
| #define | SDIO_POWER_PWRCTRL ((uint32_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint32_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint32_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint32_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint32_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint32_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint32_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint32_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint32_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint32_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint32_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint32_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint32_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint32_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint32_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint32_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | SPI_CR1_CPHA ((uint32_t)0x00000001) |
| #define | SPI_CR1_CPOL ((uint32_t)0x00000002) |
| #define | SPI_CR1_MSTR ((uint32_t)0x00000004) |
| #define | SPI_CR1_BR ((uint32_t)0x00000038) |
| #define | SPI_CR1_BR_0 ((uint32_t)0x00000008) |
| #define | SPI_CR1_BR_1 ((uint32_t)0x00000010) |
| #define | SPI_CR1_BR_2 ((uint32_t)0x00000020) |
| #define | SPI_CR1_SPE ((uint32_t)0x00000040) |
| #define | SPI_CR1_LSBFIRST ((uint32_t)0x00000080) |
| #define | SPI_CR1_SSI ((uint32_t)0x00000100) |
| #define | SPI_CR1_SSM ((uint32_t)0x00000200) |
| #define | SPI_CR1_RXONLY ((uint32_t)0x00000400) |
| #define | SPI_CR1_DFF ((uint32_t)0x00000800) |
| #define | SPI_CR1_CRCNEXT ((uint32_t)0x00001000) |
| #define | SPI_CR1_CRCEN ((uint32_t)0x00002000) |
| #define | SPI_CR1_BIDIOE ((uint32_t)0x00004000) |
| #define | SPI_CR1_BIDIMODE ((uint32_t)0x00008000) |
| #define | SPI_CR2_RXDMAEN ((uint32_t)0x00000001) |
| #define | SPI_CR2_TXDMAEN ((uint32_t)0x00000002) |
| #define | SPI_CR2_SSOE ((uint32_t)0x00000004) |
| #define | SPI_CR2_ERRIE ((uint32_t)0x00000020) |
| #define | SPI_CR2_RXNEIE ((uint32_t)0x00000040) |
| #define | SPI_CR2_TXEIE ((uint32_t)0x00000080) |
| #define | SPI_SR_RXNE ((uint32_t)0x00000001) |
| #define | SPI_SR_TXE ((uint32_t)0x00000002) |
| #define | SPI_SR_CHSIDE ((uint32_t)0x00000004) |
| #define | SPI_SR_UDR ((uint32_t)0x00000008) |
| #define | SPI_SR_CRCERR ((uint32_t)0x00000010) |
| #define | SPI_SR_MODF ((uint32_t)0x00000020) |
| #define | SPI_SR_OVR ((uint32_t)0x00000040) |
| #define | SPI_SR_BSY ((uint32_t)0x00000080) |
| #define | SPI_DR_DR ((uint32_t)0x0000FFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_SMBUS ((uint32_t)0x00000002) |
| #define | I2C_CR1_SMBTYPE ((uint32_t)0x00000008) |
| #define | I2C_CR1_ENARP ((uint32_t)0x00000010) |
| #define | I2C_CR1_ENPEC ((uint32_t)0x00000020) |
| #define | I2C_CR1_ENGC ((uint32_t)0x00000040) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) |
| #define | I2C_CR1_START ((uint32_t)0x00000100) |
| #define | I2C_CR1_STOP ((uint32_t)0x00000200) |
| #define | I2C_CR1_ACK ((uint32_t)0x00000400) |
| #define | I2C_CR1_POS ((uint32_t)0x00000800) |
| #define | I2C_CR1_PEC ((uint32_t)0x00001000) |
| #define | I2C_CR1_ALERT ((uint32_t)0x00002000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00008000) |
| #define | I2C_CR2_FREQ ((uint32_t)0x0000003F) |
| #define | I2C_CR2_FREQ_0 ((uint32_t)0x00000001) |
| #define | I2C_CR2_FREQ_1 ((uint32_t)0x00000002) |
| #define | I2C_CR2_FREQ_2 ((uint32_t)0x00000004) |
| #define | I2C_CR2_FREQ_3 ((uint32_t)0x00000008) |
| #define | I2C_CR2_FREQ_4 ((uint32_t)0x00000010) |
| #define | I2C_CR2_FREQ_5 ((uint32_t)0x00000020) |
| #define | I2C_CR2_ITERREN ((uint32_t)0x00000100) |
| #define | I2C_CR2_ITEVTEN ((uint32_t)0x00000200) |
| #define | I2C_CR2_ITBUFEN ((uint32_t)0x00000400) |
| #define | I2C_CR2_DMAEN ((uint32_t)0x00000800) |
| #define | I2C_CR2_LAST ((uint32_t)0x00001000) |
| #define | I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) |
| #define | I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) |
| #define | I2C_OAR1_ADD0 ((uint32_t)0x00000001) |
| #define | I2C_OAR1_ADD1 ((uint32_t)0x00000002) |
| #define | I2C_OAR1_ADD2 ((uint32_t)0x00000004) |
| #define | I2C_OAR1_ADD3 ((uint32_t)0x00000008) |
| #define | I2C_OAR1_ADD4 ((uint32_t)0x00000010) |
| #define | I2C_OAR1_ADD5 ((uint32_t)0x00000020) |
| #define | I2C_OAR1_ADD6 ((uint32_t)0x00000040) |
| #define | I2C_OAR1_ADD7 ((uint32_t)0x00000080) |
| #define | I2C_OAR1_ADD8 ((uint32_t)0x00000100) |
| #define | I2C_OAR1_ADD9 ((uint32_t)0x00000200) |
| #define | I2C_OAR1_ADDMODE ((uint32_t)0x00008000) |
| #define | I2C_OAR2_ENDUAL ((uint32_t)0x00000001) |
| #define | I2C_OAR2_ADD2 ((uint32_t)0x000000FE) |
| #define | I2C_SR1_SB ((uint32_t)0x00000001) |
| #define | I2C_SR1_ADDR ((uint32_t)0x00000002) |
| #define | I2C_SR1_BTF ((uint32_t)0x00000004) |
| #define | I2C_SR1_ADD10 ((uint32_t)0x00000008) |
| #define | I2C_SR1_STOPF ((uint32_t)0x00000010) |
| #define | I2C_SR1_RXNE ((uint32_t)0x00000040) |
| #define | I2C_SR1_TXE ((uint32_t)0x00000080) |
| #define | I2C_SR1_BERR ((uint32_t)0x00000100) |
| #define | I2C_SR1_ARLO ((uint32_t)0x00000200) |
| #define | I2C_SR1_AF ((uint32_t)0x00000400) |
| #define | I2C_SR1_OVR ((uint32_t)0x00000800) |
| #define | I2C_SR1_PECERR ((uint32_t)0x00001000) |
| #define | I2C_SR1_TIMEOUT ((uint32_t)0x00004000) |
| #define | I2C_SR1_SMBALERT ((uint32_t)0x00008000) |
| #define | I2C_SR2_MSL ((uint32_t)0x00000001) |
| #define | I2C_SR2_BUSY ((uint32_t)0x00000002) |
| #define | I2C_SR2_TRA ((uint32_t)0x00000004) |
| #define | I2C_SR2_GENCALL ((uint32_t)0x00000010) |
| #define | I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) |
| #define | I2C_SR2_SMBHOST ((uint32_t)0x00000040) |
| #define | I2C_SR2_DUALF ((uint32_t)0x00000080) |
| #define | I2C_SR2_PEC ((uint32_t)0x0000FF00) |
| #define | I2C_CCR_CCR ((uint32_t)0x00000FFF) |
| #define | I2C_CCR_DUTY ((uint32_t)0x00004000) |
| #define | I2C_CCR_FS ((uint32_t)0x00008000) |
| #define | I2C_TRISE_TRISE ((uint32_t)0x0000003F) |
| #define | USART_SR_PE ((uint32_t)0x00000001) |
| #define | USART_SR_FE ((uint32_t)0x00000002) |
| #define | USART_SR_NE ((uint32_t)0x00000004) |
| #define | USART_SR_ORE ((uint32_t)0x00000008) |
| #define | USART_SR_IDLE ((uint32_t)0x00000010) |
| #define | USART_SR_RXNE ((uint32_t)0x00000020) |
| #define | USART_SR_TC ((uint32_t)0x00000040) |
| #define | USART_SR_TXE ((uint32_t)0x00000080) |
| #define | USART_SR_LBD ((uint32_t)0x00000100) |
| #define | USART_SR_CTS ((uint32_t)0x00000200) |
| #define | USART_DR_DR ((uint32_t)0x000001FF) |
| #define | USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) |
| #define | USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) |
| #define | USART_CR1_SBK ((uint32_t)0x00000001) |
| #define | USART_CR1_RWU ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_UE ((uint32_t)0x00002000) |
| #define | USART_CR2_ADD ((uint32_t)0x0000000F) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_GTPR_PSC ((uint32_t)0x000000FF) |
| #define | USART_GTPR_PSC_0 ((uint32_t)0x00000001) |
| #define | USART_GTPR_PSC_1 ((uint32_t)0x00000002) |
| #define | USART_GTPR_PSC_2 ((uint32_t)0x00000004) |
| #define | USART_GTPR_PSC_3 ((uint32_t)0x00000008) |
| #define | USART_GTPR_PSC_4 ((uint32_t)0x00000010) |
| #define | USART_GTPR_PSC_5 ((uint32_t)0x00000020) |
| #define | USART_GTPR_PSC_6 ((uint32_t)0x00000040) |
| #define | USART_GTPR_PSC_7 ((uint32_t)0x00000080) |
| #define | USART_GTPR_GT ((uint32_t)0x0000FF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) |
| #define | DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) |
| #define | DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) |
| #define | DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) |
| #define | FLASH_ACR_HLFCYA ((uint32_t)0x00000008) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint32_t)0x000000A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT ((uint32_t)0x00000002) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) |
| #define | FLASH_OBR_USER ((uint32_t)0x0000001C) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) |
| #define | FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) |
| #define | FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) |
| #define | FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint32_t)0x000000FF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V2 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_2V3 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_2V4 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2V5 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_2V6 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | BKP_DR1_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR2_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR3_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR4_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR5_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR6_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR7_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR8_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR9_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR10_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR11_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR12_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR13_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR14_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR15_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR16_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR17_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR18_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR19_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR20_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR21_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR22_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR23_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR24_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR25_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR26_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR27_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR28_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR29_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR30_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR31_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR32_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR33_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR34_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR35_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR36_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR37_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR38_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR39_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR40_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR41_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR42_D ((uint32_t)0x0000FFFF) |
| #define | RTC_BKP_NUMBER 42 |
| #define | BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
| #define | BKP_RTCCR_CCO ((uint32_t)0x00000080) |
| #define | BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
| #define | BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
| #define | BKP_CR_TPE ((uint32_t)0x00000001) |
| #define | BKP_CR_TPAL ((uint32_t)0x00000002) |
| #define | BKP_CSR_CTE ((uint32_t)0x00000001) |
| #define | BKP_CSR_CTI ((uint32_t)0x00000002) |
| #define | BKP_CSR_TPIE ((uint32_t)0x00000004) |
| #define | BKP_CSR_TEF ((uint32_t)0x00000100) |
| #define | BKP_CSR_TIF ((uint32_t)0x00000200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) |
| #define | RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) |
| #define | RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) |
| #define | RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) |
| #define | RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) |
| #define | RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) |
| #define | RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
| #define | RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) |
| #define | RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) |
| #define | RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) |
| #define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
| #define | RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) |
| #define | RCC_AHBENR_FSMCEN ((uint32_t)0x00000100) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) |
| #define | RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) |
| #define | RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) |
| #define | RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) |
| #define | RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) |
| #define | RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_CECEN ((uint32_t)0x40000000) |
| #define | RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
| #define | RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) |
| #define | RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) |
| #define | RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) |
| #define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
| #define | RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) |
| #define | RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) |
| #define | RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) |
| #define | RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) |
| #define | RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) |
| #define | RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) |
| #define | RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) |
| #define | RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) |
| #define | RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) |
| #define | RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) |
| #define | RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) |
| #define | RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) |
| #define | RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) |
| #define | RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) |
| #define | RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) |
| #define | RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) |
| #define | RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) |
| #define | RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint32_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint32_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint32_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint32_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint32_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint32_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint32_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint32_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint32_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint32_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint32_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint32_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint32_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint32_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint32_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint32_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint32_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint32_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint32_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint32_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint32_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint32_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint32_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint32_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint32_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint32_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint32_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint32_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint32_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint32_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint32_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint32_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint32_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint32_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint32_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint32_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint32_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint32_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint32_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint32_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint32_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint32_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint32_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint32_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint32_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint32_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint32_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint32_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
| #define | AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
| #define | AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
| #define | AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
| #define | AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
| #define | AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PORT ((uint32_t)0x00000070) |
| #define | AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
| #define | AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
| #define | AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
| #define | AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) |
| #define | AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) |
| #define | AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) |
| #define | AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) |
| #define | AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) |
| #define | AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) |
| #define | SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) |
| #define | SCB_SCR_SEVONPEND ((uint32_t)0x00000010) |
| #define | SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) |
| #define | SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) |
| #define | SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) |
| #define | SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) |
| #define | SCB_CCR_STKALIGN ((uint32_t)0x00000200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint32_t)0x00000001) |
| #define | SCB_DFSR_BKPT ((uint32_t)0x00000002) |
| #define | SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) |
| #define | SCB_DFSR_VCATCH ((uint32_t)0x00000008) |
| #define | SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) |
| #define | DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) |
| #define | DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) |
| #define | DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) |
| #define | DAC_SR_DMAUDR1 ((uint32_t)0x00002000) |
| #define | DAC_SR_DMAUDR2 ((uint32_t)0x20000000) |
| #define | CEC_CFGR_PE ((uint32_t)0x00000001) |
| #define | CEC_CFGR_IE ((uint32_t)0x00000002) |
| #define | CEC_CFGR_BTEM ((uint32_t)0x00000004) |
| #define | CEC_CFGR_BPEM ((uint32_t)0x00000008) |
| #define | CEC_OAR_OA ((uint32_t)0x0000000F) |
| #define | CEC_OAR_OA_0 ((uint32_t)0x00000001) |
| #define | CEC_OAR_OA_1 ((uint32_t)0x00000002) |
| #define | CEC_OAR_OA_2 ((uint32_t)0x00000004) |
| #define | CEC_OAR_OA_3 ((uint32_t)0x00000008) |
| #define | CEC_PRES_PRES ((uint32_t)0x00003FFF) |
| #define | CEC_ESR_BTE ((uint32_t)0x00000001) |
| #define | CEC_ESR_BPE ((uint32_t)0x00000002) |
| #define | CEC_ESR_RBTFE ((uint32_t)0x00000004) |
| #define | CEC_ESR_SBE ((uint32_t)0x00000008) |
| #define | CEC_ESR_ACKE ((uint32_t)0x00000010) |
| #define | CEC_ESR_LINE ((uint32_t)0x00000020) |
| #define | CEC_ESR_TBTFE ((uint32_t)0x00000040) |
| #define | CEC_CSR_TSOM ((uint32_t)0x00000001) |
| #define | CEC_CSR_TEOM ((uint32_t)0x00000002) |
| #define | CEC_CSR_TERR ((uint32_t)0x00000004) |
| #define | CEC_CSR_TBTRF ((uint32_t)0x00000008) |
| #define | CEC_CSR_RSOM ((uint32_t)0x00000010) |
| #define | CEC_CSR_REOM ((uint32_t)0x00000020) |
| #define | CEC_CSR_RERR ((uint32_t)0x00000040) |
| #define | CEC_CSR_RBTF ((uint32_t)0x00000080) |
| #define | CEC_TXD_TXD ((uint32_t)0x000000FF) |
| #define | CEC_RXD_RXD ((uint32_t)0x000000FF) |
| #define | TIM_CR1_CEN ((uint32_t)0x00000001) |
| #define | TIM_CR1_UDIS ((uint32_t)0x00000002) |
| #define | TIM_CR1_URS ((uint32_t)0x00000004) |
| #define | TIM_CR1_OPM ((uint32_t)0x00000008) |
| #define | TIM_CR1_DIR ((uint32_t)0x00000010) |
| #define | TIM_CR1_CMS ((uint32_t)0x00000060) |
| #define | TIM_CR1_CMS_0 ((uint32_t)0x00000020) |
| #define | TIM_CR1_CMS_1 ((uint32_t)0x00000040) |
| #define | TIM_CR1_ARPE ((uint32_t)0x00000080) |
| #define | TIM_CR1_CKD ((uint32_t)0x00000300) |
| #define | TIM_CR1_CKD_0 ((uint32_t)0x00000100) |
| #define | TIM_CR1_CKD_1 ((uint32_t)0x00000200) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00000007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint32_t)0x00000001) |
| #define | TIM_DIER_CC1IE ((uint32_t)0x00000002) |
| #define | TIM_DIER_CC2IE ((uint32_t)0x00000004) |
| #define | TIM_DIER_CC3IE ((uint32_t)0x00000008) |
| #define | TIM_DIER_CC4IE ((uint32_t)0x00000010) |
| #define | TIM_DIER_COMIE ((uint32_t)0x00000020) |
| #define | TIM_DIER_TIE ((uint32_t)0x00000040) |
| #define | TIM_DIER_BIE ((uint32_t)0x00000080) |
| #define | TIM_DIER_UDE ((uint32_t)0x00000100) |
| #define | TIM_DIER_CC1DE ((uint32_t)0x00000200) |
| #define | TIM_DIER_CC2DE ((uint32_t)0x00000400) |
| #define | TIM_DIER_CC3DE ((uint32_t)0x00000800) |
| #define | TIM_DIER_CC4DE ((uint32_t)0x00001000) |
| #define | TIM_DIER_COMDE ((uint32_t)0x00002000) |
| #define | TIM_DIER_TDE ((uint32_t)0x00004000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_EGR_UG ((uint32_t)0x00000001) |
| #define | TIM_EGR_CC1G ((uint32_t)0x00000002) |
| #define | TIM_EGR_CC2G ((uint32_t)0x00000004) |
| #define | TIM_EGR_CC3G ((uint32_t)0x00000008) |
| #define | TIM_EGR_CC4G ((uint32_t)0x00000010) |
| #define | TIM_EGR_COMG ((uint32_t)0x00000020) |
| #define | TIM_EGR_TG ((uint32_t)0x00000040) |
| #define | TIM_EGR_BG ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00000070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x00007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_PSC_PSC ((uint32_t)0x0000FFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint32_t)0x000000FF) |
| #define | TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_DCR_DBA ((uint32_t)0x0000001F) |
| #define | TIM_DCR_DBA_0 ((uint32_t)0x00000001) |
| #define | TIM_DCR_DBA_1 ((uint32_t)0x00000002) |
| #define | TIM_DCR_DBA_2 ((uint32_t)0x00000004) |
| #define | TIM_DCR_DBA_3 ((uint32_t)0x00000008) |
| #define | TIM_DCR_DBA_4 ((uint32_t)0x00000010) |
| #define | TIM_DCR_DBL ((uint32_t)0x00001F00) |
| #define | TIM_DCR_DBL_0 ((uint32_t)0x00000100) |
| #define | TIM_DCR_DBL_1 ((uint32_t)0x00000200) |
| #define | TIM_DCR_DBL_2 ((uint32_t)0x00000400) |
| #define | TIM_DCR_DBL_3 ((uint32_t)0x00000800) |
| #define | TIM_DCR_DBL_4 ((uint32_t)0x00001000) |
| #define | TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) |
| #define | RTC_CRH_SECIE ((uint32_t)0x00000001) |
| #define | RTC_CRH_ALRIE ((uint32_t)0x00000002) |
| #define | RTC_CRH_OWIE ((uint32_t)0x00000004) |
| #define | RTC_CRL_SECF ((uint32_t)0x00000001) |
| #define | RTC_CRL_ALRF ((uint32_t)0x00000002) |
| #define | RTC_CRL_OWF ((uint32_t)0x00000004) |
| #define | RTC_CRL_RSF ((uint32_t)0x00000008) |
| #define | RTC_CRL_CNF ((uint32_t)0x00000010) |
| #define | RTC_CRL_RTOFF ((uint32_t)0x00000020) |
| #define | RTC_PRLH_PRL ((uint32_t)0x0000000F) |
| #define | RTC_PRLL_PRL ((uint32_t)0x0000FFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) |
| #define | RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | IWDG_KR_KEY ((uint32_t)0x0000FFFF) |
| #define | IWDG_PR_PR ((uint32_t)0x00000007) |
| #define | IWDG_PR_PR_0 ((uint32_t)0x00000001) |
| #define | IWDG_PR_PR_1 ((uint32_t)0x00000002) |
| #define | IWDG_PR_PR_2 ((uint32_t)0x00000004) |
| #define | IWDG_RLR_RL ((uint32_t)0x00000FFF) |
| #define | IWDG_SR_PVU ((uint32_t)0x00000001) |
| #define | IWDG_SR_RVU ((uint32_t)0x00000002) |
| #define | WWDG_CR_T ((uint32_t)0x0000007F) |
| #define | WWDG_CR_T0 ((uint32_t)0x00000001) |
| #define | WWDG_CR_T1 ((uint32_t)0x00000002) |
| #define | WWDG_CR_T2 ((uint32_t)0x00000004) |
| #define | WWDG_CR_T3 ((uint32_t)0x00000008) |
| #define | WWDG_CR_T4 ((uint32_t)0x00000010) |
| #define | WWDG_CR_T5 ((uint32_t)0x00000020) |
| #define | WWDG_CR_T6 ((uint32_t)0x00000040) |
| #define | WWDG_CR_WDGA ((uint32_t)0x00000080) |
| #define | WWDG_CFR_W ((uint32_t)0x0000007F) |
| #define | WWDG_CFR_W0 ((uint32_t)0x00000001) |
| #define | WWDG_CFR_W1 ((uint32_t)0x00000002) |
| #define | WWDG_CFR_W2 ((uint32_t)0x00000004) |
| #define | WWDG_CFR_W3 ((uint32_t)0x00000008) |
| #define | WWDG_CFR_W4 ((uint32_t)0x00000010) |
| #define | WWDG_CFR_W5 ((uint32_t)0x00000020) |
| #define | WWDG_CFR_W6 ((uint32_t)0x00000040) |
| #define | WWDG_CFR_WDGTB ((uint32_t)0x00000180) |
| #define | WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) |
| #define | WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) |
| #define | WWDG_CFR_EWI ((uint32_t)0x00000200) |
| #define | WWDG_SR_EWIF ((uint32_t)0x00000001) |
| #define | FSMC_BCRx_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCRx_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCRx_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCRx_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCRx_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCRx_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCRx_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCRx_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCRx_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCRx_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCRx_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCRx_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCRx_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCRx_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCRx_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCRx_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCRx_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BTRx_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTRx_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTRx_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTRx_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTRx_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTRx_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTRx_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTRx_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTRx_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTRx_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTRx_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTRx_DATAST_4 ((uint32_t)0x00001000) |
| #define | FSMC_BTRx_DATAST_5 ((uint32_t)0x00002000) |
| #define | FSMC_BTRx_DATAST_6 ((uint32_t)0x00004000) |
| #define | FSMC_BTRx_DATAST_7 ((uint32_t)0x00008000) |
| #define | FSMC_BTRx_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTRx_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTRx_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTRx_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTRx_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTRx_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTRx_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTRx_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTRx_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTRx_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTRx_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTRx_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTRx_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTRx_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTRx_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTRx_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTRx_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTRx_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTRx_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTRx_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTRx_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTRx_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTRx_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTRx_DATAST_4 ((uint32_t)0x00001000) |
| #define | FSMC_BWTRx_DATAST_5 ((uint32_t)0x00002000) |
| #define | FSMC_BWTRx_DATAST_6 ((uint32_t)0x00004000) |
| #define | FSMC_BWTRx_DATAST_7 ((uint32_t)0x00008000) |
| #define | FSMC_BWTRx_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTRx_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTRx_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTRx_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTRx_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTRx_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTRx_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTRx_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTRx_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTRx_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTRx_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTRx_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTRx_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | SDIO_POWER_PWRCTRL ((uint32_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint32_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint32_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint32_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint32_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint32_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint32_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint32_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint32_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint32_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint32_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint32_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint32_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint32_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint32_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint32_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | SPI_CR1_CPHA ((uint32_t)0x00000001) |
| #define | SPI_CR1_CPOL ((uint32_t)0x00000002) |
| #define | SPI_CR1_MSTR ((uint32_t)0x00000004) |
| #define | SPI_CR1_BR ((uint32_t)0x00000038) |
| #define | SPI_CR1_BR_0 ((uint32_t)0x00000008) |
| #define | SPI_CR1_BR_1 ((uint32_t)0x00000010) |
| #define | SPI_CR1_BR_2 ((uint32_t)0x00000020) |
| #define | SPI_CR1_SPE ((uint32_t)0x00000040) |
| #define | SPI_CR1_LSBFIRST ((uint32_t)0x00000080) |
| #define | SPI_CR1_SSI ((uint32_t)0x00000100) |
| #define | SPI_CR1_SSM ((uint32_t)0x00000200) |
| #define | SPI_CR1_RXONLY ((uint32_t)0x00000400) |
| #define | SPI_CR1_DFF ((uint32_t)0x00000800) |
| #define | SPI_CR1_CRCNEXT ((uint32_t)0x00001000) |
| #define | SPI_CR1_CRCEN ((uint32_t)0x00002000) |
| #define | SPI_CR1_BIDIOE ((uint32_t)0x00004000) |
| #define | SPI_CR1_BIDIMODE ((uint32_t)0x00008000) |
| #define | SPI_CR2_RXDMAEN ((uint32_t)0x00000001) |
| #define | SPI_CR2_TXDMAEN ((uint32_t)0x00000002) |
| #define | SPI_CR2_SSOE ((uint32_t)0x00000004) |
| #define | SPI_CR2_ERRIE ((uint32_t)0x00000020) |
| #define | SPI_CR2_RXNEIE ((uint32_t)0x00000040) |
| #define | SPI_CR2_TXEIE ((uint32_t)0x00000080) |
| #define | SPI_SR_RXNE ((uint32_t)0x00000001) |
| #define | SPI_SR_TXE ((uint32_t)0x00000002) |
| #define | SPI_SR_CHSIDE ((uint32_t)0x00000004) |
| #define | SPI_SR_UDR ((uint32_t)0x00000008) |
| #define | SPI_SR_CRCERR ((uint32_t)0x00000010) |
| #define | SPI_SR_MODF ((uint32_t)0x00000020) |
| #define | SPI_SR_OVR ((uint32_t)0x00000040) |
| #define | SPI_SR_BSY ((uint32_t)0x00000080) |
| #define | SPI_DR_DR ((uint32_t)0x0000FFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_SMBUS ((uint32_t)0x00000002) |
| #define | I2C_CR1_SMBTYPE ((uint32_t)0x00000008) |
| #define | I2C_CR1_ENARP ((uint32_t)0x00000010) |
| #define | I2C_CR1_ENPEC ((uint32_t)0x00000020) |
| #define | I2C_CR1_ENGC ((uint32_t)0x00000040) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) |
| #define | I2C_CR1_START ((uint32_t)0x00000100) |
| #define | I2C_CR1_STOP ((uint32_t)0x00000200) |
| #define | I2C_CR1_ACK ((uint32_t)0x00000400) |
| #define | I2C_CR1_POS ((uint32_t)0x00000800) |
| #define | I2C_CR1_PEC ((uint32_t)0x00001000) |
| #define | I2C_CR1_ALERT ((uint32_t)0x00002000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00008000) |
| #define | I2C_CR2_FREQ ((uint32_t)0x0000003F) |
| #define | I2C_CR2_FREQ_0 ((uint32_t)0x00000001) |
| #define | I2C_CR2_FREQ_1 ((uint32_t)0x00000002) |
| #define | I2C_CR2_FREQ_2 ((uint32_t)0x00000004) |
| #define | I2C_CR2_FREQ_3 ((uint32_t)0x00000008) |
| #define | I2C_CR2_FREQ_4 ((uint32_t)0x00000010) |
| #define | I2C_CR2_FREQ_5 ((uint32_t)0x00000020) |
| #define | I2C_CR2_ITERREN ((uint32_t)0x00000100) |
| #define | I2C_CR2_ITEVTEN ((uint32_t)0x00000200) |
| #define | I2C_CR2_ITBUFEN ((uint32_t)0x00000400) |
| #define | I2C_CR2_DMAEN ((uint32_t)0x00000800) |
| #define | I2C_CR2_LAST ((uint32_t)0x00001000) |
| #define | I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) |
| #define | I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) |
| #define | I2C_OAR1_ADD0 ((uint32_t)0x00000001) |
| #define | I2C_OAR1_ADD1 ((uint32_t)0x00000002) |
| #define | I2C_OAR1_ADD2 ((uint32_t)0x00000004) |
| #define | I2C_OAR1_ADD3 ((uint32_t)0x00000008) |
| #define | I2C_OAR1_ADD4 ((uint32_t)0x00000010) |
| #define | I2C_OAR1_ADD5 ((uint32_t)0x00000020) |
| #define | I2C_OAR1_ADD6 ((uint32_t)0x00000040) |
| #define | I2C_OAR1_ADD7 ((uint32_t)0x00000080) |
| #define | I2C_OAR1_ADD8 ((uint32_t)0x00000100) |
| #define | I2C_OAR1_ADD9 ((uint32_t)0x00000200) |
| #define | I2C_OAR1_ADDMODE ((uint32_t)0x00008000) |
| #define | I2C_OAR2_ENDUAL ((uint32_t)0x00000001) |
| #define | I2C_OAR2_ADD2 ((uint32_t)0x000000FE) |
| #define | I2C_SR1_SB ((uint32_t)0x00000001) |
| #define | I2C_SR1_ADDR ((uint32_t)0x00000002) |
| #define | I2C_SR1_BTF ((uint32_t)0x00000004) |
| #define | I2C_SR1_ADD10 ((uint32_t)0x00000008) |
| #define | I2C_SR1_STOPF ((uint32_t)0x00000010) |
| #define | I2C_SR1_RXNE ((uint32_t)0x00000040) |
| #define | I2C_SR1_TXE ((uint32_t)0x00000080) |
| #define | I2C_SR1_BERR ((uint32_t)0x00000100) |
| #define | I2C_SR1_ARLO ((uint32_t)0x00000200) |
| #define | I2C_SR1_AF ((uint32_t)0x00000400) |
| #define | I2C_SR1_OVR ((uint32_t)0x00000800) |
| #define | I2C_SR1_PECERR ((uint32_t)0x00001000) |
| #define | I2C_SR1_TIMEOUT ((uint32_t)0x00004000) |
| #define | I2C_SR1_SMBALERT ((uint32_t)0x00008000) |
| #define | I2C_SR2_MSL ((uint32_t)0x00000001) |
| #define | I2C_SR2_BUSY ((uint32_t)0x00000002) |
| #define | I2C_SR2_TRA ((uint32_t)0x00000004) |
| #define | I2C_SR2_GENCALL ((uint32_t)0x00000010) |
| #define | I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) |
| #define | I2C_SR2_SMBHOST ((uint32_t)0x00000040) |
| #define | I2C_SR2_DUALF ((uint32_t)0x00000080) |
| #define | I2C_SR2_PEC ((uint32_t)0x0000FF00) |
| #define | I2C_CCR_CCR ((uint32_t)0x00000FFF) |
| #define | I2C_CCR_DUTY ((uint32_t)0x00004000) |
| #define | I2C_CCR_FS ((uint32_t)0x00008000) |
| #define | I2C_TRISE_TRISE ((uint32_t)0x0000003F) |
| #define | USART_SR_PE ((uint32_t)0x00000001) |
| #define | USART_SR_FE ((uint32_t)0x00000002) |
| #define | USART_SR_NE ((uint32_t)0x00000004) |
| #define | USART_SR_ORE ((uint32_t)0x00000008) |
| #define | USART_SR_IDLE ((uint32_t)0x00000010) |
| #define | USART_SR_RXNE ((uint32_t)0x00000020) |
| #define | USART_SR_TC ((uint32_t)0x00000040) |
| #define | USART_SR_TXE ((uint32_t)0x00000080) |
| #define | USART_SR_LBD ((uint32_t)0x00000100) |
| #define | USART_SR_CTS ((uint32_t)0x00000200) |
| #define | USART_DR_DR ((uint32_t)0x000001FF) |
| #define | USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) |
| #define | USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) |
| #define | USART_CR1_SBK ((uint32_t)0x00000001) |
| #define | USART_CR1_RWU ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_UE ((uint32_t)0x00002000) |
| #define | USART_CR2_ADD ((uint32_t)0x0000000F) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_GTPR_PSC ((uint32_t)0x000000FF) |
| #define | USART_GTPR_PSC_0 ((uint32_t)0x00000001) |
| #define | USART_GTPR_PSC_1 ((uint32_t)0x00000002) |
| #define | USART_GTPR_PSC_2 ((uint32_t)0x00000004) |
| #define | USART_GTPR_PSC_3 ((uint32_t)0x00000008) |
| #define | USART_GTPR_PSC_4 ((uint32_t)0x00000010) |
| #define | USART_GTPR_PSC_5 ((uint32_t)0x00000020) |
| #define | USART_GTPR_PSC_6 ((uint32_t)0x00000040) |
| #define | USART_GTPR_PSC_7 ((uint32_t)0x00000080) |
| #define | USART_GTPR_GT ((uint32_t)0x0000FF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) |
| #define | DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) |
| #define | DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) |
| #define | DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) |
| #define | DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) |
| #define | DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) |
| #define | DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) |
| #define | DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) |
| #define | DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) |
| #define | DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) |
| #define | FLASH_ACR_HLFCYA ((uint32_t)0x00000008) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint32_t)0x000000A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT ((uint32_t)0x00000002) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) |
| #define | FLASH_OBR_USER ((uint32_t)0x0000001C) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) |
| #define | FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) |
| #define | FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) |
| #define | FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint32_t)0x000000FF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V2 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_2V3 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_2V4 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2V5 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_2V6 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | BKP_DR1_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR2_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR3_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR4_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR5_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR6_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR7_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR8_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR9_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR10_D ((uint32_t)0x0000FFFF) |
| #define | RTC_BKP_NUMBER 10 |
| #define | BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
| #define | BKP_RTCCR_CCO ((uint32_t)0x00000080) |
| #define | BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
| #define | BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
| #define | BKP_CR_TPE ((uint32_t)0x00000001) |
| #define | BKP_CR_TPAL ((uint32_t)0x00000002) |
| #define | BKP_CSR_CTE ((uint32_t)0x00000001) |
| #define | BKP_CSR_CTI ((uint32_t)0x00000002) |
| #define | BKP_CSR_TPIE ((uint32_t)0x00000004) |
| #define | BKP_CSR_TEF ((uint32_t)0x00000100) |
| #define | BKP_CSR_TIF ((uint32_t)0x00000200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint32_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint32_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint32_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint32_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint32_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint32_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint32_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint32_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint32_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint32_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint32_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint32_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint32_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint32_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint32_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint32_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint32_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint32_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint32_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint32_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint32_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint32_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint32_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint32_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint32_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint32_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint32_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint32_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint32_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint32_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint32_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint32_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint32_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint32_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint32_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint32_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint32_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint32_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint32_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint32_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint32_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint32_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint32_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint32_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint32_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint32_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint32_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint32_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
| #define | AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
| #define | AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
| #define | AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
| #define | AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
| #define | AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PORT ((uint32_t)0x00000070) |
| #define | AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
| #define | AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) |
| #define | SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) |
| #define | SCB_SCR_SEVONPEND ((uint32_t)0x00000010) |
| #define | SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) |
| #define | SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) |
| #define | SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) |
| #define | SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) |
| #define | SCB_CCR_STKALIGN ((uint32_t)0x00000200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint32_t)0x00000001) |
| #define | SCB_DFSR_BKPT ((uint32_t)0x00000002) |
| #define | SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) |
| #define | SCB_DFSR_VCATCH ((uint32_t)0x00000008) |
| #define | SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | TIM_CR1_CEN ((uint32_t)0x00000001) |
| #define | TIM_CR1_UDIS ((uint32_t)0x00000002) |
| #define | TIM_CR1_URS ((uint32_t)0x00000004) |
| #define | TIM_CR1_OPM ((uint32_t)0x00000008) |
| #define | TIM_CR1_DIR ((uint32_t)0x00000010) |
| #define | TIM_CR1_CMS ((uint32_t)0x00000060) |
| #define | TIM_CR1_CMS_0 ((uint32_t)0x00000020) |
| #define | TIM_CR1_CMS_1 ((uint32_t)0x00000040) |
| #define | TIM_CR1_ARPE ((uint32_t)0x00000080) |
| #define | TIM_CR1_CKD ((uint32_t)0x00000300) |
| #define | TIM_CR1_CKD_0 ((uint32_t)0x00000100) |
| #define | TIM_CR1_CKD_1 ((uint32_t)0x00000200) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00000007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint32_t)0x00000001) |
| #define | TIM_DIER_CC1IE ((uint32_t)0x00000002) |
| #define | TIM_DIER_CC2IE ((uint32_t)0x00000004) |
| #define | TIM_DIER_CC3IE ((uint32_t)0x00000008) |
| #define | TIM_DIER_CC4IE ((uint32_t)0x00000010) |
| #define | TIM_DIER_COMIE ((uint32_t)0x00000020) |
| #define | TIM_DIER_TIE ((uint32_t)0x00000040) |
| #define | TIM_DIER_BIE ((uint32_t)0x00000080) |
| #define | TIM_DIER_UDE ((uint32_t)0x00000100) |
| #define | TIM_DIER_CC1DE ((uint32_t)0x00000200) |
| #define | TIM_DIER_CC2DE ((uint32_t)0x00000400) |
| #define | TIM_DIER_CC3DE ((uint32_t)0x00000800) |
| #define | TIM_DIER_CC4DE ((uint32_t)0x00001000) |
| #define | TIM_DIER_COMDE ((uint32_t)0x00002000) |
| #define | TIM_DIER_TDE ((uint32_t)0x00004000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_EGR_UG ((uint32_t)0x00000001) |
| #define | TIM_EGR_CC1G ((uint32_t)0x00000002) |
| #define | TIM_EGR_CC2G ((uint32_t)0x00000004) |
| #define | TIM_EGR_CC3G ((uint32_t)0x00000008) |
| #define | TIM_EGR_CC4G ((uint32_t)0x00000010) |
| #define | TIM_EGR_COMG ((uint32_t)0x00000020) |
| #define | TIM_EGR_TG ((uint32_t)0x00000040) |
| #define | TIM_EGR_BG ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00000070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x00007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_PSC_PSC ((uint32_t)0x0000FFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint32_t)0x000000FF) |
| #define | TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_DCR_DBA ((uint32_t)0x0000001F) |
| #define | TIM_DCR_DBA_0 ((uint32_t)0x00000001) |
| #define | TIM_DCR_DBA_1 ((uint32_t)0x00000002) |
| #define | TIM_DCR_DBA_2 ((uint32_t)0x00000004) |
| #define | TIM_DCR_DBA_3 ((uint32_t)0x00000008) |
| #define | TIM_DCR_DBA_4 ((uint32_t)0x00000010) |
| #define | TIM_DCR_DBL ((uint32_t)0x00001F00) |
| #define | TIM_DCR_DBL_0 ((uint32_t)0x00000100) |
| #define | TIM_DCR_DBL_1 ((uint32_t)0x00000200) |
| #define | TIM_DCR_DBL_2 ((uint32_t)0x00000400) |
| #define | TIM_DCR_DBL_3 ((uint32_t)0x00000800) |
| #define | TIM_DCR_DBL_4 ((uint32_t)0x00001000) |
| #define | TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) |
| #define | RTC_CRH_SECIE ((uint32_t)0x00000001) |
| #define | RTC_CRH_ALRIE ((uint32_t)0x00000002) |
| #define | RTC_CRH_OWIE ((uint32_t)0x00000004) |
| #define | RTC_CRL_SECF ((uint32_t)0x00000001) |
| #define | RTC_CRL_ALRF ((uint32_t)0x00000002) |
| #define | RTC_CRL_OWF ((uint32_t)0x00000004) |
| #define | RTC_CRL_RSF ((uint32_t)0x00000008) |
| #define | RTC_CRL_CNF ((uint32_t)0x00000010) |
| #define | RTC_CRL_RTOFF ((uint32_t)0x00000020) |
| #define | RTC_PRLH_PRL ((uint32_t)0x0000000F) |
| #define | RTC_PRLL_PRL ((uint32_t)0x0000FFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) |
| #define | RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | IWDG_KR_KEY ((uint32_t)0x0000FFFF) |
| #define | IWDG_PR_PR ((uint32_t)0x00000007) |
| #define | IWDG_PR_PR_0 ((uint32_t)0x00000001) |
| #define | IWDG_PR_PR_1 ((uint32_t)0x00000002) |
| #define | IWDG_PR_PR_2 ((uint32_t)0x00000004) |
| #define | IWDG_RLR_RL ((uint32_t)0x00000FFF) |
| #define | IWDG_SR_PVU ((uint32_t)0x00000001) |
| #define | IWDG_SR_RVU ((uint32_t)0x00000002) |
| #define | WWDG_CR_T ((uint32_t)0x0000007F) |
| #define | WWDG_CR_T0 ((uint32_t)0x00000001) |
| #define | WWDG_CR_T1 ((uint32_t)0x00000002) |
| #define | WWDG_CR_T2 ((uint32_t)0x00000004) |
| #define | WWDG_CR_T3 ((uint32_t)0x00000008) |
| #define | WWDG_CR_T4 ((uint32_t)0x00000010) |
| #define | WWDG_CR_T5 ((uint32_t)0x00000020) |
| #define | WWDG_CR_T6 ((uint32_t)0x00000040) |
| #define | WWDG_CR_WDGA ((uint32_t)0x00000080) |
| #define | WWDG_CFR_W ((uint32_t)0x0000007F) |
| #define | WWDG_CFR_W0 ((uint32_t)0x00000001) |
| #define | WWDG_CFR_W1 ((uint32_t)0x00000002) |
| #define | WWDG_CFR_W2 ((uint32_t)0x00000004) |
| #define | WWDG_CFR_W3 ((uint32_t)0x00000008) |
| #define | WWDG_CFR_W4 ((uint32_t)0x00000010) |
| #define | WWDG_CFR_W5 ((uint32_t)0x00000020) |
| #define | WWDG_CFR_W6 ((uint32_t)0x00000040) |
| #define | WWDG_CFR_WDGTB ((uint32_t)0x00000180) |
| #define | WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) |
| #define | WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) |
| #define | WWDG_CFR_EWI ((uint32_t)0x00000200) |
| #define | WWDG_SR_EWIF ((uint32_t)0x00000001) |
| #define | SDIO_POWER_PWRCTRL ((uint32_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint32_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint32_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint32_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint32_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint32_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint32_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint32_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint32_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint32_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint32_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint32_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint32_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint32_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint32_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint32_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | SPI_CR1_CPHA ((uint32_t)0x00000001) |
| #define | SPI_CR1_CPOL ((uint32_t)0x00000002) |
| #define | SPI_CR1_MSTR ((uint32_t)0x00000004) |
| #define | SPI_CR1_BR ((uint32_t)0x00000038) |
| #define | SPI_CR1_BR_0 ((uint32_t)0x00000008) |
| #define | SPI_CR1_BR_1 ((uint32_t)0x00000010) |
| #define | SPI_CR1_BR_2 ((uint32_t)0x00000020) |
| #define | SPI_CR1_SPE ((uint32_t)0x00000040) |
| #define | SPI_CR1_LSBFIRST ((uint32_t)0x00000080) |
| #define | SPI_CR1_SSI ((uint32_t)0x00000100) |
| #define | SPI_CR1_SSM ((uint32_t)0x00000200) |
| #define | SPI_CR1_RXONLY ((uint32_t)0x00000400) |
| #define | SPI_CR1_DFF ((uint32_t)0x00000800) |
| #define | SPI_CR1_CRCNEXT ((uint32_t)0x00001000) |
| #define | SPI_CR1_CRCEN ((uint32_t)0x00002000) |
| #define | SPI_CR1_BIDIOE ((uint32_t)0x00004000) |
| #define | SPI_CR1_BIDIMODE ((uint32_t)0x00008000) |
| #define | SPI_CR2_RXDMAEN ((uint32_t)0x00000001) |
| #define | SPI_CR2_TXDMAEN ((uint32_t)0x00000002) |
| #define | SPI_CR2_SSOE ((uint32_t)0x00000004) |
| #define | SPI_CR2_ERRIE ((uint32_t)0x00000020) |
| #define | SPI_CR2_RXNEIE ((uint32_t)0x00000040) |
| #define | SPI_CR2_TXEIE ((uint32_t)0x00000080) |
| #define | SPI_SR_RXNE ((uint32_t)0x00000001) |
| #define | SPI_SR_TXE ((uint32_t)0x00000002) |
| #define | SPI_SR_CHSIDE ((uint32_t)0x00000004) |
| #define | SPI_SR_UDR ((uint32_t)0x00000008) |
| #define | SPI_SR_CRCERR ((uint32_t)0x00000010) |
| #define | SPI_SR_MODF ((uint32_t)0x00000020) |
| #define | SPI_SR_OVR ((uint32_t)0x00000040) |
| #define | SPI_SR_BSY ((uint32_t)0x00000080) |
| #define | SPI_DR_DR ((uint32_t)0x0000FFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_SMBUS ((uint32_t)0x00000002) |
| #define | I2C_CR1_SMBTYPE ((uint32_t)0x00000008) |
| #define | I2C_CR1_ENARP ((uint32_t)0x00000010) |
| #define | I2C_CR1_ENPEC ((uint32_t)0x00000020) |
| #define | I2C_CR1_ENGC ((uint32_t)0x00000040) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) |
| #define | I2C_CR1_START ((uint32_t)0x00000100) |
| #define | I2C_CR1_STOP ((uint32_t)0x00000200) |
| #define | I2C_CR1_ACK ((uint32_t)0x00000400) |
| #define | I2C_CR1_POS ((uint32_t)0x00000800) |
| #define | I2C_CR1_PEC ((uint32_t)0x00001000) |
| #define | I2C_CR1_ALERT ((uint32_t)0x00002000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00008000) |
| #define | I2C_CR2_FREQ ((uint32_t)0x0000003F) |
| #define | I2C_CR2_FREQ_0 ((uint32_t)0x00000001) |
| #define | I2C_CR2_FREQ_1 ((uint32_t)0x00000002) |
| #define | I2C_CR2_FREQ_2 ((uint32_t)0x00000004) |
| #define | I2C_CR2_FREQ_3 ((uint32_t)0x00000008) |
| #define | I2C_CR2_FREQ_4 ((uint32_t)0x00000010) |
| #define | I2C_CR2_FREQ_5 ((uint32_t)0x00000020) |
| #define | I2C_CR2_ITERREN ((uint32_t)0x00000100) |
| #define | I2C_CR2_ITEVTEN ((uint32_t)0x00000200) |
| #define | I2C_CR2_ITBUFEN ((uint32_t)0x00000400) |
| #define | I2C_CR2_DMAEN ((uint32_t)0x00000800) |
| #define | I2C_CR2_LAST ((uint32_t)0x00001000) |
| #define | I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) |
| #define | I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) |
| #define | I2C_OAR1_ADD0 ((uint32_t)0x00000001) |
| #define | I2C_OAR1_ADD1 ((uint32_t)0x00000002) |
| #define | I2C_OAR1_ADD2 ((uint32_t)0x00000004) |
| #define | I2C_OAR1_ADD3 ((uint32_t)0x00000008) |
| #define | I2C_OAR1_ADD4 ((uint32_t)0x00000010) |
| #define | I2C_OAR1_ADD5 ((uint32_t)0x00000020) |
| #define | I2C_OAR1_ADD6 ((uint32_t)0x00000040) |
| #define | I2C_OAR1_ADD7 ((uint32_t)0x00000080) |
| #define | I2C_OAR1_ADD8 ((uint32_t)0x00000100) |
| #define | I2C_OAR1_ADD9 ((uint32_t)0x00000200) |
| #define | I2C_OAR1_ADDMODE ((uint32_t)0x00008000) |
| #define | I2C_OAR2_ENDUAL ((uint32_t)0x00000001) |
| #define | I2C_OAR2_ADD2 ((uint32_t)0x000000FE) |
| #define | I2C_SR1_SB ((uint32_t)0x00000001) |
| #define | I2C_SR1_ADDR ((uint32_t)0x00000002) |
| #define | I2C_SR1_BTF ((uint32_t)0x00000004) |
| #define | I2C_SR1_ADD10 ((uint32_t)0x00000008) |
| #define | I2C_SR1_STOPF ((uint32_t)0x00000010) |
| #define | I2C_SR1_RXNE ((uint32_t)0x00000040) |
| #define | I2C_SR1_TXE ((uint32_t)0x00000080) |
| #define | I2C_SR1_BERR ((uint32_t)0x00000100) |
| #define | I2C_SR1_ARLO ((uint32_t)0x00000200) |
| #define | I2C_SR1_AF ((uint32_t)0x00000400) |
| #define | I2C_SR1_OVR ((uint32_t)0x00000800) |
| #define | I2C_SR1_PECERR ((uint32_t)0x00001000) |
| #define | I2C_SR1_TIMEOUT ((uint32_t)0x00004000) |
| #define | I2C_SR1_SMBALERT ((uint32_t)0x00008000) |
| #define | I2C_SR2_MSL ((uint32_t)0x00000001) |
| #define | I2C_SR2_BUSY ((uint32_t)0x00000002) |
| #define | I2C_SR2_TRA ((uint32_t)0x00000004) |
| #define | I2C_SR2_GENCALL ((uint32_t)0x00000010) |
| #define | I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) |
| #define | I2C_SR2_SMBHOST ((uint32_t)0x00000040) |
| #define | I2C_SR2_DUALF ((uint32_t)0x00000080) |
| #define | I2C_SR2_PEC ((uint32_t)0x0000FF00) |
| #define | I2C_CCR_CCR ((uint32_t)0x00000FFF) |
| #define | I2C_CCR_DUTY ((uint32_t)0x00004000) |
| #define | I2C_CCR_FS ((uint32_t)0x00008000) |
| #define | I2C_TRISE_TRISE ((uint32_t)0x0000003F) |
| #define | USART_SR_PE ((uint32_t)0x00000001) |
| #define | USART_SR_FE ((uint32_t)0x00000002) |
| #define | USART_SR_NE ((uint32_t)0x00000004) |
| #define | USART_SR_ORE ((uint32_t)0x00000008) |
| #define | USART_SR_IDLE ((uint32_t)0x00000010) |
| #define | USART_SR_RXNE ((uint32_t)0x00000020) |
| #define | USART_SR_TC ((uint32_t)0x00000040) |
| #define | USART_SR_TXE ((uint32_t)0x00000080) |
| #define | USART_SR_LBD ((uint32_t)0x00000100) |
| #define | USART_SR_CTS ((uint32_t)0x00000200) |
| #define | USART_DR_DR ((uint32_t)0x000001FF) |
| #define | USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) |
| #define | USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) |
| #define | USART_CR1_SBK ((uint32_t)0x00000001) |
| #define | USART_CR1_RWU ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_UE ((uint32_t)0x00002000) |
| #define | USART_CR2_ADD ((uint32_t)0x0000000F) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_GTPR_PSC ((uint32_t)0x000000FF) |
| #define | USART_GTPR_PSC_0 ((uint32_t)0x00000001) |
| #define | USART_GTPR_PSC_1 ((uint32_t)0x00000002) |
| #define | USART_GTPR_PSC_2 ((uint32_t)0x00000004) |
| #define | USART_GTPR_PSC_3 ((uint32_t)0x00000008) |
| #define | USART_GTPR_PSC_4 ((uint32_t)0x00000010) |
| #define | USART_GTPR_PSC_5 ((uint32_t)0x00000020) |
| #define | USART_GTPR_PSC_6 ((uint32_t)0x00000040) |
| #define | USART_GTPR_PSC_7 ((uint32_t)0x00000080) |
| #define | USART_GTPR_GT ((uint32_t)0x0000FF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) |
| #define | FLASH_ACR_HLFCYA ((uint32_t)0x00000008) |
| #define | FLASH_ACR_PRFTBE ((uint32_t)0x00000010) |
| #define | FLASH_ACR_PRFTBS ((uint32_t)0x00000020) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint32_t)0x000000A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT ((uint32_t)0x00000002) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) |
| #define | FLASH_OBR_USER ((uint32_t)0x0000001C) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) |
| #define | FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) |
| #define | FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) |
| #define | FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint32_t)0x000000FF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V2 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_2V3 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_2V4 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2V5 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_2V6 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | BKP_DR1_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR2_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR3_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR4_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR5_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR6_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR7_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR8_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR9_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR10_D ((uint32_t)0x0000FFFF) |
| #define | RTC_BKP_NUMBER 10 |
| #define | BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
| #define | BKP_RTCCR_CCO ((uint32_t)0x00000080) |
| #define | BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
| #define | BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
| #define | BKP_CR_TPE ((uint32_t)0x00000001) |
| #define | BKP_CR_TPAL ((uint32_t)0x00000002) |
| #define | BKP_CSR_CTE ((uint32_t)0x00000001) |
| #define | BKP_CSR_CTI ((uint32_t)0x00000002) |
| #define | BKP_CSR_TPIE ((uint32_t)0x00000004) |
| #define | BKP_CSR_TEF ((uint32_t)0x00000100) |
| #define | BKP_CSR_TIF ((uint32_t)0x00000200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint32_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint32_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint32_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint32_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint32_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint32_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint32_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint32_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint32_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint32_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint32_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint32_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint32_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint32_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint32_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint32_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint32_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint32_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint32_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint32_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint32_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint32_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint32_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint32_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint32_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint32_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint32_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint32_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint32_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint32_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint32_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint32_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint32_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint32_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint32_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint32_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint32_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint32_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint32_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint32_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint32_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint32_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint32_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint32_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint32_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint32_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint32_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint32_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
| #define | AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
| #define | AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
| #define | AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
| #define | AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
| #define | AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PORT ((uint32_t)0x00000070) |
| #define | AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
| #define | AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
| #define | AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) |
| #define | SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) |
| #define | SCB_SCR_SEVONPEND ((uint32_t)0x00000010) |
| #define | SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) |
| #define | SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) |
| #define | SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) |
| #define | SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) |
| #define | SCB_CCR_STKALIGN ((uint32_t)0x00000200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint32_t)0x00000001) |
| #define | SCB_DFSR_BKPT ((uint32_t)0x00000002) |
| #define | SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) |
| #define | SCB_DFSR_VCATCH ((uint32_t)0x00000008) |
| #define | SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | TIM_CR1_CEN ((uint32_t)0x00000001) |
| #define | TIM_CR1_UDIS ((uint32_t)0x00000002) |
| #define | TIM_CR1_URS ((uint32_t)0x00000004) |
| #define | TIM_CR1_OPM ((uint32_t)0x00000008) |
| #define | TIM_CR1_DIR ((uint32_t)0x00000010) |
| #define | TIM_CR1_CMS ((uint32_t)0x00000060) |
| #define | TIM_CR1_CMS_0 ((uint32_t)0x00000020) |
| #define | TIM_CR1_CMS_1 ((uint32_t)0x00000040) |
| #define | TIM_CR1_ARPE ((uint32_t)0x00000080) |
| #define | TIM_CR1_CKD ((uint32_t)0x00000300) |
| #define | TIM_CR1_CKD_0 ((uint32_t)0x00000100) |
| #define | TIM_CR1_CKD_1 ((uint32_t)0x00000200) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00000007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint32_t)0x00000001) |
| #define | TIM_DIER_CC1IE ((uint32_t)0x00000002) |
| #define | TIM_DIER_CC2IE ((uint32_t)0x00000004) |
| #define | TIM_DIER_CC3IE ((uint32_t)0x00000008) |
| #define | TIM_DIER_CC4IE ((uint32_t)0x00000010) |
| #define | TIM_DIER_COMIE ((uint32_t)0x00000020) |
| #define | TIM_DIER_TIE ((uint32_t)0x00000040) |
| #define | TIM_DIER_BIE ((uint32_t)0x00000080) |
| #define | TIM_DIER_UDE ((uint32_t)0x00000100) |
| #define | TIM_DIER_CC1DE ((uint32_t)0x00000200) |
| #define | TIM_DIER_CC2DE ((uint32_t)0x00000400) |
| #define | TIM_DIER_CC3DE ((uint32_t)0x00000800) |
| #define | TIM_DIER_CC4DE ((uint32_t)0x00001000) |
| #define | TIM_DIER_COMDE ((uint32_t)0x00002000) |
| #define | TIM_DIER_TDE ((uint32_t)0x00004000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_EGR_UG ((uint32_t)0x00000001) |
| #define | TIM_EGR_CC1G ((uint32_t)0x00000002) |
| #define | TIM_EGR_CC2G ((uint32_t)0x00000004) |
| #define | TIM_EGR_CC3G ((uint32_t)0x00000008) |
| #define | TIM_EGR_CC4G ((uint32_t)0x00000010) |
| #define | TIM_EGR_COMG ((uint32_t)0x00000020) |
| #define | TIM_EGR_TG ((uint32_t)0x00000040) |
| #define | TIM_EGR_BG ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00000070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x00007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_PSC_PSC ((uint32_t)0x0000FFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint32_t)0x000000FF) |
| #define | TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_DCR_DBA ((uint32_t)0x0000001F) |
| #define | TIM_DCR_DBA_0 ((uint32_t)0x00000001) |
| #define | TIM_DCR_DBA_1 ((uint32_t)0x00000002) |
| #define | TIM_DCR_DBA_2 ((uint32_t)0x00000004) |
| #define | TIM_DCR_DBA_3 ((uint32_t)0x00000008) |
| #define | TIM_DCR_DBA_4 ((uint32_t)0x00000010) |
| #define | TIM_DCR_DBL ((uint32_t)0x00001F00) |
| #define | TIM_DCR_DBL_0 ((uint32_t)0x00000100) |
| #define | TIM_DCR_DBL_1 ((uint32_t)0x00000200) |
| #define | TIM_DCR_DBL_2 ((uint32_t)0x00000400) |
| #define | TIM_DCR_DBL_3 ((uint32_t)0x00000800) |
| #define | TIM_DCR_DBL_4 ((uint32_t)0x00001000) |
| #define | TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) |
| #define | RTC_CRH_SECIE ((uint32_t)0x00000001) |
| #define | RTC_CRH_ALRIE ((uint32_t)0x00000002) |
| #define | RTC_CRH_OWIE ((uint32_t)0x00000004) |
| #define | RTC_CRL_SECF ((uint32_t)0x00000001) |
| #define | RTC_CRL_ALRF ((uint32_t)0x00000002) |
| #define | RTC_CRL_OWF ((uint32_t)0x00000004) |
| #define | RTC_CRL_RSF ((uint32_t)0x00000008) |
| #define | RTC_CRL_CNF ((uint32_t)0x00000010) |
| #define | RTC_CRL_RTOFF ((uint32_t)0x00000020) |
| #define | RTC_PRLH_PRL ((uint32_t)0x0000000F) |
| #define | RTC_PRLL_PRL ((uint32_t)0x0000FFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) |
| #define | RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | IWDG_KR_KEY ((uint32_t)0x0000FFFF) |
| #define | IWDG_PR_PR ((uint32_t)0x00000007) |
| #define | IWDG_PR_PR_0 ((uint32_t)0x00000001) |
| #define | IWDG_PR_PR_1 ((uint32_t)0x00000002) |
| #define | IWDG_PR_PR_2 ((uint32_t)0x00000004) |
| #define | IWDG_RLR_RL ((uint32_t)0x00000FFF) |
| #define | IWDG_SR_PVU ((uint32_t)0x00000001) |
| #define | IWDG_SR_RVU ((uint32_t)0x00000002) |
| #define | WWDG_CR_T ((uint32_t)0x0000007F) |
| #define | WWDG_CR_T0 ((uint32_t)0x00000001) |
| #define | WWDG_CR_T1 ((uint32_t)0x00000002) |
| #define | WWDG_CR_T2 ((uint32_t)0x00000004) |
| #define | WWDG_CR_T3 ((uint32_t)0x00000008) |
| #define | WWDG_CR_T4 ((uint32_t)0x00000010) |
| #define | WWDG_CR_T5 ((uint32_t)0x00000020) |
| #define | WWDG_CR_T6 ((uint32_t)0x00000040) |
| #define | WWDG_CR_WDGA ((uint32_t)0x00000080) |
| #define | WWDG_CFR_W ((uint32_t)0x0000007F) |
| #define | WWDG_CFR_W0 ((uint32_t)0x00000001) |
| #define | WWDG_CFR_W1 ((uint32_t)0x00000002) |
| #define | WWDG_CFR_W2 ((uint32_t)0x00000004) |
| #define | WWDG_CFR_W3 ((uint32_t)0x00000008) |
| #define | WWDG_CFR_W4 ((uint32_t)0x00000010) |
| #define | WWDG_CFR_W5 ((uint32_t)0x00000020) |
| #define | WWDG_CFR_W6 ((uint32_t)0x00000040) |
| #define | WWDG_CFR_WDGTB ((uint32_t)0x00000180) |
| #define | WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) |
| #define | WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) |
| #define | WWDG_CFR_EWI ((uint32_t)0x00000200) |
| #define | WWDG_SR_EWIF ((uint32_t)0x00000001) |
| #define | SDIO_POWER_PWRCTRL ((uint32_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint32_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint32_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint32_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint32_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint32_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint32_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint32_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint32_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint32_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint32_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint32_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint32_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint32_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint32_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint32_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | SPI_CR1_CPHA ((uint32_t)0x00000001) |
| #define | SPI_CR1_CPOL ((uint32_t)0x00000002) |
| #define | SPI_CR1_MSTR ((uint32_t)0x00000004) |
| #define | SPI_CR1_BR ((uint32_t)0x00000038) |
| #define | SPI_CR1_BR_0 ((uint32_t)0x00000008) |
| #define | SPI_CR1_BR_1 ((uint32_t)0x00000010) |
| #define | SPI_CR1_BR_2 ((uint32_t)0x00000020) |
| #define | SPI_CR1_SPE ((uint32_t)0x00000040) |
| #define | SPI_CR1_LSBFIRST ((uint32_t)0x00000080) |
| #define | SPI_CR1_SSI ((uint32_t)0x00000100) |
| #define | SPI_CR1_SSM ((uint32_t)0x00000200) |
| #define | SPI_CR1_RXONLY ((uint32_t)0x00000400) |
| #define | SPI_CR1_DFF ((uint32_t)0x00000800) |
| #define | SPI_CR1_CRCNEXT ((uint32_t)0x00001000) |
| #define | SPI_CR1_CRCEN ((uint32_t)0x00002000) |
| #define | SPI_CR1_BIDIOE ((uint32_t)0x00004000) |
| #define | SPI_CR1_BIDIMODE ((uint32_t)0x00008000) |
| #define | SPI_CR2_RXDMAEN ((uint32_t)0x00000001) |
| #define | SPI_CR2_TXDMAEN ((uint32_t)0x00000002) |
| #define | SPI_CR2_SSOE ((uint32_t)0x00000004) |
| #define | SPI_CR2_ERRIE ((uint32_t)0x00000020) |
| #define | SPI_CR2_RXNEIE ((uint32_t)0x00000040) |
| #define | SPI_CR2_TXEIE ((uint32_t)0x00000080) |
| #define | SPI_SR_RXNE ((uint32_t)0x00000001) |
| #define | SPI_SR_TXE ((uint32_t)0x00000002) |
| #define | SPI_SR_CHSIDE ((uint32_t)0x00000004) |
| #define | SPI_SR_UDR ((uint32_t)0x00000008) |
| #define | SPI_SR_CRCERR ((uint32_t)0x00000010) |
| #define | SPI_SR_MODF ((uint32_t)0x00000020) |
| #define | SPI_SR_OVR ((uint32_t)0x00000040) |
| #define | SPI_SR_BSY ((uint32_t)0x00000080) |
| #define | SPI_DR_DR ((uint32_t)0x0000FFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_SMBUS ((uint32_t)0x00000002) |
| #define | I2C_CR1_SMBTYPE ((uint32_t)0x00000008) |
| #define | I2C_CR1_ENARP ((uint32_t)0x00000010) |
| #define | I2C_CR1_ENPEC ((uint32_t)0x00000020) |
| #define | I2C_CR1_ENGC ((uint32_t)0x00000040) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) |
| #define | I2C_CR1_START ((uint32_t)0x00000100) |
| #define | I2C_CR1_STOP ((uint32_t)0x00000200) |
| #define | I2C_CR1_ACK ((uint32_t)0x00000400) |
| #define | I2C_CR1_POS ((uint32_t)0x00000800) |
| #define | I2C_CR1_PEC ((uint32_t)0x00001000) |
| #define | I2C_CR1_ALERT ((uint32_t)0x00002000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00008000) |
| #define | I2C_CR2_FREQ ((uint32_t)0x0000003F) |
| #define | I2C_CR2_FREQ_0 ((uint32_t)0x00000001) |
| #define | I2C_CR2_FREQ_1 ((uint32_t)0x00000002) |
| #define | I2C_CR2_FREQ_2 ((uint32_t)0x00000004) |
| #define | I2C_CR2_FREQ_3 ((uint32_t)0x00000008) |
| #define | I2C_CR2_FREQ_4 ((uint32_t)0x00000010) |
| #define | I2C_CR2_FREQ_5 ((uint32_t)0x00000020) |
| #define | I2C_CR2_ITERREN ((uint32_t)0x00000100) |
| #define | I2C_CR2_ITEVTEN ((uint32_t)0x00000200) |
| #define | I2C_CR2_ITBUFEN ((uint32_t)0x00000400) |
| #define | I2C_CR2_DMAEN ((uint32_t)0x00000800) |
| #define | I2C_CR2_LAST ((uint32_t)0x00001000) |
| #define | I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) |
| #define | I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) |
| #define | I2C_OAR1_ADD0 ((uint32_t)0x00000001) |
| #define | I2C_OAR1_ADD1 ((uint32_t)0x00000002) |
| #define | I2C_OAR1_ADD2 ((uint32_t)0x00000004) |
| #define | I2C_OAR1_ADD3 ((uint32_t)0x00000008) |
| #define | I2C_OAR1_ADD4 ((uint32_t)0x00000010) |
| #define | I2C_OAR1_ADD5 ((uint32_t)0x00000020) |
| #define | I2C_OAR1_ADD6 ((uint32_t)0x00000040) |
| #define | I2C_OAR1_ADD7 ((uint32_t)0x00000080) |
| #define | I2C_OAR1_ADD8 ((uint32_t)0x00000100) |
| #define | I2C_OAR1_ADD9 ((uint32_t)0x00000200) |
| #define | I2C_OAR1_ADDMODE ((uint32_t)0x00008000) |
| #define | I2C_OAR2_ENDUAL ((uint32_t)0x00000001) |
| #define | I2C_OAR2_ADD2 ((uint32_t)0x000000FE) |
| #define | I2C_SR1_SB ((uint32_t)0x00000001) |
| #define | I2C_SR1_ADDR ((uint32_t)0x00000002) |
| #define | I2C_SR1_BTF ((uint32_t)0x00000004) |
| #define | I2C_SR1_ADD10 ((uint32_t)0x00000008) |
| #define | I2C_SR1_STOPF ((uint32_t)0x00000010) |
| #define | I2C_SR1_RXNE ((uint32_t)0x00000040) |
| #define | I2C_SR1_TXE ((uint32_t)0x00000080) |
| #define | I2C_SR1_BERR ((uint32_t)0x00000100) |
| #define | I2C_SR1_ARLO ((uint32_t)0x00000200) |
| #define | I2C_SR1_AF ((uint32_t)0x00000400) |
| #define | I2C_SR1_OVR ((uint32_t)0x00000800) |
| #define | I2C_SR1_PECERR ((uint32_t)0x00001000) |
| #define | I2C_SR1_TIMEOUT ((uint32_t)0x00004000) |
| #define | I2C_SR1_SMBALERT ((uint32_t)0x00008000) |
| #define | I2C_SR2_MSL ((uint32_t)0x00000001) |
| #define | I2C_SR2_BUSY ((uint32_t)0x00000002) |
| #define | I2C_SR2_TRA ((uint32_t)0x00000004) |
| #define | I2C_SR2_GENCALL ((uint32_t)0x00000010) |
| #define | I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) |
| #define | I2C_SR2_SMBHOST ((uint32_t)0x00000040) |
| #define | I2C_SR2_DUALF ((uint32_t)0x00000080) |
| #define | I2C_SR2_PEC ((uint32_t)0x0000FF00) |
| #define | I2C_CCR_CCR ((uint32_t)0x00000FFF) |
| #define | I2C_CCR_DUTY ((uint32_t)0x00004000) |
| #define | I2C_CCR_FS ((uint32_t)0x00008000) |
| #define | I2C_TRISE_TRISE ((uint32_t)0x0000003F) |
| #define | USART_SR_PE ((uint32_t)0x00000001) |
| #define | USART_SR_FE ((uint32_t)0x00000002) |
| #define | USART_SR_NE ((uint32_t)0x00000004) |
| #define | USART_SR_ORE ((uint32_t)0x00000008) |
| #define | USART_SR_IDLE ((uint32_t)0x00000010) |
| #define | USART_SR_RXNE ((uint32_t)0x00000020) |
| #define | USART_SR_TC ((uint32_t)0x00000040) |
| #define | USART_SR_TXE ((uint32_t)0x00000080) |
| #define | USART_SR_LBD ((uint32_t)0x00000100) |
| #define | USART_SR_CTS ((uint32_t)0x00000200) |
| #define | USART_DR_DR ((uint32_t)0x000001FF) |
| #define | USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) |
| #define | USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) |
| #define | USART_CR1_SBK ((uint32_t)0x00000001) |
| #define | USART_CR1_RWU ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_UE ((uint32_t)0x00002000) |
| #define | USART_CR2_ADD ((uint32_t)0x0000000F) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_GTPR_PSC ((uint32_t)0x000000FF) |
| #define | USART_GTPR_PSC_0 ((uint32_t)0x00000001) |
| #define | USART_GTPR_PSC_1 ((uint32_t)0x00000002) |
| #define | USART_GTPR_PSC_2 ((uint32_t)0x00000004) |
| #define | USART_GTPR_PSC_3 ((uint32_t)0x00000008) |
| #define | USART_GTPR_PSC_4 ((uint32_t)0x00000010) |
| #define | USART_GTPR_PSC_5 ((uint32_t)0x00000020) |
| #define | USART_GTPR_PSC_6 ((uint32_t)0x00000040) |
| #define | USART_GTPR_PSC_7 ((uint32_t)0x00000080) |
| #define | USART_GTPR_GT ((uint32_t)0x0000FF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) |
| #define | FLASH_ACR_HLFCYA ((uint32_t)0x00000008) |
| #define | FLASH_ACR_PRFTBE ((uint32_t)0x00000010) |
| #define | FLASH_ACR_PRFTBS ((uint32_t)0x00000020) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint32_t)0x000000A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT ((uint32_t)0x00000002) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) |
| #define | FLASH_OBR_USER ((uint32_t)0x0000001C) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) |
| #define | FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) |
| #define | FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) |
| #define | FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint32_t)0x000000FF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V2 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_2V3 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_2V4 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2V5 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_2V6 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | BKP_DR1_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR2_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR3_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR4_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR5_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR6_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR7_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR8_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR9_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR10_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR11_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR12_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR13_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR14_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR15_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR16_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR17_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR18_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR19_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR20_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR21_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR22_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR23_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR24_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR25_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR26_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR27_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR28_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR29_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR30_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR31_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR32_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR33_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR34_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR35_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR36_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR37_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR38_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR39_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR40_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR41_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR42_D ((uint32_t)0x0000FFFF) |
| #define | RTC_BKP_NUMBER 42 |
| #define | BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
| #define | BKP_RTCCR_CCO ((uint32_t)0x00000080) |
| #define | BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
| #define | BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
| #define | BKP_CR_TPE ((uint32_t)0x00000001) |
| #define | BKP_CR_TPAL ((uint32_t)0x00000002) |
| #define | BKP_CSR_CTE ((uint32_t)0x00000001) |
| #define | BKP_CSR_CTI ((uint32_t)0x00000002) |
| #define | BKP_CSR_TPIE ((uint32_t)0x00000004) |
| #define | BKP_CSR_TEF ((uint32_t)0x00000100) |
| #define | BKP_CSR_TIF ((uint32_t)0x00000200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) |
| #define | RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) |
| #define | RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
| #define | RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) |
| #define | RCC_AHBENR_FSMCEN ((uint32_t)0x00000100) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) |
| #define | RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) |
| #define | RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
| #define | RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint32_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint32_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint32_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint32_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint32_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint32_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint32_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint32_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint32_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint32_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint32_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint32_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint32_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint32_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint32_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint32_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint32_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint32_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint32_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint32_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint32_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint32_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint32_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint32_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint32_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint32_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint32_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint32_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint32_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint32_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint32_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint32_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint32_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint32_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint32_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint32_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint32_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint32_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint32_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint32_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint32_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint32_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint32_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint32_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint32_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint32_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint32_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint32_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
| #define | AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
| #define | AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
| #define | AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
| #define | AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
| #define | AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PORT ((uint32_t)0x00000070) |
| #define | AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
| #define | AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
| #define | AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
| #define | AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) |
| #define | SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) |
| #define | SCB_SCR_SEVONPEND ((uint32_t)0x00000010) |
| #define | SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) |
| #define | SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) |
| #define | SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) |
| #define | SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) |
| #define | SCB_CCR_STKALIGN ((uint32_t)0x00000200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint32_t)0x00000001) |
| #define | SCB_DFSR_BKPT ((uint32_t)0x00000002) |
| #define | SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) |
| #define | SCB_DFSR_VCATCH ((uint32_t)0x00000008) |
| #define | SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) |
| #define | DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) |
| #define | DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) |
| #define | TIM_CR1_CEN ((uint32_t)0x00000001) |
| #define | TIM_CR1_UDIS ((uint32_t)0x00000002) |
| #define | TIM_CR1_URS ((uint32_t)0x00000004) |
| #define | TIM_CR1_OPM ((uint32_t)0x00000008) |
| #define | TIM_CR1_DIR ((uint32_t)0x00000010) |
| #define | TIM_CR1_CMS ((uint32_t)0x00000060) |
| #define | TIM_CR1_CMS_0 ((uint32_t)0x00000020) |
| #define | TIM_CR1_CMS_1 ((uint32_t)0x00000040) |
| #define | TIM_CR1_ARPE ((uint32_t)0x00000080) |
| #define | TIM_CR1_CKD ((uint32_t)0x00000300) |
| #define | TIM_CR1_CKD_0 ((uint32_t)0x00000100) |
| #define | TIM_CR1_CKD_1 ((uint32_t)0x00000200) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00000007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint32_t)0x00000001) |
| #define | TIM_DIER_CC1IE ((uint32_t)0x00000002) |
| #define | TIM_DIER_CC2IE ((uint32_t)0x00000004) |
| #define | TIM_DIER_CC3IE ((uint32_t)0x00000008) |
| #define | TIM_DIER_CC4IE ((uint32_t)0x00000010) |
| #define | TIM_DIER_COMIE ((uint32_t)0x00000020) |
| #define | TIM_DIER_TIE ((uint32_t)0x00000040) |
| #define | TIM_DIER_BIE ((uint32_t)0x00000080) |
| #define | TIM_DIER_UDE ((uint32_t)0x00000100) |
| #define | TIM_DIER_CC1DE ((uint32_t)0x00000200) |
| #define | TIM_DIER_CC2DE ((uint32_t)0x00000400) |
| #define | TIM_DIER_CC3DE ((uint32_t)0x00000800) |
| #define | TIM_DIER_CC4DE ((uint32_t)0x00001000) |
| #define | TIM_DIER_COMDE ((uint32_t)0x00002000) |
| #define | TIM_DIER_TDE ((uint32_t)0x00004000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_EGR_UG ((uint32_t)0x00000001) |
| #define | TIM_EGR_CC1G ((uint32_t)0x00000002) |
| #define | TIM_EGR_CC2G ((uint32_t)0x00000004) |
| #define | TIM_EGR_CC3G ((uint32_t)0x00000008) |
| #define | TIM_EGR_CC4G ((uint32_t)0x00000010) |
| #define | TIM_EGR_COMG ((uint32_t)0x00000020) |
| #define | TIM_EGR_TG ((uint32_t)0x00000040) |
| #define | TIM_EGR_BG ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00000070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x00007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_PSC_PSC ((uint32_t)0x0000FFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint32_t)0x000000FF) |
| #define | TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_DCR_DBA ((uint32_t)0x0000001F) |
| #define | TIM_DCR_DBA_0 ((uint32_t)0x00000001) |
| #define | TIM_DCR_DBA_1 ((uint32_t)0x00000002) |
| #define | TIM_DCR_DBA_2 ((uint32_t)0x00000004) |
| #define | TIM_DCR_DBA_3 ((uint32_t)0x00000008) |
| #define | TIM_DCR_DBA_4 ((uint32_t)0x00000010) |
| #define | TIM_DCR_DBL ((uint32_t)0x00001F00) |
| #define | TIM_DCR_DBL_0 ((uint32_t)0x00000100) |
| #define | TIM_DCR_DBL_1 ((uint32_t)0x00000200) |
| #define | TIM_DCR_DBL_2 ((uint32_t)0x00000400) |
| #define | TIM_DCR_DBL_3 ((uint32_t)0x00000800) |
| #define | TIM_DCR_DBL_4 ((uint32_t)0x00001000) |
| #define | TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) |
| #define | RTC_CRH_SECIE ((uint32_t)0x00000001) |
| #define | RTC_CRH_ALRIE ((uint32_t)0x00000002) |
| #define | RTC_CRH_OWIE ((uint32_t)0x00000004) |
| #define | RTC_CRL_SECF ((uint32_t)0x00000001) |
| #define | RTC_CRL_ALRF ((uint32_t)0x00000002) |
| #define | RTC_CRL_OWF ((uint32_t)0x00000004) |
| #define | RTC_CRL_RSF ((uint32_t)0x00000008) |
| #define | RTC_CRL_CNF ((uint32_t)0x00000010) |
| #define | RTC_CRL_RTOFF ((uint32_t)0x00000020) |
| #define | RTC_PRLH_PRL ((uint32_t)0x0000000F) |
| #define | RTC_PRLL_PRL ((uint32_t)0x0000FFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) |
| #define | RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | IWDG_KR_KEY ((uint32_t)0x0000FFFF) |
| #define | IWDG_PR_PR ((uint32_t)0x00000007) |
| #define | IWDG_PR_PR_0 ((uint32_t)0x00000001) |
| #define | IWDG_PR_PR_1 ((uint32_t)0x00000002) |
| #define | IWDG_PR_PR_2 ((uint32_t)0x00000004) |
| #define | IWDG_RLR_RL ((uint32_t)0x00000FFF) |
| #define | IWDG_SR_PVU ((uint32_t)0x00000001) |
| #define | IWDG_SR_RVU ((uint32_t)0x00000002) |
| #define | WWDG_CR_T ((uint32_t)0x0000007F) |
| #define | WWDG_CR_T0 ((uint32_t)0x00000001) |
| #define | WWDG_CR_T1 ((uint32_t)0x00000002) |
| #define | WWDG_CR_T2 ((uint32_t)0x00000004) |
| #define | WWDG_CR_T3 ((uint32_t)0x00000008) |
| #define | WWDG_CR_T4 ((uint32_t)0x00000010) |
| #define | WWDG_CR_T5 ((uint32_t)0x00000020) |
| #define | WWDG_CR_T6 ((uint32_t)0x00000040) |
| #define | WWDG_CR_WDGA ((uint32_t)0x00000080) |
| #define | WWDG_CFR_W ((uint32_t)0x0000007F) |
| #define | WWDG_CFR_W0 ((uint32_t)0x00000001) |
| #define | WWDG_CFR_W1 ((uint32_t)0x00000002) |
| #define | WWDG_CFR_W2 ((uint32_t)0x00000004) |
| #define | WWDG_CFR_W3 ((uint32_t)0x00000008) |
| #define | WWDG_CFR_W4 ((uint32_t)0x00000010) |
| #define | WWDG_CFR_W5 ((uint32_t)0x00000020) |
| #define | WWDG_CFR_W6 ((uint32_t)0x00000040) |
| #define | WWDG_CFR_WDGTB ((uint32_t)0x00000180) |
| #define | WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) |
| #define | WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) |
| #define | WWDG_CFR_EWI ((uint32_t)0x00000200) |
| #define | WWDG_SR_EWIF ((uint32_t)0x00000001) |
| #define | FSMC_BCRx_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCRx_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCRx_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCRx_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCRx_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCRx_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCRx_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCRx_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCRx_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCRx_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCRx_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCRx_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCRx_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCRx_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCRx_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCRx_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCRx_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BTRx_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTRx_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTRx_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTRx_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTRx_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTRx_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTRx_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTRx_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTRx_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTRx_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTRx_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTRx_DATAST_4 ((uint32_t)0x00001000) |
| #define | FSMC_BTRx_DATAST_5 ((uint32_t)0x00002000) |
| #define | FSMC_BTRx_DATAST_6 ((uint32_t)0x00004000) |
| #define | FSMC_BTRx_DATAST_7 ((uint32_t)0x00008000) |
| #define | FSMC_BTRx_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTRx_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTRx_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTRx_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTRx_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTRx_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTRx_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTRx_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTRx_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTRx_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTRx_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTRx_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTRx_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTRx_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTRx_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTRx_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTRx_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTRx_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTRx_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTRx_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTRx_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTRx_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTRx_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTRx_DATAST_4 ((uint32_t)0x00001000) |
| #define | FSMC_BWTRx_DATAST_5 ((uint32_t)0x00002000) |
| #define | FSMC_BWTRx_DATAST_6 ((uint32_t)0x00004000) |
| #define | FSMC_BWTRx_DATAST_7 ((uint32_t)0x00008000) |
| #define | FSMC_BWTRx_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BWTRx_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BWTRx_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BWTRx_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BWTRx_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BWTRx_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTRx_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTRx_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_PCRx_PWAITEN ((uint32_t)0x00000002) |
| #define | FSMC_PCRx_PBKEN ((uint32_t)0x00000004) |
| #define | FSMC_PCRx_PTYP ((uint32_t)0x00000008) |
| #define | FSMC_PCRx_PWID ((uint32_t)0x00000030) |
| #define | FSMC_PCRx_PWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_PCRx_PWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_PCRx_ECCEN ((uint32_t)0x00000040) |
| #define | FSMC_PCRx_TCLR ((uint32_t)0x00001E00) |
| #define | FSMC_PCRx_TCLR_0 ((uint32_t)0x00000200) |
| #define | FSMC_PCRx_TCLR_1 ((uint32_t)0x00000400) |
| #define | FSMC_PCRx_TCLR_2 ((uint32_t)0x00000800) |
| #define | FSMC_PCRx_TCLR_3 ((uint32_t)0x00001000) |
| #define | FSMC_PCRx_TAR ((uint32_t)0x0001E000) |
| #define | FSMC_PCRx_TAR_0 ((uint32_t)0x00002000) |
| #define | FSMC_PCRx_TAR_1 ((uint32_t)0x00004000) |
| #define | FSMC_PCRx_TAR_2 ((uint32_t)0x00008000) |
| #define | FSMC_PCRx_TAR_3 ((uint32_t)0x00010000) |
| #define | FSMC_PCRx_ECCPS ((uint32_t)0x000E0000) |
| #define | FSMC_PCRx_ECCPS_0 ((uint32_t)0x00020000) |
| #define | FSMC_PCRx_ECCPS_1 ((uint32_t)0x00040000) |
| #define | FSMC_PCRx_ECCPS_2 ((uint32_t)0x00080000) |
| #define | FSMC_SRx_IRS ((uint32_t)0x00000001) |
| #define | FSMC_SRx_ILS ((uint32_t)0x00000002) |
| #define | FSMC_SRx_IFS ((uint32_t)0x00000004) |
| #define | FSMC_SRx_IREN ((uint32_t)0x00000008) |
| #define | FSMC_SRx_ILEN ((uint32_t)0x00000010) |
| #define | FSMC_SRx_IFEN ((uint32_t)0x00000020) |
| #define | FSMC_SRx_FEMPT ((uint32_t)0x00000040) |
| #define | FSMC_PMEMx_MEMSETx ((uint32_t)0x000000FF) |
| #define | FSMC_PMEMx_MEMSETx_0 ((uint32_t)0x00000001) |
| #define | FSMC_PMEMx_MEMSETx_1 ((uint32_t)0x00000002) |
| #define | FSMC_PMEMx_MEMSETx_2 ((uint32_t)0x00000004) |
| #define | FSMC_PMEMx_MEMSETx_3 ((uint32_t)0x00000008) |
| #define | FSMC_PMEMx_MEMSETx_4 ((uint32_t)0x00000010) |
| #define | FSMC_PMEMx_MEMSETx_5 ((uint32_t)0x00000020) |
| #define | FSMC_PMEMx_MEMSETx_6 ((uint32_t)0x00000040) |
| #define | FSMC_PMEMx_MEMSETx_7 ((uint32_t)0x00000080) |
| #define | FSMC_PMEMx_MEMWAITx ((uint32_t)0x0000FF00) |
| #define | FSMC_PMEMx_MEMWAIT2_0 ((uint32_t)0x00000100) |
| #define | FSMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) |
| #define | FSMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) |
| #define | FSMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) |
| #define | FSMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) |
| #define | FSMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) |
| #define | FSMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) |
| #define | FSMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) |
| #define | FSMC_PMEMx_MEMHOLDx ((uint32_t)0x00FF0000) |
| #define | FSMC_PMEMx_MEMHOLDx_0 ((uint32_t)0x00010000) |
| #define | FSMC_PMEMx_MEMHOLDx_1 ((uint32_t)0x00020000) |
| #define | FSMC_PMEMx_MEMHOLDx_2 ((uint32_t)0x00040000) |
| #define | FSMC_PMEMx_MEMHOLDx_3 ((uint32_t)0x00080000) |
| #define | FSMC_PMEMx_MEMHOLDx_4 ((uint32_t)0x00100000) |
| #define | FSMC_PMEMx_MEMHOLDx_5 ((uint32_t)0x00200000) |
| #define | FSMC_PMEMx_MEMHOLDx_6 ((uint32_t)0x00400000) |
| #define | FSMC_PMEMx_MEMHOLDx_7 ((uint32_t)0x00800000) |
| #define | FSMC_PMEMx_MEMHIZx ((uint32_t)0xFF000000) |
| #define | FSMC_PMEMx_MEMHIZx_0 ((uint32_t)0x01000000) |
| #define | FSMC_PMEMx_MEMHIZx_1 ((uint32_t)0x02000000) |
| #define | FSMC_PMEMx_MEMHIZx_2 ((uint32_t)0x04000000) |
| #define | FSMC_PMEMx_MEMHIZx_3 ((uint32_t)0x08000000) |
| #define | FSMC_PMEMx_MEMHIZx_4 ((uint32_t)0x10000000) |
| #define | FSMC_PMEMx_MEMHIZx_5 ((uint32_t)0x20000000) |
| #define | FSMC_PMEMx_MEMHIZx_6 ((uint32_t)0x40000000) |
| #define | FSMC_PMEMx_MEMHIZx_7 ((uint32_t)0x80000000) |
| #define | FSMC_PATTx_ATTSETx ((uint32_t)0x000000FF) |
| #define | FSMC_PATTx_ATTSETx_0 ((uint32_t)0x00000001) |
| #define | FSMC_PATTx_ATTSETx_1 ((uint32_t)0x00000002) |
| #define | FSMC_PATTx_ATTSETx_2 ((uint32_t)0x00000004) |
| #define | FSMC_PATTx_ATTSETx_3 ((uint32_t)0x00000008) |
| #define | FSMC_PATTx_ATTSETx_4 ((uint32_t)0x00000010) |
| #define | FSMC_PATTx_ATTSETx_5 ((uint32_t)0x00000020) |
| #define | FSMC_PATTx_ATTSETx_6 ((uint32_t)0x00000040) |
| #define | FSMC_PATTx_ATTSETx_7 ((uint32_t)0x00000080) |
| #define | FSMC_PATTx_ATTWAITx ((uint32_t)0x0000FF00) |
| #define | FSMC_PATTx_ATTWAITx_0 ((uint32_t)0x00000100) |
| #define | FSMC_PATTx_ATTWAITx_1 ((uint32_t)0x00000200) |
| #define | FSMC_PATTx_ATTWAITx_2 ((uint32_t)0x00000400) |
| #define | FSMC_PATTx_ATTWAITx_3 ((uint32_t)0x00000800) |
| #define | FSMC_PATTx_ATTWAITx_4 ((uint32_t)0x00001000) |
| #define | FSMC_PATTx_ATTWAITx_5 ((uint32_t)0x00002000) |
| #define | FSMC_PATTx_ATTWAITx_6 ((uint32_t)0x00004000) |
| #define | FSMC_PATTx_ATTWAITx_7 ((uint32_t)0x00008000) |
| #define | FSMC_PATTx_ATTHOLDx ((uint32_t)0x00FF0000) |
| #define | FSMC_PATTx_ATTHOLDx_0 ((uint32_t)0x00010000) |
| #define | FSMC_PATTx_ATTHOLDx_1 ((uint32_t)0x00020000) |
| #define | FSMC_PATTx_ATTHOLDx_2 ((uint32_t)0x00040000) |
| #define | FSMC_PATTx_ATTHOLDx_3 ((uint32_t)0x00080000) |
| #define | FSMC_PATTx_ATTHOLDx_4 ((uint32_t)0x00100000) |
| #define | FSMC_PATTx_ATTHOLDx_5 ((uint32_t)0x00200000) |
| #define | FSMC_PATTx_ATTHOLDx_6 ((uint32_t)0x00400000) |
| #define | FSMC_PATTx_ATTHOLDx_7 ((uint32_t)0x00800000) |
| #define | FSMC_PATTx_ATTHIZx ((uint32_t)0xFF000000) |
| #define | FSMC_PATTx_ATTHIZx_0 ((uint32_t)0x01000000) |
| #define | FSMC_PATTx_ATTHIZx_1 ((uint32_t)0x02000000) |
| #define | FSMC_PATTx_ATTHIZx_2 ((uint32_t)0x04000000) |
| #define | FSMC_PATTx_ATTHIZx_3 ((uint32_t)0x08000000) |
| #define | FSMC_PATTx_ATTHIZx_4 ((uint32_t)0x10000000) |
| #define | FSMC_PATTx_ATTHIZx_5 ((uint32_t)0x20000000) |
| #define | FSMC_PATTx_ATTHIZx_6 ((uint32_t)0x40000000) |
| #define | FSMC_PATTx_ATTHIZx_7 ((uint32_t)0x80000000) |
| #define | FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) |
| #define | FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) |
| #define | FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) |
| #define | FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) |
| #define | FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) |
| #define | FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) |
| #define | FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) |
| #define | FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) |
| #define | FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) |
| #define | FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) |
| #define | FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) |
| #define | FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) |
| #define | FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) |
| #define | FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) |
| #define | FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) |
| #define | FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) |
| #define | FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) |
| #define | FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) |
| #define | FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) |
| #define | FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) |
| #define | FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) |
| #define | FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) |
| #define | FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) |
| #define | FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) |
| #define | FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) |
| #define | FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) |
| #define | FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) |
| #define | FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) |
| #define | FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) |
| #define | FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) |
| #define | FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) |
| #define | FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) |
| #define | FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) |
| #define | FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) |
| #define | FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) |
| #define | FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) |
| #define | FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) |
| #define | FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_POWER_PWRCTRL ((uint32_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint32_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint32_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint32_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint32_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint32_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint32_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint32_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint32_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint32_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint32_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint32_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint32_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint32_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint32_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint32_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | SPI_CR1_CPHA ((uint32_t)0x00000001) |
| #define | SPI_CR1_CPOL ((uint32_t)0x00000002) |
| #define | SPI_CR1_MSTR ((uint32_t)0x00000004) |
| #define | SPI_CR1_BR ((uint32_t)0x00000038) |
| #define | SPI_CR1_BR_0 ((uint32_t)0x00000008) |
| #define | SPI_CR1_BR_1 ((uint32_t)0x00000010) |
| #define | SPI_CR1_BR_2 ((uint32_t)0x00000020) |
| #define | SPI_CR1_SPE ((uint32_t)0x00000040) |
| #define | SPI_CR1_LSBFIRST ((uint32_t)0x00000080) |
| #define | SPI_CR1_SSI ((uint32_t)0x00000100) |
| #define | SPI_CR1_SSM ((uint32_t)0x00000200) |
| #define | SPI_CR1_RXONLY ((uint32_t)0x00000400) |
| #define | SPI_CR1_DFF ((uint32_t)0x00000800) |
| #define | SPI_CR1_CRCNEXT ((uint32_t)0x00001000) |
| #define | SPI_CR1_CRCEN ((uint32_t)0x00002000) |
| #define | SPI_CR1_BIDIOE ((uint32_t)0x00004000) |
| #define | SPI_CR1_BIDIMODE ((uint32_t)0x00008000) |
| #define | SPI_CR2_RXDMAEN ((uint32_t)0x00000001) |
| #define | SPI_CR2_TXDMAEN ((uint32_t)0x00000002) |
| #define | SPI_CR2_SSOE ((uint32_t)0x00000004) |
| #define | SPI_CR2_ERRIE ((uint32_t)0x00000020) |
| #define | SPI_CR2_RXNEIE ((uint32_t)0x00000040) |
| #define | SPI_CR2_TXEIE ((uint32_t)0x00000080) |
| #define | SPI_SR_RXNE ((uint32_t)0x00000001) |
| #define | SPI_SR_TXE ((uint32_t)0x00000002) |
| #define | SPI_SR_CHSIDE ((uint32_t)0x00000004) |
| #define | SPI_SR_UDR ((uint32_t)0x00000008) |
| #define | SPI_SR_CRCERR ((uint32_t)0x00000010) |
| #define | SPI_SR_MODF ((uint32_t)0x00000020) |
| #define | SPI_SR_OVR ((uint32_t)0x00000040) |
| #define | SPI_SR_BSY ((uint32_t)0x00000080) |
| #define | SPI_DR_DR ((uint32_t)0x0000FFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_SMBUS ((uint32_t)0x00000002) |
| #define | I2C_CR1_SMBTYPE ((uint32_t)0x00000008) |
| #define | I2C_CR1_ENARP ((uint32_t)0x00000010) |
| #define | I2C_CR1_ENPEC ((uint32_t)0x00000020) |
| #define | I2C_CR1_ENGC ((uint32_t)0x00000040) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) |
| #define | I2C_CR1_START ((uint32_t)0x00000100) |
| #define | I2C_CR1_STOP ((uint32_t)0x00000200) |
| #define | I2C_CR1_ACK ((uint32_t)0x00000400) |
| #define | I2C_CR1_POS ((uint32_t)0x00000800) |
| #define | I2C_CR1_PEC ((uint32_t)0x00001000) |
| #define | I2C_CR1_ALERT ((uint32_t)0x00002000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00008000) |
| #define | I2C_CR2_FREQ ((uint32_t)0x0000003F) |
| #define | I2C_CR2_FREQ_0 ((uint32_t)0x00000001) |
| #define | I2C_CR2_FREQ_1 ((uint32_t)0x00000002) |
| #define | I2C_CR2_FREQ_2 ((uint32_t)0x00000004) |
| #define | I2C_CR2_FREQ_3 ((uint32_t)0x00000008) |
| #define | I2C_CR2_FREQ_4 ((uint32_t)0x00000010) |
| #define | I2C_CR2_FREQ_5 ((uint32_t)0x00000020) |
| #define | I2C_CR2_ITERREN ((uint32_t)0x00000100) |
| #define | I2C_CR2_ITEVTEN ((uint32_t)0x00000200) |
| #define | I2C_CR2_ITBUFEN ((uint32_t)0x00000400) |
| #define | I2C_CR2_DMAEN ((uint32_t)0x00000800) |
| #define | I2C_CR2_LAST ((uint32_t)0x00001000) |
| #define | I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) |
| #define | I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) |
| #define | I2C_OAR1_ADD0 ((uint32_t)0x00000001) |
| #define | I2C_OAR1_ADD1 ((uint32_t)0x00000002) |
| #define | I2C_OAR1_ADD2 ((uint32_t)0x00000004) |
| #define | I2C_OAR1_ADD3 ((uint32_t)0x00000008) |
| #define | I2C_OAR1_ADD4 ((uint32_t)0x00000010) |
| #define | I2C_OAR1_ADD5 ((uint32_t)0x00000020) |
| #define | I2C_OAR1_ADD6 ((uint32_t)0x00000040) |
| #define | I2C_OAR1_ADD7 ((uint32_t)0x00000080) |
| #define | I2C_OAR1_ADD8 ((uint32_t)0x00000100) |
| #define | I2C_OAR1_ADD9 ((uint32_t)0x00000200) |
| #define | I2C_OAR1_ADDMODE ((uint32_t)0x00008000) |
| #define | I2C_OAR2_ENDUAL ((uint32_t)0x00000001) |
| #define | I2C_OAR2_ADD2 ((uint32_t)0x000000FE) |
| #define | I2C_SR1_SB ((uint32_t)0x00000001) |
| #define | I2C_SR1_ADDR ((uint32_t)0x00000002) |
| #define | I2C_SR1_BTF ((uint32_t)0x00000004) |
| #define | I2C_SR1_ADD10 ((uint32_t)0x00000008) |
| #define | I2C_SR1_STOPF ((uint32_t)0x00000010) |
| #define | I2C_SR1_RXNE ((uint32_t)0x00000040) |
| #define | I2C_SR1_TXE ((uint32_t)0x00000080) |
| #define | I2C_SR1_BERR ((uint32_t)0x00000100) |
| #define | I2C_SR1_ARLO ((uint32_t)0x00000200) |
| #define | I2C_SR1_AF ((uint32_t)0x00000400) |
| #define | I2C_SR1_OVR ((uint32_t)0x00000800) |
| #define | I2C_SR1_PECERR ((uint32_t)0x00001000) |
| #define | I2C_SR1_TIMEOUT ((uint32_t)0x00004000) |
| #define | I2C_SR1_SMBALERT ((uint32_t)0x00008000) |
| #define | I2C_SR2_MSL ((uint32_t)0x00000001) |
| #define | I2C_SR2_BUSY ((uint32_t)0x00000002) |
| #define | I2C_SR2_TRA ((uint32_t)0x00000004) |
| #define | I2C_SR2_GENCALL ((uint32_t)0x00000010) |
| #define | I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) |
| #define | I2C_SR2_SMBHOST ((uint32_t)0x00000040) |
| #define | I2C_SR2_DUALF ((uint32_t)0x00000080) |
| #define | I2C_SR2_PEC ((uint32_t)0x0000FF00) |
| #define | I2C_CCR_CCR ((uint32_t)0x00000FFF) |
| #define | I2C_CCR_DUTY ((uint32_t)0x00004000) |
| #define | I2C_CCR_FS ((uint32_t)0x00008000) |
| #define | I2C_TRISE_TRISE ((uint32_t)0x0000003F) |
| #define | USART_SR_PE ((uint32_t)0x00000001) |
| #define | USART_SR_FE ((uint32_t)0x00000002) |
| #define | USART_SR_NE ((uint32_t)0x00000004) |
| #define | USART_SR_ORE ((uint32_t)0x00000008) |
| #define | USART_SR_IDLE ((uint32_t)0x00000010) |
| #define | USART_SR_RXNE ((uint32_t)0x00000020) |
| #define | USART_SR_TC ((uint32_t)0x00000040) |
| #define | USART_SR_TXE ((uint32_t)0x00000080) |
| #define | USART_SR_LBD ((uint32_t)0x00000100) |
| #define | USART_SR_CTS ((uint32_t)0x00000200) |
| #define | USART_DR_DR ((uint32_t)0x000001FF) |
| #define | USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) |
| #define | USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) |
| #define | USART_CR1_SBK ((uint32_t)0x00000001) |
| #define | USART_CR1_RWU ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_UE ((uint32_t)0x00002000) |
| #define | USART_CR2_ADD ((uint32_t)0x0000000F) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_GTPR_PSC ((uint32_t)0x000000FF) |
| #define | USART_GTPR_PSC_0 ((uint32_t)0x00000001) |
| #define | USART_GTPR_PSC_1 ((uint32_t)0x00000002) |
| #define | USART_GTPR_PSC_2 ((uint32_t)0x00000004) |
| #define | USART_GTPR_PSC_3 ((uint32_t)0x00000008) |
| #define | USART_GTPR_PSC_4 ((uint32_t)0x00000010) |
| #define | USART_GTPR_PSC_5 ((uint32_t)0x00000020) |
| #define | USART_GTPR_PSC_6 ((uint32_t)0x00000040) |
| #define | USART_GTPR_PSC_7 ((uint32_t)0x00000080) |
| #define | USART_GTPR_GT ((uint32_t)0x0000FF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) |
| #define | DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) |
| #define | DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) |
| #define | DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) |
| #define | DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) |
| #define | DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) |
| #define | DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) |
| #define | FLASH_ACR_HLFCYA ((uint32_t)0x00000008) |
| #define | FLASH_ACR_PRFTBE ((uint32_t)0x00000010) |
| #define | FLASH_ACR_PRFTBS ((uint32_t)0x00000020) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint32_t)0x000000A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT ((uint32_t)0x00000002) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) |
| #define | FLASH_OBR_USER ((uint32_t)0x0000001C) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) |
| #define | FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) |
| #define | FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) |
| #define | FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint32_t)0x000000FF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V2 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_2V3 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_2V4 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2V5 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_2V6 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | BKP_DR1_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR2_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR3_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR4_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR5_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR6_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR7_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR8_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR9_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR10_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR11_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR12_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR13_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR14_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR15_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR16_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR17_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR18_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR19_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR20_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR21_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR22_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR23_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR24_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR25_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR26_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR27_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR28_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR29_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR30_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR31_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR32_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR33_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR34_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR35_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR36_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR37_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR38_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR39_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR40_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR41_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR42_D ((uint32_t)0x0000FFFF) |
| #define | RTC_BKP_NUMBER 42 |
| #define | BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
| #define | BKP_RTCCR_CCO ((uint32_t)0x00000080) |
| #define | BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
| #define | BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
| #define | BKP_CR_TPE ((uint32_t)0x00000001) |
| #define | BKP_CR_TPAL ((uint32_t)0x00000002) |
| #define | BKP_CSR_CTE ((uint32_t)0x00000001) |
| #define | BKP_CSR_CTI ((uint32_t)0x00000002) |
| #define | BKP_CSR_TPIE ((uint32_t)0x00000004) |
| #define | BKP_CSR_TEF ((uint32_t)0x00000100) |
| #define | BKP_CSR_TIF ((uint32_t)0x00000200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) |
| #define | RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) |
| #define | RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) |
| #define | RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) |
| #define | RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) |
| #define | RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
| #define | RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
| #define | RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) |
| #define | RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) |
| #define | RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) |
| #define | RCC_AHBENR_FSMCEN ((uint32_t)0x00000100) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) |
| #define | RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) |
| #define | RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) |
| #define | RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) |
| #define | RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) |
| #define | RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
| #define | RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
| #define | RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) |
| #define | RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) |
| #define | RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint32_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint32_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint32_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint32_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint32_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint32_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint32_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint32_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint32_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint32_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint32_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint32_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint32_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint32_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint32_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint32_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint32_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint32_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint32_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint32_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint32_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint32_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint32_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint32_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint32_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint32_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint32_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint32_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint32_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint32_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint32_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint32_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint32_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint32_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint32_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint32_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint32_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint32_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint32_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint32_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint32_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint32_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint32_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint32_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint32_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint32_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint32_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint32_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
| #define | AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
| #define | AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
| #define | AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
| #define | AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
| #define | AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PORT ((uint32_t)0x00000070) |
| #define | AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
| #define | AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
| #define | AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
| #define | AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) |
| #define | AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) |
| #define | AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) |
| #define | AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) |
| #define | AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) |
| #define | SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) |
| #define | SCB_SCR_SEVONPEND ((uint32_t)0x00000010) |
| #define | SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) |
| #define | SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) |
| #define | SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) |
| #define | SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) |
| #define | SCB_CCR_STKALIGN ((uint32_t)0x00000200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint32_t)0x00000001) |
| #define | SCB_DFSR_BKPT ((uint32_t)0x00000002) |
| #define | SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) |
| #define | SCB_DFSR_VCATCH ((uint32_t)0x00000008) |
| #define | SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
| #define | ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
| #define | ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
| #define | ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
| #define | ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) |
| #define | DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) |
| #define | DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) |
| #define | TIM_CR1_CEN ((uint32_t)0x00000001) |
| #define | TIM_CR1_UDIS ((uint32_t)0x00000002) |
| #define | TIM_CR1_URS ((uint32_t)0x00000004) |
| #define | TIM_CR1_OPM ((uint32_t)0x00000008) |
| #define | TIM_CR1_DIR ((uint32_t)0x00000010) |
| #define | TIM_CR1_CMS ((uint32_t)0x00000060) |
| #define | TIM_CR1_CMS_0 ((uint32_t)0x00000020) |
| #define | TIM_CR1_CMS_1 ((uint32_t)0x00000040) |
| #define | TIM_CR1_ARPE ((uint32_t)0x00000080) |
| #define | TIM_CR1_CKD ((uint32_t)0x00000300) |
| #define | TIM_CR1_CKD_0 ((uint32_t)0x00000100) |
| #define | TIM_CR1_CKD_1 ((uint32_t)0x00000200) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00000007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint32_t)0x00000001) |
| #define | TIM_DIER_CC1IE ((uint32_t)0x00000002) |
| #define | TIM_DIER_CC2IE ((uint32_t)0x00000004) |
| #define | TIM_DIER_CC3IE ((uint32_t)0x00000008) |
| #define | TIM_DIER_CC4IE ((uint32_t)0x00000010) |
| #define | TIM_DIER_COMIE ((uint32_t)0x00000020) |
| #define | TIM_DIER_TIE ((uint32_t)0x00000040) |
| #define | TIM_DIER_BIE ((uint32_t)0x00000080) |
| #define | TIM_DIER_UDE ((uint32_t)0x00000100) |
| #define | TIM_DIER_CC1DE ((uint32_t)0x00000200) |
| #define | TIM_DIER_CC2DE ((uint32_t)0x00000400) |
| #define | TIM_DIER_CC3DE ((uint32_t)0x00000800) |
| #define | TIM_DIER_CC4DE ((uint32_t)0x00001000) |
| #define | TIM_DIER_COMDE ((uint32_t)0x00002000) |
| #define | TIM_DIER_TDE ((uint32_t)0x00004000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_EGR_UG ((uint32_t)0x00000001) |
| #define | TIM_EGR_CC1G ((uint32_t)0x00000002) |
| #define | TIM_EGR_CC2G ((uint32_t)0x00000004) |
| #define | TIM_EGR_CC3G ((uint32_t)0x00000008) |
| #define | TIM_EGR_CC4G ((uint32_t)0x00000010) |
| #define | TIM_EGR_COMG ((uint32_t)0x00000020) |
| #define | TIM_EGR_TG ((uint32_t)0x00000040) |
| #define | TIM_EGR_BG ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00000070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x00007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_PSC_PSC ((uint32_t)0x0000FFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint32_t)0x000000FF) |
| #define | TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_DCR_DBA ((uint32_t)0x0000001F) |
| #define | TIM_DCR_DBA_0 ((uint32_t)0x00000001) |
| #define | TIM_DCR_DBA_1 ((uint32_t)0x00000002) |
| #define | TIM_DCR_DBA_2 ((uint32_t)0x00000004) |
| #define | TIM_DCR_DBA_3 ((uint32_t)0x00000008) |
| #define | TIM_DCR_DBA_4 ((uint32_t)0x00000010) |
| #define | TIM_DCR_DBL ((uint32_t)0x00001F00) |
| #define | TIM_DCR_DBL_0 ((uint32_t)0x00000100) |
| #define | TIM_DCR_DBL_1 ((uint32_t)0x00000200) |
| #define | TIM_DCR_DBL_2 ((uint32_t)0x00000400) |
| #define | TIM_DCR_DBL_3 ((uint32_t)0x00000800) |
| #define | TIM_DCR_DBL_4 ((uint32_t)0x00001000) |
| #define | TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) |
| #define | RTC_CRH_SECIE ((uint32_t)0x00000001) |
| #define | RTC_CRH_ALRIE ((uint32_t)0x00000002) |
| #define | RTC_CRH_OWIE ((uint32_t)0x00000004) |
| #define | RTC_CRL_SECF ((uint32_t)0x00000001) |
| #define | RTC_CRL_ALRF ((uint32_t)0x00000002) |
| #define | RTC_CRL_OWF ((uint32_t)0x00000004) |
| #define | RTC_CRL_RSF ((uint32_t)0x00000008) |
| #define | RTC_CRL_CNF ((uint32_t)0x00000010) |
| #define | RTC_CRL_RTOFF ((uint32_t)0x00000020) |
| #define | RTC_PRLH_PRL ((uint32_t)0x0000000F) |
| #define | RTC_PRLL_PRL ((uint32_t)0x0000FFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) |
| #define | RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | IWDG_KR_KEY ((uint32_t)0x0000FFFF) |
| #define | IWDG_PR_PR ((uint32_t)0x00000007) |
| #define | IWDG_PR_PR_0 ((uint32_t)0x00000001) |
| #define | IWDG_PR_PR_1 ((uint32_t)0x00000002) |
| #define | IWDG_PR_PR_2 ((uint32_t)0x00000004) |
| #define | IWDG_RLR_RL ((uint32_t)0x00000FFF) |
| #define | IWDG_SR_PVU ((uint32_t)0x00000001) |
| #define | IWDG_SR_RVU ((uint32_t)0x00000002) |
| #define | WWDG_CR_T ((uint32_t)0x0000007F) |
| #define | WWDG_CR_T0 ((uint32_t)0x00000001) |
| #define | WWDG_CR_T1 ((uint32_t)0x00000002) |
| #define | WWDG_CR_T2 ((uint32_t)0x00000004) |
| #define | WWDG_CR_T3 ((uint32_t)0x00000008) |
| #define | WWDG_CR_T4 ((uint32_t)0x00000010) |
| #define | WWDG_CR_T5 ((uint32_t)0x00000020) |
| #define | WWDG_CR_T6 ((uint32_t)0x00000040) |
| #define | WWDG_CR_WDGA ((uint32_t)0x00000080) |
| #define | WWDG_CFR_W ((uint32_t)0x0000007F) |
| #define | WWDG_CFR_W0 ((uint32_t)0x00000001) |
| #define | WWDG_CFR_W1 ((uint32_t)0x00000002) |
| #define | WWDG_CFR_W2 ((uint32_t)0x00000004) |
| #define | WWDG_CFR_W3 ((uint32_t)0x00000008) |
| #define | WWDG_CFR_W4 ((uint32_t)0x00000010) |
| #define | WWDG_CFR_W5 ((uint32_t)0x00000020) |
| #define | WWDG_CFR_W6 ((uint32_t)0x00000040) |
| #define | WWDG_CFR_WDGTB ((uint32_t)0x00000180) |
| #define | WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) |
| #define | WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) |
| #define | WWDG_CFR_EWI ((uint32_t)0x00000200) |
| #define | WWDG_SR_EWIF ((uint32_t)0x00000001) |
| #define | FSMC_BCRx_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCRx_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCRx_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCRx_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCRx_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCRx_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCRx_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCRx_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCRx_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCRx_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCRx_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCRx_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCRx_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCRx_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCRx_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCRx_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCRx_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BTRx_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTRx_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTRx_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTRx_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTRx_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTRx_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTRx_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTRx_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTRx_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTRx_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTRx_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTRx_DATAST_4 ((uint32_t)0x00001000) |
| #define | FSMC_BTRx_DATAST_5 ((uint32_t)0x00002000) |
| #define | FSMC_BTRx_DATAST_6 ((uint32_t)0x00004000) |
| #define | FSMC_BTRx_DATAST_7 ((uint32_t)0x00008000) |
| #define | FSMC_BTRx_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTRx_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTRx_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTRx_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTRx_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTRx_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTRx_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTRx_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTRx_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTRx_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTRx_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTRx_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTRx_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTRx_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTRx_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTRx_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTRx_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTRx_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTRx_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTRx_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTRx_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTRx_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTRx_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTRx_DATAST_4 ((uint32_t)0x00001000) |
| #define | FSMC_BWTRx_DATAST_5 ((uint32_t)0x00002000) |
| #define | FSMC_BWTRx_DATAST_6 ((uint32_t)0x00004000) |
| #define | FSMC_BWTRx_DATAST_7 ((uint32_t)0x00008000) |
| #define | FSMC_BWTRx_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BWTRx_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BWTRx_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BWTRx_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BWTRx_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BWTRx_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTRx_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTRx_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_PCRx_PWAITEN ((uint32_t)0x00000002) |
| #define | FSMC_PCRx_PBKEN ((uint32_t)0x00000004) |
| #define | FSMC_PCRx_PTYP ((uint32_t)0x00000008) |
| #define | FSMC_PCRx_PWID ((uint32_t)0x00000030) |
| #define | FSMC_PCRx_PWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_PCRx_PWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_PCRx_ECCEN ((uint32_t)0x00000040) |
| #define | FSMC_PCRx_TCLR ((uint32_t)0x00001E00) |
| #define | FSMC_PCRx_TCLR_0 ((uint32_t)0x00000200) |
| #define | FSMC_PCRx_TCLR_1 ((uint32_t)0x00000400) |
| #define | FSMC_PCRx_TCLR_2 ((uint32_t)0x00000800) |
| #define | FSMC_PCRx_TCLR_3 ((uint32_t)0x00001000) |
| #define | FSMC_PCRx_TAR ((uint32_t)0x0001E000) |
| #define | FSMC_PCRx_TAR_0 ((uint32_t)0x00002000) |
| #define | FSMC_PCRx_TAR_1 ((uint32_t)0x00004000) |
| #define | FSMC_PCRx_TAR_2 ((uint32_t)0x00008000) |
| #define | FSMC_PCRx_TAR_3 ((uint32_t)0x00010000) |
| #define | FSMC_PCRx_ECCPS ((uint32_t)0x000E0000) |
| #define | FSMC_PCRx_ECCPS_0 ((uint32_t)0x00020000) |
| #define | FSMC_PCRx_ECCPS_1 ((uint32_t)0x00040000) |
| #define | FSMC_PCRx_ECCPS_2 ((uint32_t)0x00080000) |
| #define | FSMC_SRx_IRS ((uint32_t)0x00000001) |
| #define | FSMC_SRx_ILS ((uint32_t)0x00000002) |
| #define | FSMC_SRx_IFS ((uint32_t)0x00000004) |
| #define | FSMC_SRx_IREN ((uint32_t)0x00000008) |
| #define | FSMC_SRx_ILEN ((uint32_t)0x00000010) |
| #define | FSMC_SRx_IFEN ((uint32_t)0x00000020) |
| #define | FSMC_SRx_FEMPT ((uint32_t)0x00000040) |
| #define | FSMC_PMEMx_MEMSETx ((uint32_t)0x000000FF) |
| #define | FSMC_PMEMx_MEMSETx_0 ((uint32_t)0x00000001) |
| #define | FSMC_PMEMx_MEMSETx_1 ((uint32_t)0x00000002) |
| #define | FSMC_PMEMx_MEMSETx_2 ((uint32_t)0x00000004) |
| #define | FSMC_PMEMx_MEMSETx_3 ((uint32_t)0x00000008) |
| #define | FSMC_PMEMx_MEMSETx_4 ((uint32_t)0x00000010) |
| #define | FSMC_PMEMx_MEMSETx_5 ((uint32_t)0x00000020) |
| #define | FSMC_PMEMx_MEMSETx_6 ((uint32_t)0x00000040) |
| #define | FSMC_PMEMx_MEMSETx_7 ((uint32_t)0x00000080) |
| #define | FSMC_PMEMx_MEMWAITx ((uint32_t)0x0000FF00) |
| #define | FSMC_PMEMx_MEMWAIT2_0 ((uint32_t)0x00000100) |
| #define | FSMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) |
| #define | FSMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) |
| #define | FSMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) |
| #define | FSMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) |
| #define | FSMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) |
| #define | FSMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) |
| #define | FSMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) |
| #define | FSMC_PMEMx_MEMHOLDx ((uint32_t)0x00FF0000) |
| #define | FSMC_PMEMx_MEMHOLDx_0 ((uint32_t)0x00010000) |
| #define | FSMC_PMEMx_MEMHOLDx_1 ((uint32_t)0x00020000) |
| #define | FSMC_PMEMx_MEMHOLDx_2 ((uint32_t)0x00040000) |
| #define | FSMC_PMEMx_MEMHOLDx_3 ((uint32_t)0x00080000) |
| #define | FSMC_PMEMx_MEMHOLDx_4 ((uint32_t)0x00100000) |
| #define | FSMC_PMEMx_MEMHOLDx_5 ((uint32_t)0x00200000) |
| #define | FSMC_PMEMx_MEMHOLDx_6 ((uint32_t)0x00400000) |
| #define | FSMC_PMEMx_MEMHOLDx_7 ((uint32_t)0x00800000) |
| #define | FSMC_PMEMx_MEMHIZx ((uint32_t)0xFF000000) |
| #define | FSMC_PMEMx_MEMHIZx_0 ((uint32_t)0x01000000) |
| #define | FSMC_PMEMx_MEMHIZx_1 ((uint32_t)0x02000000) |
| #define | FSMC_PMEMx_MEMHIZx_2 ((uint32_t)0x04000000) |
| #define | FSMC_PMEMx_MEMHIZx_3 ((uint32_t)0x08000000) |
| #define | FSMC_PMEMx_MEMHIZx_4 ((uint32_t)0x10000000) |
| #define | FSMC_PMEMx_MEMHIZx_5 ((uint32_t)0x20000000) |
| #define | FSMC_PMEMx_MEMHIZx_6 ((uint32_t)0x40000000) |
| #define | FSMC_PMEMx_MEMHIZx_7 ((uint32_t)0x80000000) |
| #define | FSMC_PATTx_ATTSETx ((uint32_t)0x000000FF) |
| #define | FSMC_PATTx_ATTSETx_0 ((uint32_t)0x00000001) |
| #define | FSMC_PATTx_ATTSETx_1 ((uint32_t)0x00000002) |
| #define | FSMC_PATTx_ATTSETx_2 ((uint32_t)0x00000004) |
| #define | FSMC_PATTx_ATTSETx_3 ((uint32_t)0x00000008) |
| #define | FSMC_PATTx_ATTSETx_4 ((uint32_t)0x00000010) |
| #define | FSMC_PATTx_ATTSETx_5 ((uint32_t)0x00000020) |
| #define | FSMC_PATTx_ATTSETx_6 ((uint32_t)0x00000040) |
| #define | FSMC_PATTx_ATTSETx_7 ((uint32_t)0x00000080) |
| #define | FSMC_PATTx_ATTWAITx ((uint32_t)0x0000FF00) |
| #define | FSMC_PATTx_ATTWAITx_0 ((uint32_t)0x00000100) |
| #define | FSMC_PATTx_ATTWAITx_1 ((uint32_t)0x00000200) |
| #define | FSMC_PATTx_ATTWAITx_2 ((uint32_t)0x00000400) |
| #define | FSMC_PATTx_ATTWAITx_3 ((uint32_t)0x00000800) |
| #define | FSMC_PATTx_ATTWAITx_4 ((uint32_t)0x00001000) |
| #define | FSMC_PATTx_ATTWAITx_5 ((uint32_t)0x00002000) |
| #define | FSMC_PATTx_ATTWAITx_6 ((uint32_t)0x00004000) |
| #define | FSMC_PATTx_ATTWAITx_7 ((uint32_t)0x00008000) |
| #define | FSMC_PATTx_ATTHOLDx ((uint32_t)0x00FF0000) |
| #define | FSMC_PATTx_ATTHOLDx_0 ((uint32_t)0x00010000) |
| #define | FSMC_PATTx_ATTHOLDx_1 ((uint32_t)0x00020000) |
| #define | FSMC_PATTx_ATTHOLDx_2 ((uint32_t)0x00040000) |
| #define | FSMC_PATTx_ATTHOLDx_3 ((uint32_t)0x00080000) |
| #define | FSMC_PATTx_ATTHOLDx_4 ((uint32_t)0x00100000) |
| #define | FSMC_PATTx_ATTHOLDx_5 ((uint32_t)0x00200000) |
| #define | FSMC_PATTx_ATTHOLDx_6 ((uint32_t)0x00400000) |
| #define | FSMC_PATTx_ATTHOLDx_7 ((uint32_t)0x00800000) |
| #define | FSMC_PATTx_ATTHIZx ((uint32_t)0xFF000000) |
| #define | FSMC_PATTx_ATTHIZx_0 ((uint32_t)0x01000000) |
| #define | FSMC_PATTx_ATTHIZx_1 ((uint32_t)0x02000000) |
| #define | FSMC_PATTx_ATTHIZx_2 ((uint32_t)0x04000000) |
| #define | FSMC_PATTx_ATTHIZx_3 ((uint32_t)0x08000000) |
| #define | FSMC_PATTx_ATTHIZx_4 ((uint32_t)0x10000000) |
| #define | FSMC_PATTx_ATTHIZx_5 ((uint32_t)0x20000000) |
| #define | FSMC_PATTx_ATTHIZx_6 ((uint32_t)0x40000000) |
| #define | FSMC_PATTx_ATTHIZx_7 ((uint32_t)0x80000000) |
| #define | FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) |
| #define | FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) |
| #define | FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) |
| #define | FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) |
| #define | FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) |
| #define | FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) |
| #define | FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) |
| #define | FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) |
| #define | FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) |
| #define | FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) |
| #define | FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) |
| #define | FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) |
| #define | FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) |
| #define | FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) |
| #define | FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) |
| #define | FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) |
| #define | FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) |
| #define | FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) |
| #define | FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) |
| #define | FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) |
| #define | FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) |
| #define | FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) |
| #define | FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) |
| #define | FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) |
| #define | FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) |
| #define | FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) |
| #define | FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) |
| #define | FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) |
| #define | FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) |
| #define | FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) |
| #define | FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) |
| #define | FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) |
| #define | FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) |
| #define | FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) |
| #define | FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) |
| #define | FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) |
| #define | FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) |
| #define | FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_POWER_PWRCTRL ((uint32_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint32_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint32_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint32_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint32_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint32_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint32_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint32_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint32_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint32_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint32_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint32_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint32_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint32_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint32_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint32_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | SPI_CR1_CPHA ((uint32_t)0x00000001) |
| #define | SPI_CR1_CPOL ((uint32_t)0x00000002) |
| #define | SPI_CR1_MSTR ((uint32_t)0x00000004) |
| #define | SPI_CR1_BR ((uint32_t)0x00000038) |
| #define | SPI_CR1_BR_0 ((uint32_t)0x00000008) |
| #define | SPI_CR1_BR_1 ((uint32_t)0x00000010) |
| #define | SPI_CR1_BR_2 ((uint32_t)0x00000020) |
| #define | SPI_CR1_SPE ((uint32_t)0x00000040) |
| #define | SPI_CR1_LSBFIRST ((uint32_t)0x00000080) |
| #define | SPI_CR1_SSI ((uint32_t)0x00000100) |
| #define | SPI_CR1_SSM ((uint32_t)0x00000200) |
| #define | SPI_CR1_RXONLY ((uint32_t)0x00000400) |
| #define | SPI_CR1_DFF ((uint32_t)0x00000800) |
| #define | SPI_CR1_CRCNEXT ((uint32_t)0x00001000) |
| #define | SPI_CR1_CRCEN ((uint32_t)0x00002000) |
| #define | SPI_CR1_BIDIOE ((uint32_t)0x00004000) |
| #define | SPI_CR1_BIDIMODE ((uint32_t)0x00008000) |
| #define | SPI_CR2_RXDMAEN ((uint32_t)0x00000001) |
| #define | SPI_CR2_TXDMAEN ((uint32_t)0x00000002) |
| #define | SPI_CR2_SSOE ((uint32_t)0x00000004) |
| #define | SPI_CR2_ERRIE ((uint32_t)0x00000020) |
| #define | SPI_CR2_RXNEIE ((uint32_t)0x00000040) |
| #define | SPI_CR2_TXEIE ((uint32_t)0x00000080) |
| #define | SPI_SR_RXNE ((uint32_t)0x00000001) |
| #define | SPI_SR_TXE ((uint32_t)0x00000002) |
| #define | SPI_SR_CHSIDE ((uint32_t)0x00000004) |
| #define | SPI_SR_UDR ((uint32_t)0x00000008) |
| #define | SPI_SR_CRCERR ((uint32_t)0x00000010) |
| #define | SPI_SR_MODF ((uint32_t)0x00000020) |
| #define | SPI_SR_OVR ((uint32_t)0x00000040) |
| #define | SPI_SR_BSY ((uint32_t)0x00000080) |
| #define | SPI_DR_DR ((uint32_t)0x0000FFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_SMBUS ((uint32_t)0x00000002) |
| #define | I2C_CR1_SMBTYPE ((uint32_t)0x00000008) |
| #define | I2C_CR1_ENARP ((uint32_t)0x00000010) |
| #define | I2C_CR1_ENPEC ((uint32_t)0x00000020) |
| #define | I2C_CR1_ENGC ((uint32_t)0x00000040) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) |
| #define | I2C_CR1_START ((uint32_t)0x00000100) |
| #define | I2C_CR1_STOP ((uint32_t)0x00000200) |
| #define | I2C_CR1_ACK ((uint32_t)0x00000400) |
| #define | I2C_CR1_POS ((uint32_t)0x00000800) |
| #define | I2C_CR1_PEC ((uint32_t)0x00001000) |
| #define | I2C_CR1_ALERT ((uint32_t)0x00002000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00008000) |
| #define | I2C_CR2_FREQ ((uint32_t)0x0000003F) |
| #define | I2C_CR2_FREQ_0 ((uint32_t)0x00000001) |
| #define | I2C_CR2_FREQ_1 ((uint32_t)0x00000002) |
| #define | I2C_CR2_FREQ_2 ((uint32_t)0x00000004) |
| #define | I2C_CR2_FREQ_3 ((uint32_t)0x00000008) |
| #define | I2C_CR2_FREQ_4 ((uint32_t)0x00000010) |
| #define | I2C_CR2_FREQ_5 ((uint32_t)0x00000020) |
| #define | I2C_CR2_ITERREN ((uint32_t)0x00000100) |
| #define | I2C_CR2_ITEVTEN ((uint32_t)0x00000200) |
| #define | I2C_CR2_ITBUFEN ((uint32_t)0x00000400) |
| #define | I2C_CR2_DMAEN ((uint32_t)0x00000800) |
| #define | I2C_CR2_LAST ((uint32_t)0x00001000) |
| #define | I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) |
| #define | I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) |
| #define | I2C_OAR1_ADD0 ((uint32_t)0x00000001) |
| #define | I2C_OAR1_ADD1 ((uint32_t)0x00000002) |
| #define | I2C_OAR1_ADD2 ((uint32_t)0x00000004) |
| #define | I2C_OAR1_ADD3 ((uint32_t)0x00000008) |
| #define | I2C_OAR1_ADD4 ((uint32_t)0x00000010) |
| #define | I2C_OAR1_ADD5 ((uint32_t)0x00000020) |
| #define | I2C_OAR1_ADD6 ((uint32_t)0x00000040) |
| #define | I2C_OAR1_ADD7 ((uint32_t)0x00000080) |
| #define | I2C_OAR1_ADD8 ((uint32_t)0x00000100) |
| #define | I2C_OAR1_ADD9 ((uint32_t)0x00000200) |
| #define | I2C_OAR1_ADDMODE ((uint32_t)0x00008000) |
| #define | I2C_OAR2_ENDUAL ((uint32_t)0x00000001) |
| #define | I2C_OAR2_ADD2 ((uint32_t)0x000000FE) |
| #define | I2C_SR1_SB ((uint32_t)0x00000001) |
| #define | I2C_SR1_ADDR ((uint32_t)0x00000002) |
| #define | I2C_SR1_BTF ((uint32_t)0x00000004) |
| #define | I2C_SR1_ADD10 ((uint32_t)0x00000008) |
| #define | I2C_SR1_STOPF ((uint32_t)0x00000010) |
| #define | I2C_SR1_RXNE ((uint32_t)0x00000040) |
| #define | I2C_SR1_TXE ((uint32_t)0x00000080) |
| #define | I2C_SR1_BERR ((uint32_t)0x00000100) |
| #define | I2C_SR1_ARLO ((uint32_t)0x00000200) |
| #define | I2C_SR1_AF ((uint32_t)0x00000400) |
| #define | I2C_SR1_OVR ((uint32_t)0x00000800) |
| #define | I2C_SR1_PECERR ((uint32_t)0x00001000) |
| #define | I2C_SR1_TIMEOUT ((uint32_t)0x00004000) |
| #define | I2C_SR1_SMBALERT ((uint32_t)0x00008000) |
| #define | I2C_SR2_MSL ((uint32_t)0x00000001) |
| #define | I2C_SR2_BUSY ((uint32_t)0x00000002) |
| #define | I2C_SR2_TRA ((uint32_t)0x00000004) |
| #define | I2C_SR2_GENCALL ((uint32_t)0x00000010) |
| #define | I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) |
| #define | I2C_SR2_SMBHOST ((uint32_t)0x00000040) |
| #define | I2C_SR2_DUALF ((uint32_t)0x00000080) |
| #define | I2C_SR2_PEC ((uint32_t)0x0000FF00) |
| #define | I2C_CCR_CCR ((uint32_t)0x00000FFF) |
| #define | I2C_CCR_DUTY ((uint32_t)0x00004000) |
| #define | I2C_CCR_FS ((uint32_t)0x00008000) |
| #define | I2C_TRISE_TRISE ((uint32_t)0x0000003F) |
| #define | USART_SR_PE ((uint32_t)0x00000001) |
| #define | USART_SR_FE ((uint32_t)0x00000002) |
| #define | USART_SR_NE ((uint32_t)0x00000004) |
| #define | USART_SR_ORE ((uint32_t)0x00000008) |
| #define | USART_SR_IDLE ((uint32_t)0x00000010) |
| #define | USART_SR_RXNE ((uint32_t)0x00000020) |
| #define | USART_SR_TC ((uint32_t)0x00000040) |
| #define | USART_SR_TXE ((uint32_t)0x00000080) |
| #define | USART_SR_LBD ((uint32_t)0x00000100) |
| #define | USART_SR_CTS ((uint32_t)0x00000200) |
| #define | USART_DR_DR ((uint32_t)0x000001FF) |
| #define | USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) |
| #define | USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) |
| #define | USART_CR1_SBK ((uint32_t)0x00000001) |
| #define | USART_CR1_RWU ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_UE ((uint32_t)0x00002000) |
| #define | USART_CR2_ADD ((uint32_t)0x0000000F) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_GTPR_PSC ((uint32_t)0x000000FF) |
| #define | USART_GTPR_PSC_0 ((uint32_t)0x00000001) |
| #define | USART_GTPR_PSC_1 ((uint32_t)0x00000002) |
| #define | USART_GTPR_PSC_2 ((uint32_t)0x00000004) |
| #define | USART_GTPR_PSC_3 ((uint32_t)0x00000008) |
| #define | USART_GTPR_PSC_4 ((uint32_t)0x00000010) |
| #define | USART_GTPR_PSC_5 ((uint32_t)0x00000020) |
| #define | USART_GTPR_PSC_6 ((uint32_t)0x00000040) |
| #define | USART_GTPR_PSC_7 ((uint32_t)0x00000080) |
| #define | USART_GTPR_GT ((uint32_t)0x0000FF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) |
| #define | DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) |
| #define | DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) |
| #define | DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) |
| #define | DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) |
| #define | DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) |
| #define | DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) |
| #define | DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) |
| #define | DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) |
| #define | DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) |
| #define | FLASH_ACR_HLFCYA ((uint32_t)0x00000008) |
| #define | FLASH_ACR_PRFTBE ((uint32_t)0x00000010) |
| #define | FLASH_ACR_PRFTBS ((uint32_t)0x00000020) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint32_t)0x000000A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT ((uint32_t)0x00000002) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) |
| #define | FLASH_OBR_BFB2 ((uint32_t)0x00000020) |
| #define | FLASH_OBR_USER ((uint32_t)0x0000003C) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEYR_OPTKEYR2 ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_SR2_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR2_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR2_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR2_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR2_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR2_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR2_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR2_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR2_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR2_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR2_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR2 ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) |
| #define | FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) |
| #define | FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) |
| #define | FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint32_t)0x000000FF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V2 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_2V3 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_2V4 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2V5 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_2V6 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | BKP_DR1_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR2_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR3_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR4_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR5_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR6_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR7_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR8_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR9_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR10_D ((uint32_t)0x0000FFFF) |
| #define | RTC_BKP_NUMBER 10 |
| #define | BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
| #define | BKP_RTCCR_CCO ((uint32_t)0x00000080) |
| #define | BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
| #define | BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
| #define | BKP_CR_TPE ((uint32_t)0x00000001) |
| #define | BKP_CR_TPAL ((uint32_t)0x00000002) |
| #define | BKP_CSR_CTE ((uint32_t)0x00000001) |
| #define | BKP_CSR_CTI ((uint32_t)0x00000002) |
| #define | BKP_CSR_TPIE ((uint32_t)0x00000004) |
| #define | BKP_CSR_TEF ((uint32_t)0x00000100) |
| #define | BKP_CSR_TIF ((uint32_t)0x00000200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_USBPRE ((uint32_t)0x00400000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_USBEN ((uint32_t)0x00800000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint32_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint32_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint32_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint32_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint32_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint32_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint32_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint32_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint32_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint32_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint32_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint32_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint32_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint32_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint32_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint32_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint32_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint32_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint32_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint32_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint32_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint32_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint32_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint32_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint32_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint32_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint32_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint32_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint32_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint32_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint32_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint32_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint32_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint32_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint32_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint32_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint32_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint32_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint32_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint32_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint32_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint32_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint32_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint32_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint32_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint32_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint32_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint32_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
| #define | AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
| #define | AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
| #define | AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
| #define | AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
| #define | AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PORT ((uint32_t)0x00000070) |
| #define | AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
| #define | AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) |
| #define | SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) |
| #define | SCB_SCR_SEVONPEND ((uint32_t)0x00000010) |
| #define | SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) |
| #define | SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) |
| #define | SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) |
| #define | SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) |
| #define | SCB_CCR_STKALIGN ((uint32_t)0x00000200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint32_t)0x00000001) |
| #define | SCB_DFSR_BKPT ((uint32_t)0x00000002) |
| #define | SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) |
| #define | SCB_DFSR_VCATCH ((uint32_t)0x00000008) |
| #define | SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | TIM_CR1_CEN ((uint32_t)0x00000001) |
| #define | TIM_CR1_UDIS ((uint32_t)0x00000002) |
| #define | TIM_CR1_URS ((uint32_t)0x00000004) |
| #define | TIM_CR1_OPM ((uint32_t)0x00000008) |
| #define | TIM_CR1_DIR ((uint32_t)0x00000010) |
| #define | TIM_CR1_CMS ((uint32_t)0x00000060) |
| #define | TIM_CR1_CMS_0 ((uint32_t)0x00000020) |
| #define | TIM_CR1_CMS_1 ((uint32_t)0x00000040) |
| #define | TIM_CR1_ARPE ((uint32_t)0x00000080) |
| #define | TIM_CR1_CKD ((uint32_t)0x00000300) |
| #define | TIM_CR1_CKD_0 ((uint32_t)0x00000100) |
| #define | TIM_CR1_CKD_1 ((uint32_t)0x00000200) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00000007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint32_t)0x00000001) |
| #define | TIM_DIER_CC1IE ((uint32_t)0x00000002) |
| #define | TIM_DIER_CC2IE ((uint32_t)0x00000004) |
| #define | TIM_DIER_CC3IE ((uint32_t)0x00000008) |
| #define | TIM_DIER_CC4IE ((uint32_t)0x00000010) |
| #define | TIM_DIER_COMIE ((uint32_t)0x00000020) |
| #define | TIM_DIER_TIE ((uint32_t)0x00000040) |
| #define | TIM_DIER_BIE ((uint32_t)0x00000080) |
| #define | TIM_DIER_UDE ((uint32_t)0x00000100) |
| #define | TIM_DIER_CC1DE ((uint32_t)0x00000200) |
| #define | TIM_DIER_CC2DE ((uint32_t)0x00000400) |
| #define | TIM_DIER_CC3DE ((uint32_t)0x00000800) |
| #define | TIM_DIER_CC4DE ((uint32_t)0x00001000) |
| #define | TIM_DIER_COMDE ((uint32_t)0x00002000) |
| #define | TIM_DIER_TDE ((uint32_t)0x00004000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_EGR_UG ((uint32_t)0x00000001) |
| #define | TIM_EGR_CC1G ((uint32_t)0x00000002) |
| #define | TIM_EGR_CC2G ((uint32_t)0x00000004) |
| #define | TIM_EGR_CC3G ((uint32_t)0x00000008) |
| #define | TIM_EGR_CC4G ((uint32_t)0x00000010) |
| #define | TIM_EGR_COMG ((uint32_t)0x00000020) |
| #define | TIM_EGR_TG ((uint32_t)0x00000040) |
| #define | TIM_EGR_BG ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00000070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x00007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_PSC_PSC ((uint32_t)0x0000FFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint32_t)0x000000FF) |
| #define | TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_DCR_DBA ((uint32_t)0x0000001F) |
| #define | TIM_DCR_DBA_0 ((uint32_t)0x00000001) |
| #define | TIM_DCR_DBA_1 ((uint32_t)0x00000002) |
| #define | TIM_DCR_DBA_2 ((uint32_t)0x00000004) |
| #define | TIM_DCR_DBA_3 ((uint32_t)0x00000008) |
| #define | TIM_DCR_DBA_4 ((uint32_t)0x00000010) |
| #define | TIM_DCR_DBL ((uint32_t)0x00001F00) |
| #define | TIM_DCR_DBL_0 ((uint32_t)0x00000100) |
| #define | TIM_DCR_DBL_1 ((uint32_t)0x00000200) |
| #define | TIM_DCR_DBL_2 ((uint32_t)0x00000400) |
| #define | TIM_DCR_DBL_3 ((uint32_t)0x00000800) |
| #define | TIM_DCR_DBL_4 ((uint32_t)0x00001000) |
| #define | TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) |
| #define | RTC_CRH_SECIE ((uint32_t)0x00000001) |
| #define | RTC_CRH_ALRIE ((uint32_t)0x00000002) |
| #define | RTC_CRH_OWIE ((uint32_t)0x00000004) |
| #define | RTC_CRL_SECF ((uint32_t)0x00000001) |
| #define | RTC_CRL_ALRF ((uint32_t)0x00000002) |
| #define | RTC_CRL_OWF ((uint32_t)0x00000004) |
| #define | RTC_CRL_RSF ((uint32_t)0x00000008) |
| #define | RTC_CRL_CNF ((uint32_t)0x00000010) |
| #define | RTC_CRL_RTOFF ((uint32_t)0x00000020) |
| #define | RTC_PRLH_PRL ((uint32_t)0x0000000F) |
| #define | RTC_PRLL_PRL ((uint32_t)0x0000FFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) |
| #define | RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | IWDG_KR_KEY ((uint32_t)0x0000FFFF) |
| #define | IWDG_PR_PR ((uint32_t)0x00000007) |
| #define | IWDG_PR_PR_0 ((uint32_t)0x00000001) |
| #define | IWDG_PR_PR_1 ((uint32_t)0x00000002) |
| #define | IWDG_PR_PR_2 ((uint32_t)0x00000004) |
| #define | IWDG_RLR_RL ((uint32_t)0x00000FFF) |
| #define | IWDG_SR_PVU ((uint32_t)0x00000001) |
| #define | IWDG_SR_RVU ((uint32_t)0x00000002) |
| #define | WWDG_CR_T ((uint32_t)0x0000007F) |
| #define | WWDG_CR_T0 ((uint32_t)0x00000001) |
| #define | WWDG_CR_T1 ((uint32_t)0x00000002) |
| #define | WWDG_CR_T2 ((uint32_t)0x00000004) |
| #define | WWDG_CR_T3 ((uint32_t)0x00000008) |
| #define | WWDG_CR_T4 ((uint32_t)0x00000010) |
| #define | WWDG_CR_T5 ((uint32_t)0x00000020) |
| #define | WWDG_CR_T6 ((uint32_t)0x00000040) |
| #define | WWDG_CR_WDGA ((uint32_t)0x00000080) |
| #define | WWDG_CFR_W ((uint32_t)0x0000007F) |
| #define | WWDG_CFR_W0 ((uint32_t)0x00000001) |
| #define | WWDG_CFR_W1 ((uint32_t)0x00000002) |
| #define | WWDG_CFR_W2 ((uint32_t)0x00000004) |
| #define | WWDG_CFR_W3 ((uint32_t)0x00000008) |
| #define | WWDG_CFR_W4 ((uint32_t)0x00000010) |
| #define | WWDG_CFR_W5 ((uint32_t)0x00000020) |
| #define | WWDG_CFR_W6 ((uint32_t)0x00000040) |
| #define | WWDG_CFR_WDGTB ((uint32_t)0x00000180) |
| #define | WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) |
| #define | WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) |
| #define | WWDG_CFR_EWI ((uint32_t)0x00000200) |
| #define | WWDG_SR_EWIF ((uint32_t)0x00000001) |
| #define | SDIO_POWER_PWRCTRL ((uint32_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint32_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint32_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint32_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint32_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint32_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint32_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint32_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint32_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint32_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint32_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint32_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint32_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint32_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint32_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint32_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | USB_EP0R USB_BASE |
| #define | USB_EP1R (USB_BASE + 0x00000004) |
| #define | USB_EP2R (USB_BASE + 0x00000008) |
| #define | USB_EP3R (USB_BASE + 0x0000000C) |
| #define | USB_EP4R (USB_BASE + 0x00000010) |
| #define | USB_EP5R (USB_BASE + 0x00000014) |
| #define | USB_EP6R (USB_BASE + 0x00000018) |
| #define | USB_EP7R (USB_BASE + 0x0000001C) |
| #define | USB_EP_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EPRX_STAT ((uint32_t)0x00003000) |
| #define | USB_EP_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP_T_FIELD ((uint32_t)0x00000600) |
| #define | USB_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EPTX_STAT ((uint32_t)0x00000030) |
| #define | USB_EPADDR_FIELD ((uint32_t)0x0000000F) |
| #define | USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) |
| #define | USB_EP_TYPE_MASK ((uint32_t)0x00000600) |
| #define | USB_EP_BULK ((uint32_t)0x00000000) |
| #define | USB_EP_CONTROL ((uint32_t)0x00000200) |
| #define | USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) |
| #define | USB_EP_INTERRUPT ((uint32_t)0x00000600) |
| #define | USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) |
| #define | USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) |
| #define | USB_EP_TX_DIS ((uint32_t)0x00000000) |
| #define | USB_EP_TX_STALL ((uint32_t)0x00000010) |
| #define | USB_EP_TX_NAK ((uint32_t)0x00000020) |
| #define | USB_EP_TX_VALID ((uint32_t)0x00000030) |
| #define | USB_EPTX_DTOG1 ((uint32_t)0x00000010) |
| #define | USB_EPTX_DTOG2 ((uint32_t)0x00000020) |
| #define | USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) |
| #define | USB_EP_RX_DIS ((uint32_t)0x00000000) |
| #define | USB_EP_RX_STALL ((uint32_t)0x00001000) |
| #define | USB_EP_RX_NAK ((uint32_t)0x00002000) |
| #define | USB_EP_RX_VALID ((uint32_t)0x00003000) |
| #define | USB_EPRX_DTOG1 ((uint32_t)0x00001000) |
| #define | USB_EPRX_DTOG2 ((uint32_t)0x00002000) |
| #define | USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) |
| #define | USB_EP0R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP0R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP0R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP0R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP0R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP0R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP0R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP0R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP0R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP0R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP1R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP1R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP1R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP1R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP1R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP1R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP1R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP1R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP1R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP1R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP2R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP2R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP2R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP2R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP2R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP2R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP2R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP2R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP2R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP2R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP3R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP3R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP3R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP3R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP3R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP3R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP3R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP3R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP3R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP3R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP4R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP4R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP4R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP4R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP4R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP4R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP4R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP4R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP4R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP4R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP5R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP5R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP5R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP5R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP5R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP5R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP5R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP5R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP5R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP5R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP6R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP6R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP6R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP6R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP6R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP6R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP6R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP6R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP6R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP6R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP7R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP7R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP7R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP7R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP7R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP7R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP7R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP7R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP7R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP7R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_CNTR_FRES ((uint32_t)0x00000001) |
| #define | USB_CNTR_PDWN ((uint32_t)0x00000002) |
| #define | USB_CNTR_LP_MODE ((uint32_t)0x00000004) |
| #define | USB_CNTR_FSUSP ((uint32_t)0x00000008) |
| #define | USB_CNTR_RESUME ((uint32_t)0x00000010) |
| #define | USB_CNTR_ESOFM ((uint32_t)0x00000100) |
| #define | USB_CNTR_SOFM ((uint32_t)0x00000200) |
| #define | USB_CNTR_RESETM ((uint32_t)0x00000400) |
| #define | USB_CNTR_SUSPM ((uint32_t)0x00000800) |
| #define | USB_CNTR_WKUPM ((uint32_t)0x00001000) |
| #define | USB_CNTR_ERRM ((uint32_t)0x00002000) |
| #define | USB_CNTR_PMAOVRM ((uint32_t)0x00004000) |
| #define | USB_CNTR_CTRM ((uint32_t)0x00008000) |
| #define | USB_ISTR_EP_ID ((uint32_t)0x0000000F) |
| #define | USB_ISTR_DIR ((uint32_t)0x00000010) |
| #define | USB_ISTR_ESOF ((uint32_t)0x00000100) |
| #define | USB_ISTR_SOF ((uint32_t)0x00000200) |
| #define | USB_ISTR_RESET ((uint32_t)0x00000400) |
| #define | USB_ISTR_SUSP ((uint32_t)0x00000800) |
| #define | USB_ISTR_WKUP ((uint32_t)0x00001000) |
| #define | USB_ISTR_ERR ((uint32_t)0x00002000) |
| #define | USB_ISTR_PMAOVR ((uint32_t)0x00004000) |
| #define | USB_ISTR_CTR ((uint32_t)0x00008000) |
| #define | USB_FNR_FN ((uint32_t)0x000007FF) |
| #define | USB_FNR_LSOF ((uint32_t)0x00001800) |
| #define | USB_FNR_LCK ((uint32_t)0x00002000) |
| #define | USB_FNR_RXDM ((uint32_t)0x00004000) |
| #define | USB_FNR_RXDP ((uint32_t)0x00008000) |
| #define | USB_DADDR_ADD ((uint32_t)0x0000007F) |
| #define | USB_DADDR_ADD0 ((uint32_t)0x00000001) |
| #define | USB_DADDR_ADD1 ((uint32_t)0x00000002) |
| #define | USB_DADDR_ADD2 ((uint32_t)0x00000004) |
| #define | USB_DADDR_ADD3 ((uint32_t)0x00000008) |
| #define | USB_DADDR_ADD4 ((uint32_t)0x00000010) |
| #define | USB_DADDR_ADD5 ((uint32_t)0x00000020) |
| #define | USB_DADDR_ADD6 ((uint32_t)0x00000040) |
| #define | USB_DADDR_EF ((uint32_t)0x00000080) |
| #define | USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) |
| #define | USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) |
| #define | USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) |
| #define | USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | SPI_CR1_CPHA ((uint32_t)0x00000001) |
| #define | SPI_CR1_CPOL ((uint32_t)0x00000002) |
| #define | SPI_CR1_MSTR ((uint32_t)0x00000004) |
| #define | SPI_CR1_BR ((uint32_t)0x00000038) |
| #define | SPI_CR1_BR_0 ((uint32_t)0x00000008) |
| #define | SPI_CR1_BR_1 ((uint32_t)0x00000010) |
| #define | SPI_CR1_BR_2 ((uint32_t)0x00000020) |
| #define | SPI_CR1_SPE ((uint32_t)0x00000040) |
| #define | SPI_CR1_LSBFIRST ((uint32_t)0x00000080) |
| #define | SPI_CR1_SSI ((uint32_t)0x00000100) |
| #define | SPI_CR1_SSM ((uint32_t)0x00000200) |
| #define | SPI_CR1_RXONLY ((uint32_t)0x00000400) |
| #define | SPI_CR1_DFF ((uint32_t)0x00000800) |
| #define | SPI_CR1_CRCNEXT ((uint32_t)0x00001000) |
| #define | SPI_CR1_CRCEN ((uint32_t)0x00002000) |
| #define | SPI_CR1_BIDIOE ((uint32_t)0x00004000) |
| #define | SPI_CR1_BIDIMODE ((uint32_t)0x00008000) |
| #define | SPI_CR2_RXDMAEN ((uint32_t)0x00000001) |
| #define | SPI_CR2_TXDMAEN ((uint32_t)0x00000002) |
| #define | SPI_CR2_SSOE ((uint32_t)0x00000004) |
| #define | SPI_CR2_ERRIE ((uint32_t)0x00000020) |
| #define | SPI_CR2_RXNEIE ((uint32_t)0x00000040) |
| #define | SPI_CR2_TXEIE ((uint32_t)0x00000080) |
| #define | SPI_SR_RXNE ((uint32_t)0x00000001) |
| #define | SPI_SR_TXE ((uint32_t)0x00000002) |
| #define | SPI_SR_CHSIDE ((uint32_t)0x00000004) |
| #define | SPI_SR_UDR ((uint32_t)0x00000008) |
| #define | SPI_SR_CRCERR ((uint32_t)0x00000010) |
| #define | SPI_SR_MODF ((uint32_t)0x00000020) |
| #define | SPI_SR_OVR ((uint32_t)0x00000040) |
| #define | SPI_SR_BSY ((uint32_t)0x00000080) |
| #define | SPI_DR_DR ((uint32_t)0x0000FFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_SMBUS ((uint32_t)0x00000002) |
| #define | I2C_CR1_SMBTYPE ((uint32_t)0x00000008) |
| #define | I2C_CR1_ENARP ((uint32_t)0x00000010) |
| #define | I2C_CR1_ENPEC ((uint32_t)0x00000020) |
| #define | I2C_CR1_ENGC ((uint32_t)0x00000040) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) |
| #define | I2C_CR1_START ((uint32_t)0x00000100) |
| #define | I2C_CR1_STOP ((uint32_t)0x00000200) |
| #define | I2C_CR1_ACK ((uint32_t)0x00000400) |
| #define | I2C_CR1_POS ((uint32_t)0x00000800) |
| #define | I2C_CR1_PEC ((uint32_t)0x00001000) |
| #define | I2C_CR1_ALERT ((uint32_t)0x00002000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00008000) |
| #define | I2C_CR2_FREQ ((uint32_t)0x0000003F) |
| #define | I2C_CR2_FREQ_0 ((uint32_t)0x00000001) |
| #define | I2C_CR2_FREQ_1 ((uint32_t)0x00000002) |
| #define | I2C_CR2_FREQ_2 ((uint32_t)0x00000004) |
| #define | I2C_CR2_FREQ_3 ((uint32_t)0x00000008) |
| #define | I2C_CR2_FREQ_4 ((uint32_t)0x00000010) |
| #define | I2C_CR2_FREQ_5 ((uint32_t)0x00000020) |
| #define | I2C_CR2_ITERREN ((uint32_t)0x00000100) |
| #define | I2C_CR2_ITEVTEN ((uint32_t)0x00000200) |
| #define | I2C_CR2_ITBUFEN ((uint32_t)0x00000400) |
| #define | I2C_CR2_DMAEN ((uint32_t)0x00000800) |
| #define | I2C_CR2_LAST ((uint32_t)0x00001000) |
| #define | I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) |
| #define | I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) |
| #define | I2C_OAR1_ADD0 ((uint32_t)0x00000001) |
| #define | I2C_OAR1_ADD1 ((uint32_t)0x00000002) |
| #define | I2C_OAR1_ADD2 ((uint32_t)0x00000004) |
| #define | I2C_OAR1_ADD3 ((uint32_t)0x00000008) |
| #define | I2C_OAR1_ADD4 ((uint32_t)0x00000010) |
| #define | I2C_OAR1_ADD5 ((uint32_t)0x00000020) |
| #define | I2C_OAR1_ADD6 ((uint32_t)0x00000040) |
| #define | I2C_OAR1_ADD7 ((uint32_t)0x00000080) |
| #define | I2C_OAR1_ADD8 ((uint32_t)0x00000100) |
| #define | I2C_OAR1_ADD9 ((uint32_t)0x00000200) |
| #define | I2C_OAR1_ADDMODE ((uint32_t)0x00008000) |
| #define | I2C_OAR2_ENDUAL ((uint32_t)0x00000001) |
| #define | I2C_OAR2_ADD2 ((uint32_t)0x000000FE) |
| #define | I2C_SR1_SB ((uint32_t)0x00000001) |
| #define | I2C_SR1_ADDR ((uint32_t)0x00000002) |
| #define | I2C_SR1_BTF ((uint32_t)0x00000004) |
| #define | I2C_SR1_ADD10 ((uint32_t)0x00000008) |
| #define | I2C_SR1_STOPF ((uint32_t)0x00000010) |
| #define | I2C_SR1_RXNE ((uint32_t)0x00000040) |
| #define | I2C_SR1_TXE ((uint32_t)0x00000080) |
| #define | I2C_SR1_BERR ((uint32_t)0x00000100) |
| #define | I2C_SR1_ARLO ((uint32_t)0x00000200) |
| #define | I2C_SR1_AF ((uint32_t)0x00000400) |
| #define | I2C_SR1_OVR ((uint32_t)0x00000800) |
| #define | I2C_SR1_PECERR ((uint32_t)0x00001000) |
| #define | I2C_SR1_TIMEOUT ((uint32_t)0x00004000) |
| #define | I2C_SR1_SMBALERT ((uint32_t)0x00008000) |
| #define | I2C_SR2_MSL ((uint32_t)0x00000001) |
| #define | I2C_SR2_BUSY ((uint32_t)0x00000002) |
| #define | I2C_SR2_TRA ((uint32_t)0x00000004) |
| #define | I2C_SR2_GENCALL ((uint32_t)0x00000010) |
| #define | I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) |
| #define | I2C_SR2_SMBHOST ((uint32_t)0x00000040) |
| #define | I2C_SR2_DUALF ((uint32_t)0x00000080) |
| #define | I2C_SR2_PEC ((uint32_t)0x0000FF00) |
| #define | I2C_CCR_CCR ((uint32_t)0x00000FFF) |
| #define | I2C_CCR_DUTY ((uint32_t)0x00004000) |
| #define | I2C_CCR_FS ((uint32_t)0x00008000) |
| #define | I2C_TRISE_TRISE ((uint32_t)0x0000003F) |
| #define | USART_SR_PE ((uint32_t)0x00000001) |
| #define | USART_SR_FE ((uint32_t)0x00000002) |
| #define | USART_SR_NE ((uint32_t)0x00000004) |
| #define | USART_SR_ORE ((uint32_t)0x00000008) |
| #define | USART_SR_IDLE ((uint32_t)0x00000010) |
| #define | USART_SR_RXNE ((uint32_t)0x00000020) |
| #define | USART_SR_TC ((uint32_t)0x00000040) |
| #define | USART_SR_TXE ((uint32_t)0x00000080) |
| #define | USART_SR_LBD ((uint32_t)0x00000100) |
| #define | USART_SR_CTS ((uint32_t)0x00000200) |
| #define | USART_DR_DR ((uint32_t)0x000001FF) |
| #define | USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) |
| #define | USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) |
| #define | USART_CR1_SBK ((uint32_t)0x00000001) |
| #define | USART_CR1_RWU ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_UE ((uint32_t)0x00002000) |
| #define | USART_CR2_ADD ((uint32_t)0x0000000F) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_GTPR_PSC ((uint32_t)0x000000FF) |
| #define | USART_GTPR_PSC_0 ((uint32_t)0x00000001) |
| #define | USART_GTPR_PSC_1 ((uint32_t)0x00000002) |
| #define | USART_GTPR_PSC_2 ((uint32_t)0x00000004) |
| #define | USART_GTPR_PSC_3 ((uint32_t)0x00000008) |
| #define | USART_GTPR_PSC_4 ((uint32_t)0x00000010) |
| #define | USART_GTPR_PSC_5 ((uint32_t)0x00000020) |
| #define | USART_GTPR_PSC_6 ((uint32_t)0x00000040) |
| #define | USART_GTPR_PSC_7 ((uint32_t)0x00000080) |
| #define | USART_GTPR_GT ((uint32_t)0x0000FF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) |
| #define | FLASH_ACR_HLFCYA ((uint32_t)0x00000008) |
| #define | FLASH_ACR_PRFTBE ((uint32_t)0x00000010) |
| #define | FLASH_ACR_PRFTBS ((uint32_t)0x00000020) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint32_t)0x000000A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT ((uint32_t)0x00000002) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) |
| #define | FLASH_OBR_USER ((uint32_t)0x0000001C) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) |
| #define | FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) |
| #define | FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) |
| #define | FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint32_t)0x000000FF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V2 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_2V3 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_2V4 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2V5 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_2V6 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | BKP_DR1_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR2_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR3_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR4_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR5_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR6_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR7_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR8_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR9_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR10_D ((uint32_t)0x0000FFFF) |
| #define | RTC_BKP_NUMBER 10 |
| #define | BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
| #define | BKP_RTCCR_CCO ((uint32_t)0x00000080) |
| #define | BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
| #define | BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
| #define | BKP_CR_TPE ((uint32_t)0x00000001) |
| #define | BKP_CR_TPAL ((uint32_t)0x00000002) |
| #define | BKP_CSR_CTE ((uint32_t)0x00000001) |
| #define | BKP_CSR_CTI ((uint32_t)0x00000002) |
| #define | BKP_CSR_TPIE ((uint32_t)0x00000004) |
| #define | BKP_CSR_TEF ((uint32_t)0x00000100) |
| #define | BKP_CSR_TIF ((uint32_t)0x00000200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_USBPRE ((uint32_t)0x00400000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_USBEN ((uint32_t)0x00800000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint32_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint32_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint32_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint32_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint32_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint32_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint32_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint32_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint32_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint32_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint32_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint32_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint32_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint32_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint32_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint32_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint32_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint32_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint32_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint32_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint32_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint32_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint32_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint32_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint32_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint32_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint32_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint32_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint32_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint32_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint32_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint32_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint32_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint32_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint32_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint32_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint32_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint32_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint32_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint32_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint32_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint32_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint32_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint32_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint32_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint32_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint32_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint32_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
| #define | AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
| #define | AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
| #define | AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
| #define | AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
| #define | AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PORT ((uint32_t)0x00000070) |
| #define | AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
| #define | AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
| #define | AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) |
| #define | SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) |
| #define | SCB_SCR_SEVONPEND ((uint32_t)0x00000010) |
| #define | SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) |
| #define | SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) |
| #define | SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) |
| #define | SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) |
| #define | SCB_CCR_STKALIGN ((uint32_t)0x00000200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint32_t)0x00000001) |
| #define | SCB_DFSR_BKPT ((uint32_t)0x00000002) |
| #define | SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) |
| #define | SCB_DFSR_VCATCH ((uint32_t)0x00000008) |
| #define | SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | TIM_CR1_CEN ((uint32_t)0x00000001) |
| #define | TIM_CR1_UDIS ((uint32_t)0x00000002) |
| #define | TIM_CR1_URS ((uint32_t)0x00000004) |
| #define | TIM_CR1_OPM ((uint32_t)0x00000008) |
| #define | TIM_CR1_DIR ((uint32_t)0x00000010) |
| #define | TIM_CR1_CMS ((uint32_t)0x00000060) |
| #define | TIM_CR1_CMS_0 ((uint32_t)0x00000020) |
| #define | TIM_CR1_CMS_1 ((uint32_t)0x00000040) |
| #define | TIM_CR1_ARPE ((uint32_t)0x00000080) |
| #define | TIM_CR1_CKD ((uint32_t)0x00000300) |
| #define | TIM_CR1_CKD_0 ((uint32_t)0x00000100) |
| #define | TIM_CR1_CKD_1 ((uint32_t)0x00000200) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00000007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint32_t)0x00000001) |
| #define | TIM_DIER_CC1IE ((uint32_t)0x00000002) |
| #define | TIM_DIER_CC2IE ((uint32_t)0x00000004) |
| #define | TIM_DIER_CC3IE ((uint32_t)0x00000008) |
| #define | TIM_DIER_CC4IE ((uint32_t)0x00000010) |
| #define | TIM_DIER_COMIE ((uint32_t)0x00000020) |
| #define | TIM_DIER_TIE ((uint32_t)0x00000040) |
| #define | TIM_DIER_BIE ((uint32_t)0x00000080) |
| #define | TIM_DIER_UDE ((uint32_t)0x00000100) |
| #define | TIM_DIER_CC1DE ((uint32_t)0x00000200) |
| #define | TIM_DIER_CC2DE ((uint32_t)0x00000400) |
| #define | TIM_DIER_CC3DE ((uint32_t)0x00000800) |
| #define | TIM_DIER_CC4DE ((uint32_t)0x00001000) |
| #define | TIM_DIER_COMDE ((uint32_t)0x00002000) |
| #define | TIM_DIER_TDE ((uint32_t)0x00004000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_EGR_UG ((uint32_t)0x00000001) |
| #define | TIM_EGR_CC1G ((uint32_t)0x00000002) |
| #define | TIM_EGR_CC2G ((uint32_t)0x00000004) |
| #define | TIM_EGR_CC3G ((uint32_t)0x00000008) |
| #define | TIM_EGR_CC4G ((uint32_t)0x00000010) |
| #define | TIM_EGR_COMG ((uint32_t)0x00000020) |
| #define | TIM_EGR_TG ((uint32_t)0x00000040) |
| #define | TIM_EGR_BG ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00000070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x00007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_PSC_PSC ((uint32_t)0x0000FFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint32_t)0x000000FF) |
| #define | TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_DCR_DBA ((uint32_t)0x0000001F) |
| #define | TIM_DCR_DBA_0 ((uint32_t)0x00000001) |
| #define | TIM_DCR_DBA_1 ((uint32_t)0x00000002) |
| #define | TIM_DCR_DBA_2 ((uint32_t)0x00000004) |
| #define | TIM_DCR_DBA_3 ((uint32_t)0x00000008) |
| #define | TIM_DCR_DBA_4 ((uint32_t)0x00000010) |
| #define | TIM_DCR_DBL ((uint32_t)0x00001F00) |
| #define | TIM_DCR_DBL_0 ((uint32_t)0x00000100) |
| #define | TIM_DCR_DBL_1 ((uint32_t)0x00000200) |
| #define | TIM_DCR_DBL_2 ((uint32_t)0x00000400) |
| #define | TIM_DCR_DBL_3 ((uint32_t)0x00000800) |
| #define | TIM_DCR_DBL_4 ((uint32_t)0x00001000) |
| #define | TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) |
| #define | RTC_CRH_SECIE ((uint32_t)0x00000001) |
| #define | RTC_CRH_ALRIE ((uint32_t)0x00000002) |
| #define | RTC_CRH_OWIE ((uint32_t)0x00000004) |
| #define | RTC_CRL_SECF ((uint32_t)0x00000001) |
| #define | RTC_CRL_ALRF ((uint32_t)0x00000002) |
| #define | RTC_CRL_OWF ((uint32_t)0x00000004) |
| #define | RTC_CRL_RSF ((uint32_t)0x00000008) |
| #define | RTC_CRL_CNF ((uint32_t)0x00000010) |
| #define | RTC_CRL_RTOFF ((uint32_t)0x00000020) |
| #define | RTC_PRLH_PRL ((uint32_t)0x0000000F) |
| #define | RTC_PRLL_PRL ((uint32_t)0x0000FFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) |
| #define | RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | IWDG_KR_KEY ((uint32_t)0x0000FFFF) |
| #define | IWDG_PR_PR ((uint32_t)0x00000007) |
| #define | IWDG_PR_PR_0 ((uint32_t)0x00000001) |
| #define | IWDG_PR_PR_1 ((uint32_t)0x00000002) |
| #define | IWDG_PR_PR_2 ((uint32_t)0x00000004) |
| #define | IWDG_RLR_RL ((uint32_t)0x00000FFF) |
| #define | IWDG_SR_PVU ((uint32_t)0x00000001) |
| #define | IWDG_SR_RVU ((uint32_t)0x00000002) |
| #define | WWDG_CR_T ((uint32_t)0x0000007F) |
| #define | WWDG_CR_T0 ((uint32_t)0x00000001) |
| #define | WWDG_CR_T1 ((uint32_t)0x00000002) |
| #define | WWDG_CR_T2 ((uint32_t)0x00000004) |
| #define | WWDG_CR_T3 ((uint32_t)0x00000008) |
| #define | WWDG_CR_T4 ((uint32_t)0x00000010) |
| #define | WWDG_CR_T5 ((uint32_t)0x00000020) |
| #define | WWDG_CR_T6 ((uint32_t)0x00000040) |
| #define | WWDG_CR_WDGA ((uint32_t)0x00000080) |
| #define | WWDG_CFR_W ((uint32_t)0x0000007F) |
| #define | WWDG_CFR_W0 ((uint32_t)0x00000001) |
| #define | WWDG_CFR_W1 ((uint32_t)0x00000002) |
| #define | WWDG_CFR_W2 ((uint32_t)0x00000004) |
| #define | WWDG_CFR_W3 ((uint32_t)0x00000008) |
| #define | WWDG_CFR_W4 ((uint32_t)0x00000010) |
| #define | WWDG_CFR_W5 ((uint32_t)0x00000020) |
| #define | WWDG_CFR_W6 ((uint32_t)0x00000040) |
| #define | WWDG_CFR_WDGTB ((uint32_t)0x00000180) |
| #define | WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) |
| #define | WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) |
| #define | WWDG_CFR_EWI ((uint32_t)0x00000200) |
| #define | WWDG_SR_EWIF ((uint32_t)0x00000001) |
| #define | SDIO_POWER_PWRCTRL ((uint32_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint32_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint32_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint32_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint32_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint32_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint32_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint32_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint32_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint32_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint32_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint32_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint32_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint32_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint32_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint32_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | USB_EP0R USB_BASE |
| #define | USB_EP1R (USB_BASE + 0x00000004) |
| #define | USB_EP2R (USB_BASE + 0x00000008) |
| #define | USB_EP3R (USB_BASE + 0x0000000C) |
| #define | USB_EP4R (USB_BASE + 0x00000010) |
| #define | USB_EP5R (USB_BASE + 0x00000014) |
| #define | USB_EP6R (USB_BASE + 0x00000018) |
| #define | USB_EP7R (USB_BASE + 0x0000001C) |
| #define | USB_EP_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EPRX_STAT ((uint32_t)0x00003000) |
| #define | USB_EP_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP_T_FIELD ((uint32_t)0x00000600) |
| #define | USB_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EPTX_STAT ((uint32_t)0x00000030) |
| #define | USB_EPADDR_FIELD ((uint32_t)0x0000000F) |
| #define | USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) |
| #define | USB_EP_TYPE_MASK ((uint32_t)0x00000600) |
| #define | USB_EP_BULK ((uint32_t)0x00000000) |
| #define | USB_EP_CONTROL ((uint32_t)0x00000200) |
| #define | USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) |
| #define | USB_EP_INTERRUPT ((uint32_t)0x00000600) |
| #define | USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) |
| #define | USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) |
| #define | USB_EP_TX_DIS ((uint32_t)0x00000000) |
| #define | USB_EP_TX_STALL ((uint32_t)0x00000010) |
| #define | USB_EP_TX_NAK ((uint32_t)0x00000020) |
| #define | USB_EP_TX_VALID ((uint32_t)0x00000030) |
| #define | USB_EPTX_DTOG1 ((uint32_t)0x00000010) |
| #define | USB_EPTX_DTOG2 ((uint32_t)0x00000020) |
| #define | USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) |
| #define | USB_EP_RX_DIS ((uint32_t)0x00000000) |
| #define | USB_EP_RX_STALL ((uint32_t)0x00001000) |
| #define | USB_EP_RX_NAK ((uint32_t)0x00002000) |
| #define | USB_EP_RX_VALID ((uint32_t)0x00003000) |
| #define | USB_EPRX_DTOG1 ((uint32_t)0x00001000) |
| #define | USB_EPRX_DTOG2 ((uint32_t)0x00002000) |
| #define | USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) |
| #define | USB_EP0R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP0R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP0R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP0R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP0R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP0R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP0R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP0R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP0R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP0R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP1R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP1R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP1R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP1R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP1R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP1R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP1R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP1R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP1R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP1R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP2R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP2R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP2R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP2R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP2R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP2R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP2R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP2R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP2R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP2R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP3R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP3R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP3R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP3R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP3R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP3R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP3R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP3R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP3R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP3R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP4R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP4R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP4R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP4R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP4R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP4R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP4R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP4R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP4R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP4R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP5R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP5R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP5R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP5R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP5R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP5R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP5R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP5R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP5R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP5R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP6R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP6R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP6R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP6R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP6R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP6R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP6R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP6R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP6R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP6R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP7R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP7R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP7R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP7R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP7R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP7R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP7R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP7R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP7R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP7R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_CNTR_FRES ((uint32_t)0x00000001) |
| #define | USB_CNTR_PDWN ((uint32_t)0x00000002) |
| #define | USB_CNTR_LP_MODE ((uint32_t)0x00000004) |
| #define | USB_CNTR_FSUSP ((uint32_t)0x00000008) |
| #define | USB_CNTR_RESUME ((uint32_t)0x00000010) |
| #define | USB_CNTR_ESOFM ((uint32_t)0x00000100) |
| #define | USB_CNTR_SOFM ((uint32_t)0x00000200) |
| #define | USB_CNTR_RESETM ((uint32_t)0x00000400) |
| #define | USB_CNTR_SUSPM ((uint32_t)0x00000800) |
| #define | USB_CNTR_WKUPM ((uint32_t)0x00001000) |
| #define | USB_CNTR_ERRM ((uint32_t)0x00002000) |
| #define | USB_CNTR_PMAOVRM ((uint32_t)0x00004000) |
| #define | USB_CNTR_CTRM ((uint32_t)0x00008000) |
| #define | USB_ISTR_EP_ID ((uint32_t)0x0000000F) |
| #define | USB_ISTR_DIR ((uint32_t)0x00000010) |
| #define | USB_ISTR_ESOF ((uint32_t)0x00000100) |
| #define | USB_ISTR_SOF ((uint32_t)0x00000200) |
| #define | USB_ISTR_RESET ((uint32_t)0x00000400) |
| #define | USB_ISTR_SUSP ((uint32_t)0x00000800) |
| #define | USB_ISTR_WKUP ((uint32_t)0x00001000) |
| #define | USB_ISTR_ERR ((uint32_t)0x00002000) |
| #define | USB_ISTR_PMAOVR ((uint32_t)0x00004000) |
| #define | USB_ISTR_CTR ((uint32_t)0x00008000) |
| #define | USB_FNR_FN ((uint32_t)0x000007FF) |
| #define | USB_FNR_LSOF ((uint32_t)0x00001800) |
| #define | USB_FNR_LCK ((uint32_t)0x00002000) |
| #define | USB_FNR_RXDM ((uint32_t)0x00004000) |
| #define | USB_FNR_RXDP ((uint32_t)0x00008000) |
| #define | USB_DADDR_ADD ((uint32_t)0x0000007F) |
| #define | USB_DADDR_ADD0 ((uint32_t)0x00000001) |
| #define | USB_DADDR_ADD1 ((uint32_t)0x00000002) |
| #define | USB_DADDR_ADD2 ((uint32_t)0x00000004) |
| #define | USB_DADDR_ADD3 ((uint32_t)0x00000008) |
| #define | USB_DADDR_ADD4 ((uint32_t)0x00000010) |
| #define | USB_DADDR_ADD5 ((uint32_t)0x00000020) |
| #define | USB_DADDR_ADD6 ((uint32_t)0x00000040) |
| #define | USB_DADDR_EF ((uint32_t)0x00000080) |
| #define | USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) |
| #define | USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) |
| #define | USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) |
| #define | USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | SPI_CR1_CPHA ((uint32_t)0x00000001) |
| #define | SPI_CR1_CPOL ((uint32_t)0x00000002) |
| #define | SPI_CR1_MSTR ((uint32_t)0x00000004) |
| #define | SPI_CR1_BR ((uint32_t)0x00000038) |
| #define | SPI_CR1_BR_0 ((uint32_t)0x00000008) |
| #define | SPI_CR1_BR_1 ((uint32_t)0x00000010) |
| #define | SPI_CR1_BR_2 ((uint32_t)0x00000020) |
| #define | SPI_CR1_SPE ((uint32_t)0x00000040) |
| #define | SPI_CR1_LSBFIRST ((uint32_t)0x00000080) |
| #define | SPI_CR1_SSI ((uint32_t)0x00000100) |
| #define | SPI_CR1_SSM ((uint32_t)0x00000200) |
| #define | SPI_CR1_RXONLY ((uint32_t)0x00000400) |
| #define | SPI_CR1_DFF ((uint32_t)0x00000800) |
| #define | SPI_CR1_CRCNEXT ((uint32_t)0x00001000) |
| #define | SPI_CR1_CRCEN ((uint32_t)0x00002000) |
| #define | SPI_CR1_BIDIOE ((uint32_t)0x00004000) |
| #define | SPI_CR1_BIDIMODE ((uint32_t)0x00008000) |
| #define | SPI_CR2_RXDMAEN ((uint32_t)0x00000001) |
| #define | SPI_CR2_TXDMAEN ((uint32_t)0x00000002) |
| #define | SPI_CR2_SSOE ((uint32_t)0x00000004) |
| #define | SPI_CR2_ERRIE ((uint32_t)0x00000020) |
| #define | SPI_CR2_RXNEIE ((uint32_t)0x00000040) |
| #define | SPI_CR2_TXEIE ((uint32_t)0x00000080) |
| #define | SPI_SR_RXNE ((uint32_t)0x00000001) |
| #define | SPI_SR_TXE ((uint32_t)0x00000002) |
| #define | SPI_SR_CHSIDE ((uint32_t)0x00000004) |
| #define | SPI_SR_UDR ((uint32_t)0x00000008) |
| #define | SPI_SR_CRCERR ((uint32_t)0x00000010) |
| #define | SPI_SR_MODF ((uint32_t)0x00000020) |
| #define | SPI_SR_OVR ((uint32_t)0x00000040) |
| #define | SPI_SR_BSY ((uint32_t)0x00000080) |
| #define | SPI_DR_DR ((uint32_t)0x0000FFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_SMBUS ((uint32_t)0x00000002) |
| #define | I2C_CR1_SMBTYPE ((uint32_t)0x00000008) |
| #define | I2C_CR1_ENARP ((uint32_t)0x00000010) |
| #define | I2C_CR1_ENPEC ((uint32_t)0x00000020) |
| #define | I2C_CR1_ENGC ((uint32_t)0x00000040) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) |
| #define | I2C_CR1_START ((uint32_t)0x00000100) |
| #define | I2C_CR1_STOP ((uint32_t)0x00000200) |
| #define | I2C_CR1_ACK ((uint32_t)0x00000400) |
| #define | I2C_CR1_POS ((uint32_t)0x00000800) |
| #define | I2C_CR1_PEC ((uint32_t)0x00001000) |
| #define | I2C_CR1_ALERT ((uint32_t)0x00002000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00008000) |
| #define | I2C_CR2_FREQ ((uint32_t)0x0000003F) |
| #define | I2C_CR2_FREQ_0 ((uint32_t)0x00000001) |
| #define | I2C_CR2_FREQ_1 ((uint32_t)0x00000002) |
| #define | I2C_CR2_FREQ_2 ((uint32_t)0x00000004) |
| #define | I2C_CR2_FREQ_3 ((uint32_t)0x00000008) |
| #define | I2C_CR2_FREQ_4 ((uint32_t)0x00000010) |
| #define | I2C_CR2_FREQ_5 ((uint32_t)0x00000020) |
| #define | I2C_CR2_ITERREN ((uint32_t)0x00000100) |
| #define | I2C_CR2_ITEVTEN ((uint32_t)0x00000200) |
| #define | I2C_CR2_ITBUFEN ((uint32_t)0x00000400) |
| #define | I2C_CR2_DMAEN ((uint32_t)0x00000800) |
| #define | I2C_CR2_LAST ((uint32_t)0x00001000) |
| #define | I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) |
| #define | I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) |
| #define | I2C_OAR1_ADD0 ((uint32_t)0x00000001) |
| #define | I2C_OAR1_ADD1 ((uint32_t)0x00000002) |
| #define | I2C_OAR1_ADD2 ((uint32_t)0x00000004) |
| #define | I2C_OAR1_ADD3 ((uint32_t)0x00000008) |
| #define | I2C_OAR1_ADD4 ((uint32_t)0x00000010) |
| #define | I2C_OAR1_ADD5 ((uint32_t)0x00000020) |
| #define | I2C_OAR1_ADD6 ((uint32_t)0x00000040) |
| #define | I2C_OAR1_ADD7 ((uint32_t)0x00000080) |
| #define | I2C_OAR1_ADD8 ((uint32_t)0x00000100) |
| #define | I2C_OAR1_ADD9 ((uint32_t)0x00000200) |
| #define | I2C_OAR1_ADDMODE ((uint32_t)0x00008000) |
| #define | I2C_OAR2_ENDUAL ((uint32_t)0x00000001) |
| #define | I2C_OAR2_ADD2 ((uint32_t)0x000000FE) |
| #define | I2C_SR1_SB ((uint32_t)0x00000001) |
| #define | I2C_SR1_ADDR ((uint32_t)0x00000002) |
| #define | I2C_SR1_BTF ((uint32_t)0x00000004) |
| #define | I2C_SR1_ADD10 ((uint32_t)0x00000008) |
| #define | I2C_SR1_STOPF ((uint32_t)0x00000010) |
| #define | I2C_SR1_RXNE ((uint32_t)0x00000040) |
| #define | I2C_SR1_TXE ((uint32_t)0x00000080) |
| #define | I2C_SR1_BERR ((uint32_t)0x00000100) |
| #define | I2C_SR1_ARLO ((uint32_t)0x00000200) |
| #define | I2C_SR1_AF ((uint32_t)0x00000400) |
| #define | I2C_SR1_OVR ((uint32_t)0x00000800) |
| #define | I2C_SR1_PECERR ((uint32_t)0x00001000) |
| #define | I2C_SR1_TIMEOUT ((uint32_t)0x00004000) |
| #define | I2C_SR1_SMBALERT ((uint32_t)0x00008000) |
| #define | I2C_SR2_MSL ((uint32_t)0x00000001) |
| #define | I2C_SR2_BUSY ((uint32_t)0x00000002) |
| #define | I2C_SR2_TRA ((uint32_t)0x00000004) |
| #define | I2C_SR2_GENCALL ((uint32_t)0x00000010) |
| #define | I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) |
| #define | I2C_SR2_SMBHOST ((uint32_t)0x00000040) |
| #define | I2C_SR2_DUALF ((uint32_t)0x00000080) |
| #define | I2C_SR2_PEC ((uint32_t)0x0000FF00) |
| #define | I2C_CCR_CCR ((uint32_t)0x00000FFF) |
| #define | I2C_CCR_DUTY ((uint32_t)0x00004000) |
| #define | I2C_CCR_FS ((uint32_t)0x00008000) |
| #define | I2C_TRISE_TRISE ((uint32_t)0x0000003F) |
| #define | USART_SR_PE ((uint32_t)0x00000001) |
| #define | USART_SR_FE ((uint32_t)0x00000002) |
| #define | USART_SR_NE ((uint32_t)0x00000004) |
| #define | USART_SR_ORE ((uint32_t)0x00000008) |
| #define | USART_SR_IDLE ((uint32_t)0x00000010) |
| #define | USART_SR_RXNE ((uint32_t)0x00000020) |
| #define | USART_SR_TC ((uint32_t)0x00000040) |
| #define | USART_SR_TXE ((uint32_t)0x00000080) |
| #define | USART_SR_LBD ((uint32_t)0x00000100) |
| #define | USART_SR_CTS ((uint32_t)0x00000200) |
| #define | USART_DR_DR ((uint32_t)0x000001FF) |
| #define | USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) |
| #define | USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) |
| #define | USART_CR1_SBK ((uint32_t)0x00000001) |
| #define | USART_CR1_RWU ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_UE ((uint32_t)0x00002000) |
| #define | USART_CR2_ADD ((uint32_t)0x0000000F) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_GTPR_PSC ((uint32_t)0x000000FF) |
| #define | USART_GTPR_PSC_0 ((uint32_t)0x00000001) |
| #define | USART_GTPR_PSC_1 ((uint32_t)0x00000002) |
| #define | USART_GTPR_PSC_2 ((uint32_t)0x00000004) |
| #define | USART_GTPR_PSC_3 ((uint32_t)0x00000008) |
| #define | USART_GTPR_PSC_4 ((uint32_t)0x00000010) |
| #define | USART_GTPR_PSC_5 ((uint32_t)0x00000020) |
| #define | USART_GTPR_PSC_6 ((uint32_t)0x00000040) |
| #define | USART_GTPR_PSC_7 ((uint32_t)0x00000080) |
| #define | USART_GTPR_GT ((uint32_t)0x0000FF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) |
| #define | FLASH_ACR_HLFCYA ((uint32_t)0x00000008) |
| #define | FLASH_ACR_PRFTBE ((uint32_t)0x00000010) |
| #define | FLASH_ACR_PRFTBS ((uint32_t)0x00000020) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint32_t)0x000000A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT ((uint32_t)0x00000002) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) |
| #define | FLASH_OBR_USER ((uint32_t)0x0000001C) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) |
| #define | FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) |
| #define | FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) |
| #define | FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint32_t)0x000000FF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V2 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_2V3 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_2V4 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2V5 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_2V6 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | BKP_DR1_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR2_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR3_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR4_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR5_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR6_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR7_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR8_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR9_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR10_D ((uint32_t)0x0000FFFF) |
| #define | RTC_BKP_NUMBER 10 |
| #define | BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
| #define | BKP_RTCCR_CCO ((uint32_t)0x00000080) |
| #define | BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
| #define | BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
| #define | BKP_CR_TPE ((uint32_t)0x00000001) |
| #define | BKP_CR_TPAL ((uint32_t)0x00000002) |
| #define | BKP_CSR_CTE ((uint32_t)0x00000001) |
| #define | BKP_CSR_CTI ((uint32_t)0x00000002) |
| #define | BKP_CSR_TPIE ((uint32_t)0x00000004) |
| #define | BKP_CSR_TEF ((uint32_t)0x00000100) |
| #define | BKP_CSR_TIF ((uint32_t)0x00000200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_USBPRE ((uint32_t)0x00400000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_USBEN ((uint32_t)0x00800000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint32_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint32_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint32_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint32_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint32_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint32_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint32_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint32_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint32_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint32_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint32_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint32_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint32_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint32_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint32_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint32_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint32_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint32_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint32_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint32_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint32_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint32_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint32_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint32_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint32_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint32_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint32_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint32_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint32_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint32_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint32_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint32_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint32_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint32_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint32_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint32_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint32_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint32_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint32_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint32_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint32_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint32_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint32_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint32_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint32_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint32_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint32_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint32_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
| #define | AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
| #define | AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
| #define | AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
| #define | AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
| #define | AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PORT ((uint32_t)0x00000070) |
| #define | AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
| #define | AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) |
| #define | AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) |
| #define | AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) |
| #define | SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) |
| #define | SCB_SCR_SEVONPEND ((uint32_t)0x00000010) |
| #define | SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) |
| #define | SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) |
| #define | SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) |
| #define | SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) |
| #define | SCB_CCR_STKALIGN ((uint32_t)0x00000200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint32_t)0x00000001) |
| #define | SCB_DFSR_BKPT ((uint32_t)0x00000002) |
| #define | SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) |
| #define | SCB_DFSR_VCATCH ((uint32_t)0x00000008) |
| #define | SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
| #define | ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
| #define | ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
| #define | ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
| #define | ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
| #define | TIM_CR1_CEN ((uint32_t)0x00000001) |
| #define | TIM_CR1_UDIS ((uint32_t)0x00000002) |
| #define | TIM_CR1_URS ((uint32_t)0x00000004) |
| #define | TIM_CR1_OPM ((uint32_t)0x00000008) |
| #define | TIM_CR1_DIR ((uint32_t)0x00000010) |
| #define | TIM_CR1_CMS ((uint32_t)0x00000060) |
| #define | TIM_CR1_CMS_0 ((uint32_t)0x00000020) |
| #define | TIM_CR1_CMS_1 ((uint32_t)0x00000040) |
| #define | TIM_CR1_ARPE ((uint32_t)0x00000080) |
| #define | TIM_CR1_CKD ((uint32_t)0x00000300) |
| #define | TIM_CR1_CKD_0 ((uint32_t)0x00000100) |
| #define | TIM_CR1_CKD_1 ((uint32_t)0x00000200) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00000007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint32_t)0x00000001) |
| #define | TIM_DIER_CC1IE ((uint32_t)0x00000002) |
| #define | TIM_DIER_CC2IE ((uint32_t)0x00000004) |
| #define | TIM_DIER_CC3IE ((uint32_t)0x00000008) |
| #define | TIM_DIER_CC4IE ((uint32_t)0x00000010) |
| #define | TIM_DIER_COMIE ((uint32_t)0x00000020) |
| #define | TIM_DIER_TIE ((uint32_t)0x00000040) |
| #define | TIM_DIER_BIE ((uint32_t)0x00000080) |
| #define | TIM_DIER_UDE ((uint32_t)0x00000100) |
| #define | TIM_DIER_CC1DE ((uint32_t)0x00000200) |
| #define | TIM_DIER_CC2DE ((uint32_t)0x00000400) |
| #define | TIM_DIER_CC3DE ((uint32_t)0x00000800) |
| #define | TIM_DIER_CC4DE ((uint32_t)0x00001000) |
| #define | TIM_DIER_COMDE ((uint32_t)0x00002000) |
| #define | TIM_DIER_TDE ((uint32_t)0x00004000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_EGR_UG ((uint32_t)0x00000001) |
| #define | TIM_EGR_CC1G ((uint32_t)0x00000002) |
| #define | TIM_EGR_CC2G ((uint32_t)0x00000004) |
| #define | TIM_EGR_CC3G ((uint32_t)0x00000008) |
| #define | TIM_EGR_CC4G ((uint32_t)0x00000010) |
| #define | TIM_EGR_COMG ((uint32_t)0x00000020) |
| #define | TIM_EGR_TG ((uint32_t)0x00000040) |
| #define | TIM_EGR_BG ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00000070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x00007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_PSC_PSC ((uint32_t)0x0000FFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint32_t)0x000000FF) |
| #define | TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_DCR_DBA ((uint32_t)0x0000001F) |
| #define | TIM_DCR_DBA_0 ((uint32_t)0x00000001) |
| #define | TIM_DCR_DBA_1 ((uint32_t)0x00000002) |
| #define | TIM_DCR_DBA_2 ((uint32_t)0x00000004) |
| #define | TIM_DCR_DBA_3 ((uint32_t)0x00000008) |
| #define | TIM_DCR_DBA_4 ((uint32_t)0x00000010) |
| #define | TIM_DCR_DBL ((uint32_t)0x00001F00) |
| #define | TIM_DCR_DBL_0 ((uint32_t)0x00000100) |
| #define | TIM_DCR_DBL_1 ((uint32_t)0x00000200) |
| #define | TIM_DCR_DBL_2 ((uint32_t)0x00000400) |
| #define | TIM_DCR_DBL_3 ((uint32_t)0x00000800) |
| #define | TIM_DCR_DBL_4 ((uint32_t)0x00001000) |
| #define | TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) |
| #define | RTC_CRH_SECIE ((uint32_t)0x00000001) |
| #define | RTC_CRH_ALRIE ((uint32_t)0x00000002) |
| #define | RTC_CRH_OWIE ((uint32_t)0x00000004) |
| #define | RTC_CRL_SECF ((uint32_t)0x00000001) |
| #define | RTC_CRL_ALRF ((uint32_t)0x00000002) |
| #define | RTC_CRL_OWF ((uint32_t)0x00000004) |
| #define | RTC_CRL_RSF ((uint32_t)0x00000008) |
| #define | RTC_CRL_CNF ((uint32_t)0x00000010) |
| #define | RTC_CRL_RTOFF ((uint32_t)0x00000020) |
| #define | RTC_PRLH_PRL ((uint32_t)0x0000000F) |
| #define | RTC_PRLL_PRL ((uint32_t)0x0000FFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) |
| #define | RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | IWDG_KR_KEY ((uint32_t)0x0000FFFF) |
| #define | IWDG_PR_PR ((uint32_t)0x00000007) |
| #define | IWDG_PR_PR_0 ((uint32_t)0x00000001) |
| #define | IWDG_PR_PR_1 ((uint32_t)0x00000002) |
| #define | IWDG_PR_PR_2 ((uint32_t)0x00000004) |
| #define | IWDG_RLR_RL ((uint32_t)0x00000FFF) |
| #define | IWDG_SR_PVU ((uint32_t)0x00000001) |
| #define | IWDG_SR_RVU ((uint32_t)0x00000002) |
| #define | WWDG_CR_T ((uint32_t)0x0000007F) |
| #define | WWDG_CR_T0 ((uint32_t)0x00000001) |
| #define | WWDG_CR_T1 ((uint32_t)0x00000002) |
| #define | WWDG_CR_T2 ((uint32_t)0x00000004) |
| #define | WWDG_CR_T3 ((uint32_t)0x00000008) |
| #define | WWDG_CR_T4 ((uint32_t)0x00000010) |
| #define | WWDG_CR_T5 ((uint32_t)0x00000020) |
| #define | WWDG_CR_T6 ((uint32_t)0x00000040) |
| #define | WWDG_CR_WDGA ((uint32_t)0x00000080) |
| #define | WWDG_CFR_W ((uint32_t)0x0000007F) |
| #define | WWDG_CFR_W0 ((uint32_t)0x00000001) |
| #define | WWDG_CFR_W1 ((uint32_t)0x00000002) |
| #define | WWDG_CFR_W2 ((uint32_t)0x00000004) |
| #define | WWDG_CFR_W3 ((uint32_t)0x00000008) |
| #define | WWDG_CFR_W4 ((uint32_t)0x00000010) |
| #define | WWDG_CFR_W5 ((uint32_t)0x00000020) |
| #define | WWDG_CFR_W6 ((uint32_t)0x00000040) |
| #define | WWDG_CFR_WDGTB ((uint32_t)0x00000180) |
| #define | WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) |
| #define | WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) |
| #define | WWDG_CFR_EWI ((uint32_t)0x00000200) |
| #define | WWDG_SR_EWIF ((uint32_t)0x00000001) |
| #define | SDIO_POWER_PWRCTRL ((uint32_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint32_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint32_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint32_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint32_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint32_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint32_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint32_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint32_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint32_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint32_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint32_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint32_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint32_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint32_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint32_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | USB_EP0R USB_BASE |
| #define | USB_EP1R (USB_BASE + 0x00000004) |
| #define | USB_EP2R (USB_BASE + 0x00000008) |
| #define | USB_EP3R (USB_BASE + 0x0000000C) |
| #define | USB_EP4R (USB_BASE + 0x00000010) |
| #define | USB_EP5R (USB_BASE + 0x00000014) |
| #define | USB_EP6R (USB_BASE + 0x00000018) |
| #define | USB_EP7R (USB_BASE + 0x0000001C) |
| #define | USB_EP_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EPRX_STAT ((uint32_t)0x00003000) |
| #define | USB_EP_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP_T_FIELD ((uint32_t)0x00000600) |
| #define | USB_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EPTX_STAT ((uint32_t)0x00000030) |
| #define | USB_EPADDR_FIELD ((uint32_t)0x0000000F) |
| #define | USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) |
| #define | USB_EP_TYPE_MASK ((uint32_t)0x00000600) |
| #define | USB_EP_BULK ((uint32_t)0x00000000) |
| #define | USB_EP_CONTROL ((uint32_t)0x00000200) |
| #define | USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) |
| #define | USB_EP_INTERRUPT ((uint32_t)0x00000600) |
| #define | USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) |
| #define | USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) |
| #define | USB_EP_TX_DIS ((uint32_t)0x00000000) |
| #define | USB_EP_TX_STALL ((uint32_t)0x00000010) |
| #define | USB_EP_TX_NAK ((uint32_t)0x00000020) |
| #define | USB_EP_TX_VALID ((uint32_t)0x00000030) |
| #define | USB_EPTX_DTOG1 ((uint32_t)0x00000010) |
| #define | USB_EPTX_DTOG2 ((uint32_t)0x00000020) |
| #define | USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) |
| #define | USB_EP_RX_DIS ((uint32_t)0x00000000) |
| #define | USB_EP_RX_STALL ((uint32_t)0x00001000) |
| #define | USB_EP_RX_NAK ((uint32_t)0x00002000) |
| #define | USB_EP_RX_VALID ((uint32_t)0x00003000) |
| #define | USB_EPRX_DTOG1 ((uint32_t)0x00001000) |
| #define | USB_EPRX_DTOG2 ((uint32_t)0x00002000) |
| #define | USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) |
| #define | USB_EP0R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP0R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP0R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP0R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP0R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP0R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP0R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP0R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP0R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP0R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP1R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP1R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP1R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP1R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP1R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP1R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP1R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP1R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP1R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP1R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP2R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP2R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP2R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP2R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP2R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP2R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP2R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP2R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP2R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP2R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP3R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP3R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP3R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP3R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP3R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP3R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP3R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP3R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP3R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP3R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP4R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP4R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP4R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP4R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP4R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP4R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP4R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP4R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP4R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP4R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP5R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP5R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP5R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP5R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP5R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP5R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP5R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP5R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP5R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP5R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP6R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP6R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP6R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP6R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP6R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP6R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP6R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP6R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP6R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP6R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP7R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP7R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP7R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP7R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP7R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP7R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP7R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP7R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP7R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP7R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_CNTR_FRES ((uint32_t)0x00000001) |
| #define | USB_CNTR_PDWN ((uint32_t)0x00000002) |
| #define | USB_CNTR_LP_MODE ((uint32_t)0x00000004) |
| #define | USB_CNTR_FSUSP ((uint32_t)0x00000008) |
| #define | USB_CNTR_RESUME ((uint32_t)0x00000010) |
| #define | USB_CNTR_ESOFM ((uint32_t)0x00000100) |
| #define | USB_CNTR_SOFM ((uint32_t)0x00000200) |
| #define | USB_CNTR_RESETM ((uint32_t)0x00000400) |
| #define | USB_CNTR_SUSPM ((uint32_t)0x00000800) |
| #define | USB_CNTR_WKUPM ((uint32_t)0x00001000) |
| #define | USB_CNTR_ERRM ((uint32_t)0x00002000) |
| #define | USB_CNTR_PMAOVRM ((uint32_t)0x00004000) |
| #define | USB_CNTR_CTRM ((uint32_t)0x00008000) |
| #define | USB_ISTR_EP_ID ((uint32_t)0x0000000F) |
| #define | USB_ISTR_DIR ((uint32_t)0x00000010) |
| #define | USB_ISTR_ESOF ((uint32_t)0x00000100) |
| #define | USB_ISTR_SOF ((uint32_t)0x00000200) |
| #define | USB_ISTR_RESET ((uint32_t)0x00000400) |
| #define | USB_ISTR_SUSP ((uint32_t)0x00000800) |
| #define | USB_ISTR_WKUP ((uint32_t)0x00001000) |
| #define | USB_ISTR_ERR ((uint32_t)0x00002000) |
| #define | USB_ISTR_PMAOVR ((uint32_t)0x00004000) |
| #define | USB_ISTR_CTR ((uint32_t)0x00008000) |
| #define | USB_FNR_FN ((uint32_t)0x000007FF) |
| #define | USB_FNR_LSOF ((uint32_t)0x00001800) |
| #define | USB_FNR_LCK ((uint32_t)0x00002000) |
| #define | USB_FNR_RXDM ((uint32_t)0x00004000) |
| #define | USB_FNR_RXDP ((uint32_t)0x00008000) |
| #define | USB_DADDR_ADD ((uint32_t)0x0000007F) |
| #define | USB_DADDR_ADD0 ((uint32_t)0x00000001) |
| #define | USB_DADDR_ADD1 ((uint32_t)0x00000002) |
| #define | USB_DADDR_ADD2 ((uint32_t)0x00000004) |
| #define | USB_DADDR_ADD3 ((uint32_t)0x00000008) |
| #define | USB_DADDR_ADD4 ((uint32_t)0x00000010) |
| #define | USB_DADDR_ADD5 ((uint32_t)0x00000020) |
| #define | USB_DADDR_ADD6 ((uint32_t)0x00000040) |
| #define | USB_DADDR_EF ((uint32_t)0x00000080) |
| #define | USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) |
| #define | USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) |
| #define | USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) |
| #define | USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | CAN_MCR_INRQ ((uint32_t)0x00000001) |
| #define | CAN_MCR_SLEEP ((uint32_t)0x00000002) |
| #define | CAN_MCR_TXFP ((uint32_t)0x00000004) |
| #define | CAN_MCR_RFLM ((uint32_t)0x00000008) |
| #define | CAN_MCR_NART ((uint32_t)0x00000010) |
| #define | CAN_MCR_AWUM ((uint32_t)0x00000020) |
| #define | CAN_MCR_ABOM ((uint32_t)0x00000040) |
| #define | CAN_MCR_TTCM ((uint32_t)0x00000080) |
| #define | CAN_MCR_RESET ((uint32_t)0x00008000) |
| #define | CAN_MCR_DBF ((uint32_t)0x00010000) |
| #define | CAN_MSR_INAK ((uint32_t)0x00000001) |
| #define | CAN_MSR_SLAK ((uint32_t)0x00000002) |
| #define | CAN_MSR_ERRI ((uint32_t)0x00000004) |
| #define | CAN_MSR_WKUI ((uint32_t)0x00000008) |
| #define | CAN_MSR_SLAKI ((uint32_t)0x00000010) |
| #define | CAN_MSR_TXM ((uint32_t)0x00000100) |
| #define | CAN_MSR_RXM ((uint32_t)0x00000200) |
| #define | CAN_MSR_SAMP ((uint32_t)0x00000400) |
| #define | CAN_MSR_RX ((uint32_t)0x00000800) |
| #define | CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
| #define | CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
| #define | CAN_TSR_ALST0 ((uint32_t)0x00000004) |
| #define | CAN_TSR_TERR0 ((uint32_t)0x00000008) |
| #define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
| #define | CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
| #define | CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
| #define | CAN_TSR_ALST1 ((uint32_t)0x00000400) |
| #define | CAN_TSR_TERR1 ((uint32_t)0x00000800) |
| #define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
| #define | CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
| #define | CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
| #define | CAN_TSR_ALST2 ((uint32_t)0x00040000) |
| #define | CAN_TSR_TERR2 ((uint32_t)0x00080000) |
| #define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
| #define | CAN_TSR_CODE ((uint32_t)0x03000000) |
| #define | CAN_TSR_TME ((uint32_t)0x1C000000) |
| #define | CAN_TSR_TME0 ((uint32_t)0x04000000) |
| #define | CAN_TSR_TME1 ((uint32_t)0x08000000) |
| #define | CAN_TSR_TME2 ((uint32_t)0x10000000) |
| #define | CAN_TSR_LOW ((uint32_t)0xE0000000) |
| #define | CAN_TSR_LOW0 ((uint32_t)0x20000000) |
| #define | CAN_TSR_LOW1 ((uint32_t)0x40000000) |
| #define | CAN_TSR_LOW2 ((uint32_t)0x80000000) |
| #define | CAN_RF0R_FMP0 ((uint32_t)0x00000003) |
| #define | CAN_RF0R_FULL0 ((uint32_t)0x00000008) |
| #define | CAN_RF0R_FOVR0 ((uint32_t)0x00000010) |
| #define | CAN_RF0R_RFOM0 ((uint32_t)0x00000020) |
| #define | CAN_RF1R_FMP1 ((uint32_t)0x00000003) |
| #define | CAN_RF1R_FULL1 ((uint32_t)0x00000008) |
| #define | CAN_RF1R_FOVR1 ((uint32_t)0x00000010) |
| #define | CAN_RF1R_RFOM1 ((uint32_t)0x00000020) |
| #define | CAN_IER_TMEIE ((uint32_t)0x00000001) |
| #define | CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
| #define | CAN_IER_FFIE0 ((uint32_t)0x00000004) |
| #define | CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
| #define | CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
| #define | CAN_IER_FFIE1 ((uint32_t)0x00000020) |
| #define | CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
| #define | CAN_IER_EWGIE ((uint32_t)0x00000100) |
| #define | CAN_IER_EPVIE ((uint32_t)0x00000200) |
| #define | CAN_IER_BOFIE ((uint32_t)0x00000400) |
| #define | CAN_IER_LECIE ((uint32_t)0x00000800) |
| #define | CAN_IER_ERRIE ((uint32_t)0x00008000) |
| #define | CAN_IER_WKUIE ((uint32_t)0x00010000) |
| #define | CAN_IER_SLKIE ((uint32_t)0x00020000) |
| #define | CAN_ESR_EWGF ((uint32_t)0x00000001) |
| #define | CAN_ESR_EPVF ((uint32_t)0x00000002) |
| #define | CAN_ESR_BOFF ((uint32_t)0x00000004) |
| #define | CAN_ESR_LEC ((uint32_t)0x00000070) |
| #define | CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
| #define | CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
| #define | CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
| #define | CAN_ESR_TEC ((uint32_t)0x00FF0000) |
| #define | CAN_ESR_REC ((uint32_t)0xFF000000) |
| #define | CAN_BTR_BRP ((uint32_t)0x000003FF) |
| #define | CAN_BTR_TS1 ((uint32_t)0x000F0000) |
| #define | CAN_BTR_TS1_0 ((uint32_t)0x00010000) |
| #define | CAN_BTR_TS1_1 ((uint32_t)0x00020000) |
| #define | CAN_BTR_TS1_2 ((uint32_t)0x00040000) |
| #define | CAN_BTR_TS1_3 ((uint32_t)0x00080000) |
| #define | CAN_BTR_TS2 ((uint32_t)0x00700000) |
| #define | CAN_BTR_TS2_0 ((uint32_t)0x00100000) |
| #define | CAN_BTR_TS2_1 ((uint32_t)0x00200000) |
| #define | CAN_BTR_TS2_2 ((uint32_t)0x00400000) |
| #define | CAN_BTR_SJW ((uint32_t)0x03000000) |
| #define | CAN_BTR_SJW_0 ((uint32_t)0x01000000) |
| #define | CAN_BTR_SJW_1 ((uint32_t)0x02000000) |
| #define | CAN_BTR_LBKM ((uint32_t)0x40000000) |
| #define | CAN_BTR_SILM ((uint32_t)0x80000000) |
| #define | CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT0R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT1R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI2R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI2R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI2R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT2R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_FMR_FINIT ((uint32_t)0x00000001) |
| #define | CAN_FMR_CAN2SB ((uint32_t)0x00003F00) |
| #define | CAN_FM1R_FBM ((uint32_t)0x00003FFF) |
| #define | CAN_FM1R_FBM0 ((uint32_t)0x00000001) |
| #define | CAN_FM1R_FBM1 ((uint32_t)0x00000002) |
| #define | CAN_FM1R_FBM2 ((uint32_t)0x00000004) |
| #define | CAN_FM1R_FBM3 ((uint32_t)0x00000008) |
| #define | CAN_FM1R_FBM4 ((uint32_t)0x00000010) |
| #define | CAN_FM1R_FBM5 ((uint32_t)0x00000020) |
| #define | CAN_FM1R_FBM6 ((uint32_t)0x00000040) |
| #define | CAN_FM1R_FBM7 ((uint32_t)0x00000080) |
| #define | CAN_FM1R_FBM8 ((uint32_t)0x00000100) |
| #define | CAN_FM1R_FBM9 ((uint32_t)0x00000200) |
| #define | CAN_FM1R_FBM10 ((uint32_t)0x00000400) |
| #define | CAN_FM1R_FBM11 ((uint32_t)0x00000800) |
| #define | CAN_FM1R_FBM12 ((uint32_t)0x00001000) |
| #define | CAN_FM1R_FBM13 ((uint32_t)0x00002000) |
| #define | CAN_FS1R_FSC ((uint32_t)0x00003FFF) |
| #define | CAN_FS1R_FSC0 ((uint32_t)0x00000001) |
| #define | CAN_FS1R_FSC1 ((uint32_t)0x00000002) |
| #define | CAN_FS1R_FSC2 ((uint32_t)0x00000004) |
| #define | CAN_FS1R_FSC3 ((uint32_t)0x00000008) |
| #define | CAN_FS1R_FSC4 ((uint32_t)0x00000010) |
| #define | CAN_FS1R_FSC5 ((uint32_t)0x00000020) |
| #define | CAN_FS1R_FSC6 ((uint32_t)0x00000040) |
| #define | CAN_FS1R_FSC7 ((uint32_t)0x00000080) |
| #define | CAN_FS1R_FSC8 ((uint32_t)0x00000100) |
| #define | CAN_FS1R_FSC9 ((uint32_t)0x00000200) |
| #define | CAN_FS1R_FSC10 ((uint32_t)0x00000400) |
| #define | CAN_FS1R_FSC11 ((uint32_t)0x00000800) |
| #define | CAN_FS1R_FSC12 ((uint32_t)0x00001000) |
| #define | CAN_FS1R_FSC13 ((uint32_t)0x00002000) |
| #define | CAN_FFA1R_FFA ((uint32_t)0x00003FFF) |
| #define | CAN_FFA1R_FFA0 ((uint32_t)0x00000001) |
| #define | CAN_FFA1R_FFA1 ((uint32_t)0x00000002) |
| #define | CAN_FFA1R_FFA2 ((uint32_t)0x00000004) |
| #define | CAN_FFA1R_FFA3 ((uint32_t)0x00000008) |
| #define | CAN_FFA1R_FFA4 ((uint32_t)0x00000010) |
| #define | CAN_FFA1R_FFA5 ((uint32_t)0x00000020) |
| #define | CAN_FFA1R_FFA6 ((uint32_t)0x00000040) |
| #define | CAN_FFA1R_FFA7 ((uint32_t)0x00000080) |
| #define | CAN_FFA1R_FFA8 ((uint32_t)0x00000100) |
| #define | CAN_FFA1R_FFA9 ((uint32_t)0x00000200) |
| #define | CAN_FFA1R_FFA10 ((uint32_t)0x00000400) |
| #define | CAN_FFA1R_FFA11 ((uint32_t)0x00000800) |
| #define | CAN_FFA1R_FFA12 ((uint32_t)0x00001000) |
| #define | CAN_FFA1R_FFA13 ((uint32_t)0x00002000) |
| #define | CAN_FA1R_FACT ((uint32_t)0x00003FFF) |
| #define | CAN_FA1R_FACT0 ((uint32_t)0x00000001) |
| #define | CAN_FA1R_FACT1 ((uint32_t)0x00000002) |
| #define | CAN_FA1R_FACT2 ((uint32_t)0x00000004) |
| #define | CAN_FA1R_FACT3 ((uint32_t)0x00000008) |
| #define | CAN_FA1R_FACT4 ((uint32_t)0x00000010) |
| #define | CAN_FA1R_FACT5 ((uint32_t)0x00000020) |
| #define | CAN_FA1R_FACT6 ((uint32_t)0x00000040) |
| #define | CAN_FA1R_FACT7 ((uint32_t)0x00000080) |
| #define | CAN_FA1R_FACT8 ((uint32_t)0x00000100) |
| #define | CAN_FA1R_FACT9 ((uint32_t)0x00000200) |
| #define | CAN_FA1R_FACT10 ((uint32_t)0x00000400) |
| #define | CAN_FA1R_FACT11 ((uint32_t)0x00000800) |
| #define | CAN_FA1R_FACT12 ((uint32_t)0x00001000) |
| #define | CAN_FA1R_FACT13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F0R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R2_FB31 ((uint32_t)0x80000000) |
| #define | SPI_CR1_CPHA ((uint32_t)0x00000001) |
| #define | SPI_CR1_CPOL ((uint32_t)0x00000002) |
| #define | SPI_CR1_MSTR ((uint32_t)0x00000004) |
| #define | SPI_CR1_BR ((uint32_t)0x00000038) |
| #define | SPI_CR1_BR_0 ((uint32_t)0x00000008) |
| #define | SPI_CR1_BR_1 ((uint32_t)0x00000010) |
| #define | SPI_CR1_BR_2 ((uint32_t)0x00000020) |
| #define | SPI_CR1_SPE ((uint32_t)0x00000040) |
| #define | SPI_CR1_LSBFIRST ((uint32_t)0x00000080) |
| #define | SPI_CR1_SSI ((uint32_t)0x00000100) |
| #define | SPI_CR1_SSM ((uint32_t)0x00000200) |
| #define | SPI_CR1_RXONLY ((uint32_t)0x00000400) |
| #define | SPI_CR1_DFF ((uint32_t)0x00000800) |
| #define | SPI_CR1_CRCNEXT ((uint32_t)0x00001000) |
| #define | SPI_CR1_CRCEN ((uint32_t)0x00002000) |
| #define | SPI_CR1_BIDIOE ((uint32_t)0x00004000) |
| #define | SPI_CR1_BIDIMODE ((uint32_t)0x00008000) |
| #define | SPI_CR2_RXDMAEN ((uint32_t)0x00000001) |
| #define | SPI_CR2_TXDMAEN ((uint32_t)0x00000002) |
| #define | SPI_CR2_SSOE ((uint32_t)0x00000004) |
| #define | SPI_CR2_ERRIE ((uint32_t)0x00000020) |
| #define | SPI_CR2_RXNEIE ((uint32_t)0x00000040) |
| #define | SPI_CR2_TXEIE ((uint32_t)0x00000080) |
| #define | SPI_SR_RXNE ((uint32_t)0x00000001) |
| #define | SPI_SR_TXE ((uint32_t)0x00000002) |
| #define | SPI_SR_CHSIDE ((uint32_t)0x00000004) |
| #define | SPI_SR_UDR ((uint32_t)0x00000008) |
| #define | SPI_SR_CRCERR ((uint32_t)0x00000010) |
| #define | SPI_SR_MODF ((uint32_t)0x00000020) |
| #define | SPI_SR_OVR ((uint32_t)0x00000040) |
| #define | SPI_SR_BSY ((uint32_t)0x00000080) |
| #define | SPI_DR_DR ((uint32_t)0x0000FFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_SMBUS ((uint32_t)0x00000002) |
| #define | I2C_CR1_SMBTYPE ((uint32_t)0x00000008) |
| #define | I2C_CR1_ENARP ((uint32_t)0x00000010) |
| #define | I2C_CR1_ENPEC ((uint32_t)0x00000020) |
| #define | I2C_CR1_ENGC ((uint32_t)0x00000040) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) |
| #define | I2C_CR1_START ((uint32_t)0x00000100) |
| #define | I2C_CR1_STOP ((uint32_t)0x00000200) |
| #define | I2C_CR1_ACK ((uint32_t)0x00000400) |
| #define | I2C_CR1_POS ((uint32_t)0x00000800) |
| #define | I2C_CR1_PEC ((uint32_t)0x00001000) |
| #define | I2C_CR1_ALERT ((uint32_t)0x00002000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00008000) |
| #define | I2C_CR2_FREQ ((uint32_t)0x0000003F) |
| #define | I2C_CR2_FREQ_0 ((uint32_t)0x00000001) |
| #define | I2C_CR2_FREQ_1 ((uint32_t)0x00000002) |
| #define | I2C_CR2_FREQ_2 ((uint32_t)0x00000004) |
| #define | I2C_CR2_FREQ_3 ((uint32_t)0x00000008) |
| #define | I2C_CR2_FREQ_4 ((uint32_t)0x00000010) |
| #define | I2C_CR2_FREQ_5 ((uint32_t)0x00000020) |
| #define | I2C_CR2_ITERREN ((uint32_t)0x00000100) |
| #define | I2C_CR2_ITEVTEN ((uint32_t)0x00000200) |
| #define | I2C_CR2_ITBUFEN ((uint32_t)0x00000400) |
| #define | I2C_CR2_DMAEN ((uint32_t)0x00000800) |
| #define | I2C_CR2_LAST ((uint32_t)0x00001000) |
| #define | I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) |
| #define | I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) |
| #define | I2C_OAR1_ADD0 ((uint32_t)0x00000001) |
| #define | I2C_OAR1_ADD1 ((uint32_t)0x00000002) |
| #define | I2C_OAR1_ADD2 ((uint32_t)0x00000004) |
| #define | I2C_OAR1_ADD3 ((uint32_t)0x00000008) |
| #define | I2C_OAR1_ADD4 ((uint32_t)0x00000010) |
| #define | I2C_OAR1_ADD5 ((uint32_t)0x00000020) |
| #define | I2C_OAR1_ADD6 ((uint32_t)0x00000040) |
| #define | I2C_OAR1_ADD7 ((uint32_t)0x00000080) |
| #define | I2C_OAR1_ADD8 ((uint32_t)0x00000100) |
| #define | I2C_OAR1_ADD9 ((uint32_t)0x00000200) |
| #define | I2C_OAR1_ADDMODE ((uint32_t)0x00008000) |
| #define | I2C_OAR2_ENDUAL ((uint32_t)0x00000001) |
| #define | I2C_OAR2_ADD2 ((uint32_t)0x000000FE) |
| #define | I2C_SR1_SB ((uint32_t)0x00000001) |
| #define | I2C_SR1_ADDR ((uint32_t)0x00000002) |
| #define | I2C_SR1_BTF ((uint32_t)0x00000004) |
| #define | I2C_SR1_ADD10 ((uint32_t)0x00000008) |
| #define | I2C_SR1_STOPF ((uint32_t)0x00000010) |
| #define | I2C_SR1_RXNE ((uint32_t)0x00000040) |
| #define | I2C_SR1_TXE ((uint32_t)0x00000080) |
| #define | I2C_SR1_BERR ((uint32_t)0x00000100) |
| #define | I2C_SR1_ARLO ((uint32_t)0x00000200) |
| #define | I2C_SR1_AF ((uint32_t)0x00000400) |
| #define | I2C_SR1_OVR ((uint32_t)0x00000800) |
| #define | I2C_SR1_PECERR ((uint32_t)0x00001000) |
| #define | I2C_SR1_TIMEOUT ((uint32_t)0x00004000) |
| #define | I2C_SR1_SMBALERT ((uint32_t)0x00008000) |
| #define | I2C_SR2_MSL ((uint32_t)0x00000001) |
| #define | I2C_SR2_BUSY ((uint32_t)0x00000002) |
| #define | I2C_SR2_TRA ((uint32_t)0x00000004) |
| #define | I2C_SR2_GENCALL ((uint32_t)0x00000010) |
| #define | I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) |
| #define | I2C_SR2_SMBHOST ((uint32_t)0x00000040) |
| #define | I2C_SR2_DUALF ((uint32_t)0x00000080) |
| #define | I2C_SR2_PEC ((uint32_t)0x0000FF00) |
| #define | I2C_CCR_CCR ((uint32_t)0x00000FFF) |
| #define | I2C_CCR_DUTY ((uint32_t)0x00004000) |
| #define | I2C_CCR_FS ((uint32_t)0x00008000) |
| #define | I2C_TRISE_TRISE ((uint32_t)0x0000003F) |
| #define | USART_SR_PE ((uint32_t)0x00000001) |
| #define | USART_SR_FE ((uint32_t)0x00000002) |
| #define | USART_SR_NE ((uint32_t)0x00000004) |
| #define | USART_SR_ORE ((uint32_t)0x00000008) |
| #define | USART_SR_IDLE ((uint32_t)0x00000010) |
| #define | USART_SR_RXNE ((uint32_t)0x00000020) |
| #define | USART_SR_TC ((uint32_t)0x00000040) |
| #define | USART_SR_TXE ((uint32_t)0x00000080) |
| #define | USART_SR_LBD ((uint32_t)0x00000100) |
| #define | USART_SR_CTS ((uint32_t)0x00000200) |
| #define | USART_DR_DR ((uint32_t)0x000001FF) |
| #define | USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) |
| #define | USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) |
| #define | USART_CR1_SBK ((uint32_t)0x00000001) |
| #define | USART_CR1_RWU ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_UE ((uint32_t)0x00002000) |
| #define | USART_CR2_ADD ((uint32_t)0x0000000F) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_GTPR_PSC ((uint32_t)0x000000FF) |
| #define | USART_GTPR_PSC_0 ((uint32_t)0x00000001) |
| #define | USART_GTPR_PSC_1 ((uint32_t)0x00000002) |
| #define | USART_GTPR_PSC_2 ((uint32_t)0x00000004) |
| #define | USART_GTPR_PSC_3 ((uint32_t)0x00000008) |
| #define | USART_GTPR_PSC_4 ((uint32_t)0x00000010) |
| #define | USART_GTPR_PSC_5 ((uint32_t)0x00000020) |
| #define | USART_GTPR_PSC_6 ((uint32_t)0x00000040) |
| #define | USART_GTPR_PSC_7 ((uint32_t)0x00000080) |
| #define | USART_GTPR_GT ((uint32_t)0x0000FF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) |
| #define | FLASH_ACR_HLFCYA ((uint32_t)0x00000008) |
| #define | FLASH_ACR_PRFTBE ((uint32_t)0x00000010) |
| #define | FLASH_ACR_PRFTBS ((uint32_t)0x00000020) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint32_t)0x000000A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT ((uint32_t)0x00000002) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) |
| #define | FLASH_OBR_USER ((uint32_t)0x0000001C) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) |
| #define | FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) |
| #define | FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) |
| #define | FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint32_t)0x000000FF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V2 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_2V3 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_2V4 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2V5 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_2V6 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | BKP_DR1_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR2_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR3_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR4_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR5_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR6_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR7_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR8_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR9_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR10_D ((uint32_t)0x0000FFFF) |
| #define | RTC_BKP_NUMBER 10 |
| #define | BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
| #define | BKP_RTCCR_CCO ((uint32_t)0x00000080) |
| #define | BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
| #define | BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
| #define | BKP_CR_TPE ((uint32_t)0x00000001) |
| #define | BKP_CR_TPAL ((uint32_t)0x00000002) |
| #define | BKP_CSR_CTE ((uint32_t)0x00000001) |
| #define | BKP_CSR_CTI ((uint32_t)0x00000002) |
| #define | BKP_CSR_TPIE ((uint32_t)0x00000004) |
| #define | BKP_CSR_TEF ((uint32_t)0x00000100) |
| #define | BKP_CSR_TIF ((uint32_t)0x00000200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_USBPRE ((uint32_t)0x00400000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_USBEN ((uint32_t)0x00800000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint32_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint32_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint32_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint32_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint32_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint32_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint32_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint32_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint32_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint32_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint32_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint32_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint32_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint32_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint32_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint32_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint32_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint32_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint32_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint32_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint32_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint32_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint32_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint32_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint32_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint32_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint32_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint32_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint32_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint32_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint32_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint32_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint32_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint32_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint32_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint32_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint32_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint32_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint32_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint32_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint32_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint32_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint32_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint32_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint32_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint32_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint32_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint32_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
| #define | AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
| #define | AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
| #define | AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
| #define | AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
| #define | AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PORT ((uint32_t)0x00000070) |
| #define | AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
| #define | AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
| #define | AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
| #define | AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) |
| #define | AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) |
| #define | AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) |
| #define | SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) |
| #define | SCB_SCR_SEVONPEND ((uint32_t)0x00000010) |
| #define | SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) |
| #define | SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) |
| #define | SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) |
| #define | SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) |
| #define | SCB_CCR_STKALIGN ((uint32_t)0x00000200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint32_t)0x00000001) |
| #define | SCB_DFSR_BKPT ((uint32_t)0x00000002) |
| #define | SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) |
| #define | SCB_DFSR_VCATCH ((uint32_t)0x00000008) |
| #define | SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
| #define | ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
| #define | ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
| #define | ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
| #define | ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
| #define | TIM_CR1_CEN ((uint32_t)0x00000001) |
| #define | TIM_CR1_UDIS ((uint32_t)0x00000002) |
| #define | TIM_CR1_URS ((uint32_t)0x00000004) |
| #define | TIM_CR1_OPM ((uint32_t)0x00000008) |
| #define | TIM_CR1_DIR ((uint32_t)0x00000010) |
| #define | TIM_CR1_CMS ((uint32_t)0x00000060) |
| #define | TIM_CR1_CMS_0 ((uint32_t)0x00000020) |
| #define | TIM_CR1_CMS_1 ((uint32_t)0x00000040) |
| #define | TIM_CR1_ARPE ((uint32_t)0x00000080) |
| #define | TIM_CR1_CKD ((uint32_t)0x00000300) |
| #define | TIM_CR1_CKD_0 ((uint32_t)0x00000100) |
| #define | TIM_CR1_CKD_1 ((uint32_t)0x00000200) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00000007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint32_t)0x00000001) |
| #define | TIM_DIER_CC1IE ((uint32_t)0x00000002) |
| #define | TIM_DIER_CC2IE ((uint32_t)0x00000004) |
| #define | TIM_DIER_CC3IE ((uint32_t)0x00000008) |
| #define | TIM_DIER_CC4IE ((uint32_t)0x00000010) |
| #define | TIM_DIER_COMIE ((uint32_t)0x00000020) |
| #define | TIM_DIER_TIE ((uint32_t)0x00000040) |
| #define | TIM_DIER_BIE ((uint32_t)0x00000080) |
| #define | TIM_DIER_UDE ((uint32_t)0x00000100) |
| #define | TIM_DIER_CC1DE ((uint32_t)0x00000200) |
| #define | TIM_DIER_CC2DE ((uint32_t)0x00000400) |
| #define | TIM_DIER_CC3DE ((uint32_t)0x00000800) |
| #define | TIM_DIER_CC4DE ((uint32_t)0x00001000) |
| #define | TIM_DIER_COMDE ((uint32_t)0x00002000) |
| #define | TIM_DIER_TDE ((uint32_t)0x00004000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_EGR_UG ((uint32_t)0x00000001) |
| #define | TIM_EGR_CC1G ((uint32_t)0x00000002) |
| #define | TIM_EGR_CC2G ((uint32_t)0x00000004) |
| #define | TIM_EGR_CC3G ((uint32_t)0x00000008) |
| #define | TIM_EGR_CC4G ((uint32_t)0x00000010) |
| #define | TIM_EGR_COMG ((uint32_t)0x00000020) |
| #define | TIM_EGR_TG ((uint32_t)0x00000040) |
| #define | TIM_EGR_BG ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00000070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x00007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_PSC_PSC ((uint32_t)0x0000FFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint32_t)0x000000FF) |
| #define | TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_DCR_DBA ((uint32_t)0x0000001F) |
| #define | TIM_DCR_DBA_0 ((uint32_t)0x00000001) |
| #define | TIM_DCR_DBA_1 ((uint32_t)0x00000002) |
| #define | TIM_DCR_DBA_2 ((uint32_t)0x00000004) |
| #define | TIM_DCR_DBA_3 ((uint32_t)0x00000008) |
| #define | TIM_DCR_DBA_4 ((uint32_t)0x00000010) |
| #define | TIM_DCR_DBL ((uint32_t)0x00001F00) |
| #define | TIM_DCR_DBL_0 ((uint32_t)0x00000100) |
| #define | TIM_DCR_DBL_1 ((uint32_t)0x00000200) |
| #define | TIM_DCR_DBL_2 ((uint32_t)0x00000400) |
| #define | TIM_DCR_DBL_3 ((uint32_t)0x00000800) |
| #define | TIM_DCR_DBL_4 ((uint32_t)0x00001000) |
| #define | TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) |
| #define | RTC_CRH_SECIE ((uint32_t)0x00000001) |
| #define | RTC_CRH_ALRIE ((uint32_t)0x00000002) |
| #define | RTC_CRH_OWIE ((uint32_t)0x00000004) |
| #define | RTC_CRL_SECF ((uint32_t)0x00000001) |
| #define | RTC_CRL_ALRF ((uint32_t)0x00000002) |
| #define | RTC_CRL_OWF ((uint32_t)0x00000004) |
| #define | RTC_CRL_RSF ((uint32_t)0x00000008) |
| #define | RTC_CRL_CNF ((uint32_t)0x00000010) |
| #define | RTC_CRL_RTOFF ((uint32_t)0x00000020) |
| #define | RTC_PRLH_PRL ((uint32_t)0x0000000F) |
| #define | RTC_PRLL_PRL ((uint32_t)0x0000FFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) |
| #define | RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | IWDG_KR_KEY ((uint32_t)0x0000FFFF) |
| #define | IWDG_PR_PR ((uint32_t)0x00000007) |
| #define | IWDG_PR_PR_0 ((uint32_t)0x00000001) |
| #define | IWDG_PR_PR_1 ((uint32_t)0x00000002) |
| #define | IWDG_PR_PR_2 ((uint32_t)0x00000004) |
| #define | IWDG_RLR_RL ((uint32_t)0x00000FFF) |
| #define | IWDG_SR_PVU ((uint32_t)0x00000001) |
| #define | IWDG_SR_RVU ((uint32_t)0x00000002) |
| #define | WWDG_CR_T ((uint32_t)0x0000007F) |
| #define | WWDG_CR_T0 ((uint32_t)0x00000001) |
| #define | WWDG_CR_T1 ((uint32_t)0x00000002) |
| #define | WWDG_CR_T2 ((uint32_t)0x00000004) |
| #define | WWDG_CR_T3 ((uint32_t)0x00000008) |
| #define | WWDG_CR_T4 ((uint32_t)0x00000010) |
| #define | WWDG_CR_T5 ((uint32_t)0x00000020) |
| #define | WWDG_CR_T6 ((uint32_t)0x00000040) |
| #define | WWDG_CR_WDGA ((uint32_t)0x00000080) |
| #define | WWDG_CFR_W ((uint32_t)0x0000007F) |
| #define | WWDG_CFR_W0 ((uint32_t)0x00000001) |
| #define | WWDG_CFR_W1 ((uint32_t)0x00000002) |
| #define | WWDG_CFR_W2 ((uint32_t)0x00000004) |
| #define | WWDG_CFR_W3 ((uint32_t)0x00000008) |
| #define | WWDG_CFR_W4 ((uint32_t)0x00000010) |
| #define | WWDG_CFR_W5 ((uint32_t)0x00000020) |
| #define | WWDG_CFR_W6 ((uint32_t)0x00000040) |
| #define | WWDG_CFR_WDGTB ((uint32_t)0x00000180) |
| #define | WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) |
| #define | WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) |
| #define | WWDG_CFR_EWI ((uint32_t)0x00000200) |
| #define | WWDG_SR_EWIF ((uint32_t)0x00000001) |
| #define | SDIO_POWER_PWRCTRL ((uint32_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint32_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint32_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint32_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint32_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint32_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint32_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint32_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint32_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint32_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint32_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint32_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint32_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint32_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint32_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint32_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | USB_EP0R USB_BASE |
| #define | USB_EP1R (USB_BASE + 0x00000004) |
| #define | USB_EP2R (USB_BASE + 0x00000008) |
| #define | USB_EP3R (USB_BASE + 0x0000000C) |
| #define | USB_EP4R (USB_BASE + 0x00000010) |
| #define | USB_EP5R (USB_BASE + 0x00000014) |
| #define | USB_EP6R (USB_BASE + 0x00000018) |
| #define | USB_EP7R (USB_BASE + 0x0000001C) |
| #define | USB_EP_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EPRX_STAT ((uint32_t)0x00003000) |
| #define | USB_EP_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP_T_FIELD ((uint32_t)0x00000600) |
| #define | USB_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EPTX_STAT ((uint32_t)0x00000030) |
| #define | USB_EPADDR_FIELD ((uint32_t)0x0000000F) |
| #define | USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) |
| #define | USB_EP_TYPE_MASK ((uint32_t)0x00000600) |
| #define | USB_EP_BULK ((uint32_t)0x00000000) |
| #define | USB_EP_CONTROL ((uint32_t)0x00000200) |
| #define | USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) |
| #define | USB_EP_INTERRUPT ((uint32_t)0x00000600) |
| #define | USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) |
| #define | USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) |
| #define | USB_EP_TX_DIS ((uint32_t)0x00000000) |
| #define | USB_EP_TX_STALL ((uint32_t)0x00000010) |
| #define | USB_EP_TX_NAK ((uint32_t)0x00000020) |
| #define | USB_EP_TX_VALID ((uint32_t)0x00000030) |
| #define | USB_EPTX_DTOG1 ((uint32_t)0x00000010) |
| #define | USB_EPTX_DTOG2 ((uint32_t)0x00000020) |
| #define | USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) |
| #define | USB_EP_RX_DIS ((uint32_t)0x00000000) |
| #define | USB_EP_RX_STALL ((uint32_t)0x00001000) |
| #define | USB_EP_RX_NAK ((uint32_t)0x00002000) |
| #define | USB_EP_RX_VALID ((uint32_t)0x00003000) |
| #define | USB_EPRX_DTOG1 ((uint32_t)0x00001000) |
| #define | USB_EPRX_DTOG2 ((uint32_t)0x00002000) |
| #define | USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) |
| #define | USB_EP0R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP0R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP0R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP0R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP0R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP0R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP0R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP0R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP0R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP0R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP1R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP1R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP1R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP1R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP1R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP1R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP1R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP1R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP1R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP1R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP2R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP2R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP2R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP2R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP2R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP2R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP2R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP2R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP2R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP2R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP3R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP3R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP3R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP3R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP3R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP3R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP3R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP3R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP3R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP3R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP4R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP4R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP4R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP4R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP4R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP4R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP4R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP4R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP4R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP4R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP5R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP5R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP5R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP5R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP5R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP5R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP5R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP5R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP5R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP5R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP6R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP6R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP6R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP6R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP6R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP6R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP6R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP6R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP6R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP6R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP7R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP7R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP7R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP7R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP7R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP7R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP7R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP7R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP7R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP7R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_CNTR_FRES ((uint32_t)0x00000001) |
| #define | USB_CNTR_PDWN ((uint32_t)0x00000002) |
| #define | USB_CNTR_LP_MODE ((uint32_t)0x00000004) |
| #define | USB_CNTR_FSUSP ((uint32_t)0x00000008) |
| #define | USB_CNTR_RESUME ((uint32_t)0x00000010) |
| #define | USB_CNTR_ESOFM ((uint32_t)0x00000100) |
| #define | USB_CNTR_SOFM ((uint32_t)0x00000200) |
| #define | USB_CNTR_RESETM ((uint32_t)0x00000400) |
| #define | USB_CNTR_SUSPM ((uint32_t)0x00000800) |
| #define | USB_CNTR_WKUPM ((uint32_t)0x00001000) |
| #define | USB_CNTR_ERRM ((uint32_t)0x00002000) |
| #define | USB_CNTR_PMAOVRM ((uint32_t)0x00004000) |
| #define | USB_CNTR_CTRM ((uint32_t)0x00008000) |
| #define | USB_ISTR_EP_ID ((uint32_t)0x0000000F) |
| #define | USB_ISTR_DIR ((uint32_t)0x00000010) |
| #define | USB_ISTR_ESOF ((uint32_t)0x00000100) |
| #define | USB_ISTR_SOF ((uint32_t)0x00000200) |
| #define | USB_ISTR_RESET ((uint32_t)0x00000400) |
| #define | USB_ISTR_SUSP ((uint32_t)0x00000800) |
| #define | USB_ISTR_WKUP ((uint32_t)0x00001000) |
| #define | USB_ISTR_ERR ((uint32_t)0x00002000) |
| #define | USB_ISTR_PMAOVR ((uint32_t)0x00004000) |
| #define | USB_ISTR_CTR ((uint32_t)0x00008000) |
| #define | USB_FNR_FN ((uint32_t)0x000007FF) |
| #define | USB_FNR_LSOF ((uint32_t)0x00001800) |
| #define | USB_FNR_LCK ((uint32_t)0x00002000) |
| #define | USB_FNR_RXDM ((uint32_t)0x00004000) |
| #define | USB_FNR_RXDP ((uint32_t)0x00008000) |
| #define | USB_DADDR_ADD ((uint32_t)0x0000007F) |
| #define | USB_DADDR_ADD0 ((uint32_t)0x00000001) |
| #define | USB_DADDR_ADD1 ((uint32_t)0x00000002) |
| #define | USB_DADDR_ADD2 ((uint32_t)0x00000004) |
| #define | USB_DADDR_ADD3 ((uint32_t)0x00000008) |
| #define | USB_DADDR_ADD4 ((uint32_t)0x00000010) |
| #define | USB_DADDR_ADD5 ((uint32_t)0x00000020) |
| #define | USB_DADDR_ADD6 ((uint32_t)0x00000040) |
| #define | USB_DADDR_EF ((uint32_t)0x00000080) |
| #define | USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) |
| #define | USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) |
| #define | USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) |
| #define | USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | CAN_MCR_INRQ ((uint32_t)0x00000001) |
| #define | CAN_MCR_SLEEP ((uint32_t)0x00000002) |
| #define | CAN_MCR_TXFP ((uint32_t)0x00000004) |
| #define | CAN_MCR_RFLM ((uint32_t)0x00000008) |
| #define | CAN_MCR_NART ((uint32_t)0x00000010) |
| #define | CAN_MCR_AWUM ((uint32_t)0x00000020) |
| #define | CAN_MCR_ABOM ((uint32_t)0x00000040) |
| #define | CAN_MCR_TTCM ((uint32_t)0x00000080) |
| #define | CAN_MCR_RESET ((uint32_t)0x00008000) |
| #define | CAN_MCR_DBF ((uint32_t)0x00010000) |
| #define | CAN_MSR_INAK ((uint32_t)0x00000001) |
| #define | CAN_MSR_SLAK ((uint32_t)0x00000002) |
| #define | CAN_MSR_ERRI ((uint32_t)0x00000004) |
| #define | CAN_MSR_WKUI ((uint32_t)0x00000008) |
| #define | CAN_MSR_SLAKI ((uint32_t)0x00000010) |
| #define | CAN_MSR_TXM ((uint32_t)0x00000100) |
| #define | CAN_MSR_RXM ((uint32_t)0x00000200) |
| #define | CAN_MSR_SAMP ((uint32_t)0x00000400) |
| #define | CAN_MSR_RX ((uint32_t)0x00000800) |
| #define | CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
| #define | CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
| #define | CAN_TSR_ALST0 ((uint32_t)0x00000004) |
| #define | CAN_TSR_TERR0 ((uint32_t)0x00000008) |
| #define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
| #define | CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
| #define | CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
| #define | CAN_TSR_ALST1 ((uint32_t)0x00000400) |
| #define | CAN_TSR_TERR1 ((uint32_t)0x00000800) |
| #define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
| #define | CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
| #define | CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
| #define | CAN_TSR_ALST2 ((uint32_t)0x00040000) |
| #define | CAN_TSR_TERR2 ((uint32_t)0x00080000) |
| #define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
| #define | CAN_TSR_CODE ((uint32_t)0x03000000) |
| #define | CAN_TSR_TME ((uint32_t)0x1C000000) |
| #define | CAN_TSR_TME0 ((uint32_t)0x04000000) |
| #define | CAN_TSR_TME1 ((uint32_t)0x08000000) |
| #define | CAN_TSR_TME2 ((uint32_t)0x10000000) |
| #define | CAN_TSR_LOW ((uint32_t)0xE0000000) |
| #define | CAN_TSR_LOW0 ((uint32_t)0x20000000) |
| #define | CAN_TSR_LOW1 ((uint32_t)0x40000000) |
| #define | CAN_TSR_LOW2 ((uint32_t)0x80000000) |
| #define | CAN_RF0R_FMP0 ((uint32_t)0x00000003) |
| #define | CAN_RF0R_FULL0 ((uint32_t)0x00000008) |
| #define | CAN_RF0R_FOVR0 ((uint32_t)0x00000010) |
| #define | CAN_RF0R_RFOM0 ((uint32_t)0x00000020) |
| #define | CAN_RF1R_FMP1 ((uint32_t)0x00000003) |
| #define | CAN_RF1R_FULL1 ((uint32_t)0x00000008) |
| #define | CAN_RF1R_FOVR1 ((uint32_t)0x00000010) |
| #define | CAN_RF1R_RFOM1 ((uint32_t)0x00000020) |
| #define | CAN_IER_TMEIE ((uint32_t)0x00000001) |
| #define | CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
| #define | CAN_IER_FFIE0 ((uint32_t)0x00000004) |
| #define | CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
| #define | CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
| #define | CAN_IER_FFIE1 ((uint32_t)0x00000020) |
| #define | CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
| #define | CAN_IER_EWGIE ((uint32_t)0x00000100) |
| #define | CAN_IER_EPVIE ((uint32_t)0x00000200) |
| #define | CAN_IER_BOFIE ((uint32_t)0x00000400) |
| #define | CAN_IER_LECIE ((uint32_t)0x00000800) |
| #define | CAN_IER_ERRIE ((uint32_t)0x00008000) |
| #define | CAN_IER_WKUIE ((uint32_t)0x00010000) |
| #define | CAN_IER_SLKIE ((uint32_t)0x00020000) |
| #define | CAN_ESR_EWGF ((uint32_t)0x00000001) |
| #define | CAN_ESR_EPVF ((uint32_t)0x00000002) |
| #define | CAN_ESR_BOFF ((uint32_t)0x00000004) |
| #define | CAN_ESR_LEC ((uint32_t)0x00000070) |
| #define | CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
| #define | CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
| #define | CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
| #define | CAN_ESR_TEC ((uint32_t)0x00FF0000) |
| #define | CAN_ESR_REC ((uint32_t)0xFF000000) |
| #define | CAN_BTR_BRP ((uint32_t)0x000003FF) |
| #define | CAN_BTR_TS1 ((uint32_t)0x000F0000) |
| #define | CAN_BTR_TS1_0 ((uint32_t)0x00010000) |
| #define | CAN_BTR_TS1_1 ((uint32_t)0x00020000) |
| #define | CAN_BTR_TS1_2 ((uint32_t)0x00040000) |
| #define | CAN_BTR_TS1_3 ((uint32_t)0x00080000) |
| #define | CAN_BTR_TS2 ((uint32_t)0x00700000) |
| #define | CAN_BTR_TS2_0 ((uint32_t)0x00100000) |
| #define | CAN_BTR_TS2_1 ((uint32_t)0x00200000) |
| #define | CAN_BTR_TS2_2 ((uint32_t)0x00400000) |
| #define | CAN_BTR_SJW ((uint32_t)0x03000000) |
| #define | CAN_BTR_SJW_0 ((uint32_t)0x01000000) |
| #define | CAN_BTR_SJW_1 ((uint32_t)0x02000000) |
| #define | CAN_BTR_LBKM ((uint32_t)0x40000000) |
| #define | CAN_BTR_SILM ((uint32_t)0x80000000) |
| #define | CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT0R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT1R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI2R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI2R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI2R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT2R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_FMR_FINIT ((uint32_t)0x00000001) |
| #define | CAN_FMR_CAN2SB ((uint32_t)0x00003F00) |
| #define | CAN_FM1R_FBM ((uint32_t)0x00003FFF) |
| #define | CAN_FM1R_FBM0 ((uint32_t)0x00000001) |
| #define | CAN_FM1R_FBM1 ((uint32_t)0x00000002) |
| #define | CAN_FM1R_FBM2 ((uint32_t)0x00000004) |
| #define | CAN_FM1R_FBM3 ((uint32_t)0x00000008) |
| #define | CAN_FM1R_FBM4 ((uint32_t)0x00000010) |
| #define | CAN_FM1R_FBM5 ((uint32_t)0x00000020) |
| #define | CAN_FM1R_FBM6 ((uint32_t)0x00000040) |
| #define | CAN_FM1R_FBM7 ((uint32_t)0x00000080) |
| #define | CAN_FM1R_FBM8 ((uint32_t)0x00000100) |
| #define | CAN_FM1R_FBM9 ((uint32_t)0x00000200) |
| #define | CAN_FM1R_FBM10 ((uint32_t)0x00000400) |
| #define | CAN_FM1R_FBM11 ((uint32_t)0x00000800) |
| #define | CAN_FM1R_FBM12 ((uint32_t)0x00001000) |
| #define | CAN_FM1R_FBM13 ((uint32_t)0x00002000) |
| #define | CAN_FS1R_FSC ((uint32_t)0x00003FFF) |
| #define | CAN_FS1R_FSC0 ((uint32_t)0x00000001) |
| #define | CAN_FS1R_FSC1 ((uint32_t)0x00000002) |
| #define | CAN_FS1R_FSC2 ((uint32_t)0x00000004) |
| #define | CAN_FS1R_FSC3 ((uint32_t)0x00000008) |
| #define | CAN_FS1R_FSC4 ((uint32_t)0x00000010) |
| #define | CAN_FS1R_FSC5 ((uint32_t)0x00000020) |
| #define | CAN_FS1R_FSC6 ((uint32_t)0x00000040) |
| #define | CAN_FS1R_FSC7 ((uint32_t)0x00000080) |
| #define | CAN_FS1R_FSC8 ((uint32_t)0x00000100) |
| #define | CAN_FS1R_FSC9 ((uint32_t)0x00000200) |
| #define | CAN_FS1R_FSC10 ((uint32_t)0x00000400) |
| #define | CAN_FS1R_FSC11 ((uint32_t)0x00000800) |
| #define | CAN_FS1R_FSC12 ((uint32_t)0x00001000) |
| #define | CAN_FS1R_FSC13 ((uint32_t)0x00002000) |
| #define | CAN_FFA1R_FFA ((uint32_t)0x00003FFF) |
| #define | CAN_FFA1R_FFA0 ((uint32_t)0x00000001) |
| #define | CAN_FFA1R_FFA1 ((uint32_t)0x00000002) |
| #define | CAN_FFA1R_FFA2 ((uint32_t)0x00000004) |
| #define | CAN_FFA1R_FFA3 ((uint32_t)0x00000008) |
| #define | CAN_FFA1R_FFA4 ((uint32_t)0x00000010) |
| #define | CAN_FFA1R_FFA5 ((uint32_t)0x00000020) |
| #define | CAN_FFA1R_FFA6 ((uint32_t)0x00000040) |
| #define | CAN_FFA1R_FFA7 ((uint32_t)0x00000080) |
| #define | CAN_FFA1R_FFA8 ((uint32_t)0x00000100) |
| #define | CAN_FFA1R_FFA9 ((uint32_t)0x00000200) |
| #define | CAN_FFA1R_FFA10 ((uint32_t)0x00000400) |
| #define | CAN_FFA1R_FFA11 ((uint32_t)0x00000800) |
| #define | CAN_FFA1R_FFA12 ((uint32_t)0x00001000) |
| #define | CAN_FFA1R_FFA13 ((uint32_t)0x00002000) |
| #define | CAN_FA1R_FACT ((uint32_t)0x00003FFF) |
| #define | CAN_FA1R_FACT0 ((uint32_t)0x00000001) |
| #define | CAN_FA1R_FACT1 ((uint32_t)0x00000002) |
| #define | CAN_FA1R_FACT2 ((uint32_t)0x00000004) |
| #define | CAN_FA1R_FACT3 ((uint32_t)0x00000008) |
| #define | CAN_FA1R_FACT4 ((uint32_t)0x00000010) |
| #define | CAN_FA1R_FACT5 ((uint32_t)0x00000020) |
| #define | CAN_FA1R_FACT6 ((uint32_t)0x00000040) |
| #define | CAN_FA1R_FACT7 ((uint32_t)0x00000080) |
| #define | CAN_FA1R_FACT8 ((uint32_t)0x00000100) |
| #define | CAN_FA1R_FACT9 ((uint32_t)0x00000200) |
| #define | CAN_FA1R_FACT10 ((uint32_t)0x00000400) |
| #define | CAN_FA1R_FACT11 ((uint32_t)0x00000800) |
| #define | CAN_FA1R_FACT12 ((uint32_t)0x00001000) |
| #define | CAN_FA1R_FACT13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F0R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R2_FB31 ((uint32_t)0x80000000) |
| #define | SPI_CR1_CPHA ((uint32_t)0x00000001) |
| #define | SPI_CR1_CPOL ((uint32_t)0x00000002) |
| #define | SPI_CR1_MSTR ((uint32_t)0x00000004) |
| #define | SPI_CR1_BR ((uint32_t)0x00000038) |
| #define | SPI_CR1_BR_0 ((uint32_t)0x00000008) |
| #define | SPI_CR1_BR_1 ((uint32_t)0x00000010) |
| #define | SPI_CR1_BR_2 ((uint32_t)0x00000020) |
| #define | SPI_CR1_SPE ((uint32_t)0x00000040) |
| #define | SPI_CR1_LSBFIRST ((uint32_t)0x00000080) |
| #define | SPI_CR1_SSI ((uint32_t)0x00000100) |
| #define | SPI_CR1_SSM ((uint32_t)0x00000200) |
| #define | SPI_CR1_RXONLY ((uint32_t)0x00000400) |
| #define | SPI_CR1_DFF ((uint32_t)0x00000800) |
| #define | SPI_CR1_CRCNEXT ((uint32_t)0x00001000) |
| #define | SPI_CR1_CRCEN ((uint32_t)0x00002000) |
| #define | SPI_CR1_BIDIOE ((uint32_t)0x00004000) |
| #define | SPI_CR1_BIDIMODE ((uint32_t)0x00008000) |
| #define | SPI_CR2_RXDMAEN ((uint32_t)0x00000001) |
| #define | SPI_CR2_TXDMAEN ((uint32_t)0x00000002) |
| #define | SPI_CR2_SSOE ((uint32_t)0x00000004) |
| #define | SPI_CR2_ERRIE ((uint32_t)0x00000020) |
| #define | SPI_CR2_RXNEIE ((uint32_t)0x00000040) |
| #define | SPI_CR2_TXEIE ((uint32_t)0x00000080) |
| #define | SPI_SR_RXNE ((uint32_t)0x00000001) |
| #define | SPI_SR_TXE ((uint32_t)0x00000002) |
| #define | SPI_SR_CHSIDE ((uint32_t)0x00000004) |
| #define | SPI_SR_UDR ((uint32_t)0x00000008) |
| #define | SPI_SR_CRCERR ((uint32_t)0x00000010) |
| #define | SPI_SR_MODF ((uint32_t)0x00000020) |
| #define | SPI_SR_OVR ((uint32_t)0x00000040) |
| #define | SPI_SR_BSY ((uint32_t)0x00000080) |
| #define | SPI_DR_DR ((uint32_t)0x0000FFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_SMBUS ((uint32_t)0x00000002) |
| #define | I2C_CR1_SMBTYPE ((uint32_t)0x00000008) |
| #define | I2C_CR1_ENARP ((uint32_t)0x00000010) |
| #define | I2C_CR1_ENPEC ((uint32_t)0x00000020) |
| #define | I2C_CR1_ENGC ((uint32_t)0x00000040) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) |
| #define | I2C_CR1_START ((uint32_t)0x00000100) |
| #define | I2C_CR1_STOP ((uint32_t)0x00000200) |
| #define | I2C_CR1_ACK ((uint32_t)0x00000400) |
| #define | I2C_CR1_POS ((uint32_t)0x00000800) |
| #define | I2C_CR1_PEC ((uint32_t)0x00001000) |
| #define | I2C_CR1_ALERT ((uint32_t)0x00002000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00008000) |
| #define | I2C_CR2_FREQ ((uint32_t)0x0000003F) |
| #define | I2C_CR2_FREQ_0 ((uint32_t)0x00000001) |
| #define | I2C_CR2_FREQ_1 ((uint32_t)0x00000002) |
| #define | I2C_CR2_FREQ_2 ((uint32_t)0x00000004) |
| #define | I2C_CR2_FREQ_3 ((uint32_t)0x00000008) |
| #define | I2C_CR2_FREQ_4 ((uint32_t)0x00000010) |
| #define | I2C_CR2_FREQ_5 ((uint32_t)0x00000020) |
| #define | I2C_CR2_ITERREN ((uint32_t)0x00000100) |
| #define | I2C_CR2_ITEVTEN ((uint32_t)0x00000200) |
| #define | I2C_CR2_ITBUFEN ((uint32_t)0x00000400) |
| #define | I2C_CR2_DMAEN ((uint32_t)0x00000800) |
| #define | I2C_CR2_LAST ((uint32_t)0x00001000) |
| #define | I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) |
| #define | I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) |
| #define | I2C_OAR1_ADD0 ((uint32_t)0x00000001) |
| #define | I2C_OAR1_ADD1 ((uint32_t)0x00000002) |
| #define | I2C_OAR1_ADD2 ((uint32_t)0x00000004) |
| #define | I2C_OAR1_ADD3 ((uint32_t)0x00000008) |
| #define | I2C_OAR1_ADD4 ((uint32_t)0x00000010) |
| #define | I2C_OAR1_ADD5 ((uint32_t)0x00000020) |
| #define | I2C_OAR1_ADD6 ((uint32_t)0x00000040) |
| #define | I2C_OAR1_ADD7 ((uint32_t)0x00000080) |
| #define | I2C_OAR1_ADD8 ((uint32_t)0x00000100) |
| #define | I2C_OAR1_ADD9 ((uint32_t)0x00000200) |
| #define | I2C_OAR1_ADDMODE ((uint32_t)0x00008000) |
| #define | I2C_OAR2_ENDUAL ((uint32_t)0x00000001) |
| #define | I2C_OAR2_ADD2 ((uint32_t)0x000000FE) |
| #define | I2C_SR1_SB ((uint32_t)0x00000001) |
| #define | I2C_SR1_ADDR ((uint32_t)0x00000002) |
| #define | I2C_SR1_BTF ((uint32_t)0x00000004) |
| #define | I2C_SR1_ADD10 ((uint32_t)0x00000008) |
| #define | I2C_SR1_STOPF ((uint32_t)0x00000010) |
| #define | I2C_SR1_RXNE ((uint32_t)0x00000040) |
| #define | I2C_SR1_TXE ((uint32_t)0x00000080) |
| #define | I2C_SR1_BERR ((uint32_t)0x00000100) |
| #define | I2C_SR1_ARLO ((uint32_t)0x00000200) |
| #define | I2C_SR1_AF ((uint32_t)0x00000400) |
| #define | I2C_SR1_OVR ((uint32_t)0x00000800) |
| #define | I2C_SR1_PECERR ((uint32_t)0x00001000) |
| #define | I2C_SR1_TIMEOUT ((uint32_t)0x00004000) |
| #define | I2C_SR1_SMBALERT ((uint32_t)0x00008000) |
| #define | I2C_SR2_MSL ((uint32_t)0x00000001) |
| #define | I2C_SR2_BUSY ((uint32_t)0x00000002) |
| #define | I2C_SR2_TRA ((uint32_t)0x00000004) |
| #define | I2C_SR2_GENCALL ((uint32_t)0x00000010) |
| #define | I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) |
| #define | I2C_SR2_SMBHOST ((uint32_t)0x00000040) |
| #define | I2C_SR2_DUALF ((uint32_t)0x00000080) |
| #define | I2C_SR2_PEC ((uint32_t)0x0000FF00) |
| #define | I2C_CCR_CCR ((uint32_t)0x00000FFF) |
| #define | I2C_CCR_DUTY ((uint32_t)0x00004000) |
| #define | I2C_CCR_FS ((uint32_t)0x00008000) |
| #define | I2C_TRISE_TRISE ((uint32_t)0x0000003F) |
| #define | USART_SR_PE ((uint32_t)0x00000001) |
| #define | USART_SR_FE ((uint32_t)0x00000002) |
| #define | USART_SR_NE ((uint32_t)0x00000004) |
| #define | USART_SR_ORE ((uint32_t)0x00000008) |
| #define | USART_SR_IDLE ((uint32_t)0x00000010) |
| #define | USART_SR_RXNE ((uint32_t)0x00000020) |
| #define | USART_SR_TC ((uint32_t)0x00000040) |
| #define | USART_SR_TXE ((uint32_t)0x00000080) |
| #define | USART_SR_LBD ((uint32_t)0x00000100) |
| #define | USART_SR_CTS ((uint32_t)0x00000200) |
| #define | USART_DR_DR ((uint32_t)0x000001FF) |
| #define | USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) |
| #define | USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) |
| #define | USART_CR1_SBK ((uint32_t)0x00000001) |
| #define | USART_CR1_RWU ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_UE ((uint32_t)0x00002000) |
| #define | USART_CR2_ADD ((uint32_t)0x0000000F) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_GTPR_PSC ((uint32_t)0x000000FF) |
| #define | USART_GTPR_PSC_0 ((uint32_t)0x00000001) |
| #define | USART_GTPR_PSC_1 ((uint32_t)0x00000002) |
| #define | USART_GTPR_PSC_2 ((uint32_t)0x00000004) |
| #define | USART_GTPR_PSC_3 ((uint32_t)0x00000008) |
| #define | USART_GTPR_PSC_4 ((uint32_t)0x00000010) |
| #define | USART_GTPR_PSC_5 ((uint32_t)0x00000020) |
| #define | USART_GTPR_PSC_6 ((uint32_t)0x00000040) |
| #define | USART_GTPR_PSC_7 ((uint32_t)0x00000080) |
| #define | USART_GTPR_GT ((uint32_t)0x0000FF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) |
| #define | DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) |
| #define | FLASH_ACR_HLFCYA ((uint32_t)0x00000008) |
| #define | FLASH_ACR_PRFTBE ((uint32_t)0x00000010) |
| #define | FLASH_ACR_PRFTBS ((uint32_t)0x00000020) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint32_t)0x000000A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT ((uint32_t)0x00000002) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) |
| #define | FLASH_OBR_USER ((uint32_t)0x0000001C) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) |
| #define | FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) |
| #define | FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) |
| #define | FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint32_t)0x000000FF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V2 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_2V3 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_2V4 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2V5 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_2V6 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | BKP_DR1_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR2_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR3_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR4_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR5_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR6_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR7_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR8_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR9_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR10_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR11_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR12_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR13_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR14_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR15_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR16_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR17_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR18_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR19_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR20_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR21_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR22_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR23_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR24_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR25_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR26_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR27_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR28_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR29_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR30_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR31_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR32_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR33_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR34_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR35_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR36_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR37_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR38_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR39_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR40_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR41_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR42_D ((uint32_t)0x0000FFFF) |
| #define | RTC_BKP_NUMBER 42 |
| #define | BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
| #define | BKP_RTCCR_CCO ((uint32_t)0x00000080) |
| #define | BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
| #define | BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
| #define | BKP_CR_TPE ((uint32_t)0x00000001) |
| #define | BKP_CR_TPAL ((uint32_t)0x00000002) |
| #define | BKP_CSR_CTE ((uint32_t)0x00000001) |
| #define | BKP_CSR_CTI ((uint32_t)0x00000002) |
| #define | BKP_CSR_TPIE ((uint32_t)0x00000004) |
| #define | BKP_CSR_TEF ((uint32_t)0x00000100) |
| #define | BKP_CSR_TIF ((uint32_t)0x00000200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_USBPRE ((uint32_t)0x00400000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) |
| #define | RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) |
| #define | RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) |
| #define | RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) |
| #define | RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) |
| #define | RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
| #define | RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) |
| #define | RCC_AHBENR_FSMCEN ((uint32_t)0x00000100) |
| #define | RCC_AHBENR_SDIOEN ((uint32_t)0x00000400) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) |
| #define | RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) |
| #define | RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) |
| #define | RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) |
| #define | RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_USBEN ((uint32_t)0x00800000) |
| #define | RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
| #define | RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint32_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint32_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint32_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint32_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint32_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint32_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint32_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint32_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint32_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint32_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint32_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint32_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint32_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint32_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint32_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint32_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint32_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint32_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint32_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint32_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint32_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint32_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint32_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint32_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint32_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint32_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint32_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint32_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint32_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint32_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint32_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint32_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint32_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint32_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint32_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint32_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint32_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint32_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint32_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint32_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint32_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint32_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint32_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint32_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint32_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint32_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint32_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint32_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
| #define | AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
| #define | AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
| #define | AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
| #define | AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
| #define | AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PORT ((uint32_t)0x00000070) |
| #define | AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
| #define | AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
| #define | AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
| #define | AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) |
| #define | AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) |
| #define | AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
| #define | AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) |
| #define | AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) |
| #define | AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) |
| #define | AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
| #define | AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) |
| #define | SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) |
| #define | SCB_SCR_SEVONPEND ((uint32_t)0x00000010) |
| #define | SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) |
| #define | SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) |
| #define | SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) |
| #define | SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) |
| #define | SCB_CCR_STKALIGN ((uint32_t)0x00000200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint32_t)0x00000001) |
| #define | SCB_DFSR_BKPT ((uint32_t)0x00000002) |
| #define | SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) |
| #define | SCB_DFSR_VCATCH ((uint32_t)0x00000008) |
| #define | SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
| #define | ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
| #define | ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
| #define | ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
| #define | ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) |
| #define | DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) |
| #define | DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) |
| #define | TIM_CR1_CEN ((uint32_t)0x00000001) |
| #define | TIM_CR1_UDIS ((uint32_t)0x00000002) |
| #define | TIM_CR1_URS ((uint32_t)0x00000004) |
| #define | TIM_CR1_OPM ((uint32_t)0x00000008) |
| #define | TIM_CR1_DIR ((uint32_t)0x00000010) |
| #define | TIM_CR1_CMS ((uint32_t)0x00000060) |
| #define | TIM_CR1_CMS_0 ((uint32_t)0x00000020) |
| #define | TIM_CR1_CMS_1 ((uint32_t)0x00000040) |
| #define | TIM_CR1_ARPE ((uint32_t)0x00000080) |
| #define | TIM_CR1_CKD ((uint32_t)0x00000300) |
| #define | TIM_CR1_CKD_0 ((uint32_t)0x00000100) |
| #define | TIM_CR1_CKD_1 ((uint32_t)0x00000200) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00000007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint32_t)0x00000001) |
| #define | TIM_DIER_CC1IE ((uint32_t)0x00000002) |
| #define | TIM_DIER_CC2IE ((uint32_t)0x00000004) |
| #define | TIM_DIER_CC3IE ((uint32_t)0x00000008) |
| #define | TIM_DIER_CC4IE ((uint32_t)0x00000010) |
| #define | TIM_DIER_COMIE ((uint32_t)0x00000020) |
| #define | TIM_DIER_TIE ((uint32_t)0x00000040) |
| #define | TIM_DIER_BIE ((uint32_t)0x00000080) |
| #define | TIM_DIER_UDE ((uint32_t)0x00000100) |
| #define | TIM_DIER_CC1DE ((uint32_t)0x00000200) |
| #define | TIM_DIER_CC2DE ((uint32_t)0x00000400) |
| #define | TIM_DIER_CC3DE ((uint32_t)0x00000800) |
| #define | TIM_DIER_CC4DE ((uint32_t)0x00001000) |
| #define | TIM_DIER_COMDE ((uint32_t)0x00002000) |
| #define | TIM_DIER_TDE ((uint32_t)0x00004000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_EGR_UG ((uint32_t)0x00000001) |
| #define | TIM_EGR_CC1G ((uint32_t)0x00000002) |
| #define | TIM_EGR_CC2G ((uint32_t)0x00000004) |
| #define | TIM_EGR_CC3G ((uint32_t)0x00000008) |
| #define | TIM_EGR_CC4G ((uint32_t)0x00000010) |
| #define | TIM_EGR_COMG ((uint32_t)0x00000020) |
| #define | TIM_EGR_TG ((uint32_t)0x00000040) |
| #define | TIM_EGR_BG ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00000070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x00007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_PSC_PSC ((uint32_t)0x0000FFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint32_t)0x000000FF) |
| #define | TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_DCR_DBA ((uint32_t)0x0000001F) |
| #define | TIM_DCR_DBA_0 ((uint32_t)0x00000001) |
| #define | TIM_DCR_DBA_1 ((uint32_t)0x00000002) |
| #define | TIM_DCR_DBA_2 ((uint32_t)0x00000004) |
| #define | TIM_DCR_DBA_3 ((uint32_t)0x00000008) |
| #define | TIM_DCR_DBA_4 ((uint32_t)0x00000010) |
| #define | TIM_DCR_DBL ((uint32_t)0x00001F00) |
| #define | TIM_DCR_DBL_0 ((uint32_t)0x00000100) |
| #define | TIM_DCR_DBL_1 ((uint32_t)0x00000200) |
| #define | TIM_DCR_DBL_2 ((uint32_t)0x00000400) |
| #define | TIM_DCR_DBL_3 ((uint32_t)0x00000800) |
| #define | TIM_DCR_DBL_4 ((uint32_t)0x00001000) |
| #define | TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) |
| #define | RTC_CRH_SECIE ((uint32_t)0x00000001) |
| #define | RTC_CRH_ALRIE ((uint32_t)0x00000002) |
| #define | RTC_CRH_OWIE ((uint32_t)0x00000004) |
| #define | RTC_CRL_SECF ((uint32_t)0x00000001) |
| #define | RTC_CRL_ALRF ((uint32_t)0x00000002) |
| #define | RTC_CRL_OWF ((uint32_t)0x00000004) |
| #define | RTC_CRL_RSF ((uint32_t)0x00000008) |
| #define | RTC_CRL_CNF ((uint32_t)0x00000010) |
| #define | RTC_CRL_RTOFF ((uint32_t)0x00000020) |
| #define | RTC_PRLH_PRL ((uint32_t)0x0000000F) |
| #define | RTC_PRLL_PRL ((uint32_t)0x0000FFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) |
| #define | RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | IWDG_KR_KEY ((uint32_t)0x0000FFFF) |
| #define | IWDG_PR_PR ((uint32_t)0x00000007) |
| #define | IWDG_PR_PR_0 ((uint32_t)0x00000001) |
| #define | IWDG_PR_PR_1 ((uint32_t)0x00000002) |
| #define | IWDG_PR_PR_2 ((uint32_t)0x00000004) |
| #define | IWDG_RLR_RL ((uint32_t)0x00000FFF) |
| #define | IWDG_SR_PVU ((uint32_t)0x00000001) |
| #define | IWDG_SR_RVU ((uint32_t)0x00000002) |
| #define | WWDG_CR_T ((uint32_t)0x0000007F) |
| #define | WWDG_CR_T0 ((uint32_t)0x00000001) |
| #define | WWDG_CR_T1 ((uint32_t)0x00000002) |
| #define | WWDG_CR_T2 ((uint32_t)0x00000004) |
| #define | WWDG_CR_T3 ((uint32_t)0x00000008) |
| #define | WWDG_CR_T4 ((uint32_t)0x00000010) |
| #define | WWDG_CR_T5 ((uint32_t)0x00000020) |
| #define | WWDG_CR_T6 ((uint32_t)0x00000040) |
| #define | WWDG_CR_WDGA ((uint32_t)0x00000080) |
| #define | WWDG_CFR_W ((uint32_t)0x0000007F) |
| #define | WWDG_CFR_W0 ((uint32_t)0x00000001) |
| #define | WWDG_CFR_W1 ((uint32_t)0x00000002) |
| #define | WWDG_CFR_W2 ((uint32_t)0x00000004) |
| #define | WWDG_CFR_W3 ((uint32_t)0x00000008) |
| #define | WWDG_CFR_W4 ((uint32_t)0x00000010) |
| #define | WWDG_CFR_W5 ((uint32_t)0x00000020) |
| #define | WWDG_CFR_W6 ((uint32_t)0x00000040) |
| #define | WWDG_CFR_WDGTB ((uint32_t)0x00000180) |
| #define | WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) |
| #define | WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) |
| #define | WWDG_CFR_EWI ((uint32_t)0x00000200) |
| #define | WWDG_SR_EWIF ((uint32_t)0x00000001) |
| #define | FSMC_BCRx_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCRx_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCRx_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCRx_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCRx_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCRx_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCRx_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCRx_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCRx_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCRx_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCRx_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCRx_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCRx_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCRx_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCRx_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCRx_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCRx_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BTRx_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTRx_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTRx_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTRx_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTRx_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTRx_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTRx_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTRx_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTRx_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTRx_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTRx_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTRx_DATAST_4 ((uint32_t)0x00001000) |
| #define | FSMC_BTRx_DATAST_5 ((uint32_t)0x00002000) |
| #define | FSMC_BTRx_DATAST_6 ((uint32_t)0x00004000) |
| #define | FSMC_BTRx_DATAST_7 ((uint32_t)0x00008000) |
| #define | FSMC_BTRx_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTRx_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTRx_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTRx_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTRx_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTRx_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTRx_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTRx_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTRx_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTRx_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTRx_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTRx_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTRx_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTRx_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTRx_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTRx_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTRx_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTRx_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTRx_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTRx_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTRx_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTRx_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTRx_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTRx_DATAST_4 ((uint32_t)0x00001000) |
| #define | FSMC_BWTRx_DATAST_5 ((uint32_t)0x00002000) |
| #define | FSMC_BWTRx_DATAST_6 ((uint32_t)0x00004000) |
| #define | FSMC_BWTRx_DATAST_7 ((uint32_t)0x00008000) |
| #define | FSMC_BWTRx_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BWTRx_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BWTRx_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BWTRx_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BWTRx_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BWTRx_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTRx_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTRx_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_PCRx_PWAITEN ((uint32_t)0x00000002) |
| #define | FSMC_PCRx_PBKEN ((uint32_t)0x00000004) |
| #define | FSMC_PCRx_PTYP ((uint32_t)0x00000008) |
| #define | FSMC_PCRx_PWID ((uint32_t)0x00000030) |
| #define | FSMC_PCRx_PWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_PCRx_PWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_PCRx_ECCEN ((uint32_t)0x00000040) |
| #define | FSMC_PCRx_TCLR ((uint32_t)0x00001E00) |
| #define | FSMC_PCRx_TCLR_0 ((uint32_t)0x00000200) |
| #define | FSMC_PCRx_TCLR_1 ((uint32_t)0x00000400) |
| #define | FSMC_PCRx_TCLR_2 ((uint32_t)0x00000800) |
| #define | FSMC_PCRx_TCLR_3 ((uint32_t)0x00001000) |
| #define | FSMC_PCRx_TAR ((uint32_t)0x0001E000) |
| #define | FSMC_PCRx_TAR_0 ((uint32_t)0x00002000) |
| #define | FSMC_PCRx_TAR_1 ((uint32_t)0x00004000) |
| #define | FSMC_PCRx_TAR_2 ((uint32_t)0x00008000) |
| #define | FSMC_PCRx_TAR_3 ((uint32_t)0x00010000) |
| #define | FSMC_PCRx_ECCPS ((uint32_t)0x000E0000) |
| #define | FSMC_PCRx_ECCPS_0 ((uint32_t)0x00020000) |
| #define | FSMC_PCRx_ECCPS_1 ((uint32_t)0x00040000) |
| #define | FSMC_PCRx_ECCPS_2 ((uint32_t)0x00080000) |
| #define | FSMC_SRx_IRS ((uint32_t)0x00000001) |
| #define | FSMC_SRx_ILS ((uint32_t)0x00000002) |
| #define | FSMC_SRx_IFS ((uint32_t)0x00000004) |
| #define | FSMC_SRx_IREN ((uint32_t)0x00000008) |
| #define | FSMC_SRx_ILEN ((uint32_t)0x00000010) |
| #define | FSMC_SRx_IFEN ((uint32_t)0x00000020) |
| #define | FSMC_SRx_FEMPT ((uint32_t)0x00000040) |
| #define | FSMC_PMEMx_MEMSETx ((uint32_t)0x000000FF) |
| #define | FSMC_PMEMx_MEMSETx_0 ((uint32_t)0x00000001) |
| #define | FSMC_PMEMx_MEMSETx_1 ((uint32_t)0x00000002) |
| #define | FSMC_PMEMx_MEMSETx_2 ((uint32_t)0x00000004) |
| #define | FSMC_PMEMx_MEMSETx_3 ((uint32_t)0x00000008) |
| #define | FSMC_PMEMx_MEMSETx_4 ((uint32_t)0x00000010) |
| #define | FSMC_PMEMx_MEMSETx_5 ((uint32_t)0x00000020) |
| #define | FSMC_PMEMx_MEMSETx_6 ((uint32_t)0x00000040) |
| #define | FSMC_PMEMx_MEMSETx_7 ((uint32_t)0x00000080) |
| #define | FSMC_PMEMx_MEMWAITx ((uint32_t)0x0000FF00) |
| #define | FSMC_PMEMx_MEMWAIT2_0 ((uint32_t)0x00000100) |
| #define | FSMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) |
| #define | FSMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) |
| #define | FSMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) |
| #define | FSMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) |
| #define | FSMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) |
| #define | FSMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) |
| #define | FSMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) |
| #define | FSMC_PMEMx_MEMHOLDx ((uint32_t)0x00FF0000) |
| #define | FSMC_PMEMx_MEMHOLDx_0 ((uint32_t)0x00010000) |
| #define | FSMC_PMEMx_MEMHOLDx_1 ((uint32_t)0x00020000) |
| #define | FSMC_PMEMx_MEMHOLDx_2 ((uint32_t)0x00040000) |
| #define | FSMC_PMEMx_MEMHOLDx_3 ((uint32_t)0x00080000) |
| #define | FSMC_PMEMx_MEMHOLDx_4 ((uint32_t)0x00100000) |
| #define | FSMC_PMEMx_MEMHOLDx_5 ((uint32_t)0x00200000) |
| #define | FSMC_PMEMx_MEMHOLDx_6 ((uint32_t)0x00400000) |
| #define | FSMC_PMEMx_MEMHOLDx_7 ((uint32_t)0x00800000) |
| #define | FSMC_PMEMx_MEMHIZx ((uint32_t)0xFF000000) |
| #define | FSMC_PMEMx_MEMHIZx_0 ((uint32_t)0x01000000) |
| #define | FSMC_PMEMx_MEMHIZx_1 ((uint32_t)0x02000000) |
| #define | FSMC_PMEMx_MEMHIZx_2 ((uint32_t)0x04000000) |
| #define | FSMC_PMEMx_MEMHIZx_3 ((uint32_t)0x08000000) |
| #define | FSMC_PMEMx_MEMHIZx_4 ((uint32_t)0x10000000) |
| #define | FSMC_PMEMx_MEMHIZx_5 ((uint32_t)0x20000000) |
| #define | FSMC_PMEMx_MEMHIZx_6 ((uint32_t)0x40000000) |
| #define | FSMC_PMEMx_MEMHIZx_7 ((uint32_t)0x80000000) |
| #define | FSMC_PATTx_ATTSETx ((uint32_t)0x000000FF) |
| #define | FSMC_PATTx_ATTSETx_0 ((uint32_t)0x00000001) |
| #define | FSMC_PATTx_ATTSETx_1 ((uint32_t)0x00000002) |
| #define | FSMC_PATTx_ATTSETx_2 ((uint32_t)0x00000004) |
| #define | FSMC_PATTx_ATTSETx_3 ((uint32_t)0x00000008) |
| #define | FSMC_PATTx_ATTSETx_4 ((uint32_t)0x00000010) |
| #define | FSMC_PATTx_ATTSETx_5 ((uint32_t)0x00000020) |
| #define | FSMC_PATTx_ATTSETx_6 ((uint32_t)0x00000040) |
| #define | FSMC_PATTx_ATTSETx_7 ((uint32_t)0x00000080) |
| #define | FSMC_PATTx_ATTWAITx ((uint32_t)0x0000FF00) |
| #define | FSMC_PATTx_ATTWAITx_0 ((uint32_t)0x00000100) |
| #define | FSMC_PATTx_ATTWAITx_1 ((uint32_t)0x00000200) |
| #define | FSMC_PATTx_ATTWAITx_2 ((uint32_t)0x00000400) |
| #define | FSMC_PATTx_ATTWAITx_3 ((uint32_t)0x00000800) |
| #define | FSMC_PATTx_ATTWAITx_4 ((uint32_t)0x00001000) |
| #define | FSMC_PATTx_ATTWAITx_5 ((uint32_t)0x00002000) |
| #define | FSMC_PATTx_ATTWAITx_6 ((uint32_t)0x00004000) |
| #define | FSMC_PATTx_ATTWAITx_7 ((uint32_t)0x00008000) |
| #define | FSMC_PATTx_ATTHOLDx ((uint32_t)0x00FF0000) |
| #define | FSMC_PATTx_ATTHOLDx_0 ((uint32_t)0x00010000) |
| #define | FSMC_PATTx_ATTHOLDx_1 ((uint32_t)0x00020000) |
| #define | FSMC_PATTx_ATTHOLDx_2 ((uint32_t)0x00040000) |
| #define | FSMC_PATTx_ATTHOLDx_3 ((uint32_t)0x00080000) |
| #define | FSMC_PATTx_ATTHOLDx_4 ((uint32_t)0x00100000) |
| #define | FSMC_PATTx_ATTHOLDx_5 ((uint32_t)0x00200000) |
| #define | FSMC_PATTx_ATTHOLDx_6 ((uint32_t)0x00400000) |
| #define | FSMC_PATTx_ATTHOLDx_7 ((uint32_t)0x00800000) |
| #define | FSMC_PATTx_ATTHIZx ((uint32_t)0xFF000000) |
| #define | FSMC_PATTx_ATTHIZx_0 ((uint32_t)0x01000000) |
| #define | FSMC_PATTx_ATTHIZx_1 ((uint32_t)0x02000000) |
| #define | FSMC_PATTx_ATTHIZx_2 ((uint32_t)0x04000000) |
| #define | FSMC_PATTx_ATTHIZx_3 ((uint32_t)0x08000000) |
| #define | FSMC_PATTx_ATTHIZx_4 ((uint32_t)0x10000000) |
| #define | FSMC_PATTx_ATTHIZx_5 ((uint32_t)0x20000000) |
| #define | FSMC_PATTx_ATTHIZx_6 ((uint32_t)0x40000000) |
| #define | FSMC_PATTx_ATTHIZx_7 ((uint32_t)0x80000000) |
| #define | FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) |
| #define | FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) |
| #define | FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) |
| #define | FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) |
| #define | FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) |
| #define | FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) |
| #define | FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) |
| #define | FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) |
| #define | FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) |
| #define | FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) |
| #define | FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) |
| #define | FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) |
| #define | FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) |
| #define | FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) |
| #define | FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) |
| #define | FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) |
| #define | FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) |
| #define | FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) |
| #define | FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) |
| #define | FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) |
| #define | FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) |
| #define | FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) |
| #define | FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) |
| #define | FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) |
| #define | FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) |
| #define | FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) |
| #define | FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) |
| #define | FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) |
| #define | FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) |
| #define | FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) |
| #define | FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) |
| #define | FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) |
| #define | FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) |
| #define | FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) |
| #define | FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) |
| #define | FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) |
| #define | FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) |
| #define | FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_POWER_PWRCTRL ((uint32_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint32_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint32_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint32_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint32_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint32_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint32_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint32_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint32_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint32_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint32_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint32_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint32_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint32_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint32_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint32_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | USB_EP0R USB_BASE |
| #define | USB_EP1R (USB_BASE + 0x00000004) |
| #define | USB_EP2R (USB_BASE + 0x00000008) |
| #define | USB_EP3R (USB_BASE + 0x0000000C) |
| #define | USB_EP4R (USB_BASE + 0x00000010) |
| #define | USB_EP5R (USB_BASE + 0x00000014) |
| #define | USB_EP6R (USB_BASE + 0x00000018) |
| #define | USB_EP7R (USB_BASE + 0x0000001C) |
| #define | USB_EP_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EPRX_STAT ((uint32_t)0x00003000) |
| #define | USB_EP_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP_T_FIELD ((uint32_t)0x00000600) |
| #define | USB_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EPTX_STAT ((uint32_t)0x00000030) |
| #define | USB_EPADDR_FIELD ((uint32_t)0x0000000F) |
| #define | USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) |
| #define | USB_EP_TYPE_MASK ((uint32_t)0x00000600) |
| #define | USB_EP_BULK ((uint32_t)0x00000000) |
| #define | USB_EP_CONTROL ((uint32_t)0x00000200) |
| #define | USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) |
| #define | USB_EP_INTERRUPT ((uint32_t)0x00000600) |
| #define | USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) |
| #define | USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) |
| #define | USB_EP_TX_DIS ((uint32_t)0x00000000) |
| #define | USB_EP_TX_STALL ((uint32_t)0x00000010) |
| #define | USB_EP_TX_NAK ((uint32_t)0x00000020) |
| #define | USB_EP_TX_VALID ((uint32_t)0x00000030) |
| #define | USB_EPTX_DTOG1 ((uint32_t)0x00000010) |
| #define | USB_EPTX_DTOG2 ((uint32_t)0x00000020) |
| #define | USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) |
| #define | USB_EP_RX_DIS ((uint32_t)0x00000000) |
| #define | USB_EP_RX_STALL ((uint32_t)0x00001000) |
| #define | USB_EP_RX_NAK ((uint32_t)0x00002000) |
| #define | USB_EP_RX_VALID ((uint32_t)0x00003000) |
| #define | USB_EPRX_DTOG1 ((uint32_t)0x00001000) |
| #define | USB_EPRX_DTOG2 ((uint32_t)0x00002000) |
| #define | USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) |
| #define | USB_EP0R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP0R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP0R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP0R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP0R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP0R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP0R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP0R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP0R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP0R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP1R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP1R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP1R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP1R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP1R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP1R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP1R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP1R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP1R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP1R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP2R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP2R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP2R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP2R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP2R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP2R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP2R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP2R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP2R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP2R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP3R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP3R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP3R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP3R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP3R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP3R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP3R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP3R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP3R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP3R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP4R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP4R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP4R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP4R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP4R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP4R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP4R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP4R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP4R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP4R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP5R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP5R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP5R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP5R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP5R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP5R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP5R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP5R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP5R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP5R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP6R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP6R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP6R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP6R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP6R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP6R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP6R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP6R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP6R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP6R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP7R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP7R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP7R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP7R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP7R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP7R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP7R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP7R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP7R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP7R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_CNTR_FRES ((uint32_t)0x00000001) |
| #define | USB_CNTR_PDWN ((uint32_t)0x00000002) |
| #define | USB_CNTR_LP_MODE ((uint32_t)0x00000004) |
| #define | USB_CNTR_FSUSP ((uint32_t)0x00000008) |
| #define | USB_CNTR_RESUME ((uint32_t)0x00000010) |
| #define | USB_CNTR_ESOFM ((uint32_t)0x00000100) |
| #define | USB_CNTR_SOFM ((uint32_t)0x00000200) |
| #define | USB_CNTR_RESETM ((uint32_t)0x00000400) |
| #define | USB_CNTR_SUSPM ((uint32_t)0x00000800) |
| #define | USB_CNTR_WKUPM ((uint32_t)0x00001000) |
| #define | USB_CNTR_ERRM ((uint32_t)0x00002000) |
| #define | USB_CNTR_PMAOVRM ((uint32_t)0x00004000) |
| #define | USB_CNTR_CTRM ((uint32_t)0x00008000) |
| #define | USB_ISTR_EP_ID ((uint32_t)0x0000000F) |
| #define | USB_ISTR_DIR ((uint32_t)0x00000010) |
| #define | USB_ISTR_ESOF ((uint32_t)0x00000100) |
| #define | USB_ISTR_SOF ((uint32_t)0x00000200) |
| #define | USB_ISTR_RESET ((uint32_t)0x00000400) |
| #define | USB_ISTR_SUSP ((uint32_t)0x00000800) |
| #define | USB_ISTR_WKUP ((uint32_t)0x00001000) |
| #define | USB_ISTR_ERR ((uint32_t)0x00002000) |
| #define | USB_ISTR_PMAOVR ((uint32_t)0x00004000) |
| #define | USB_ISTR_CTR ((uint32_t)0x00008000) |
| #define | USB_FNR_FN ((uint32_t)0x000007FF) |
| #define | USB_FNR_LSOF ((uint32_t)0x00001800) |
| #define | USB_FNR_LCK ((uint32_t)0x00002000) |
| #define | USB_FNR_RXDM ((uint32_t)0x00004000) |
| #define | USB_FNR_RXDP ((uint32_t)0x00008000) |
| #define | USB_DADDR_ADD ((uint32_t)0x0000007F) |
| #define | USB_DADDR_ADD0 ((uint32_t)0x00000001) |
| #define | USB_DADDR_ADD1 ((uint32_t)0x00000002) |
| #define | USB_DADDR_ADD2 ((uint32_t)0x00000004) |
| #define | USB_DADDR_ADD3 ((uint32_t)0x00000008) |
| #define | USB_DADDR_ADD4 ((uint32_t)0x00000010) |
| #define | USB_DADDR_ADD5 ((uint32_t)0x00000020) |
| #define | USB_DADDR_ADD6 ((uint32_t)0x00000040) |
| #define | USB_DADDR_EF ((uint32_t)0x00000080) |
| #define | USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) |
| #define | USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) |
| #define | USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) |
| #define | USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | CAN_MCR_INRQ ((uint32_t)0x00000001) |
| #define | CAN_MCR_SLEEP ((uint32_t)0x00000002) |
| #define | CAN_MCR_TXFP ((uint32_t)0x00000004) |
| #define | CAN_MCR_RFLM ((uint32_t)0x00000008) |
| #define | CAN_MCR_NART ((uint32_t)0x00000010) |
| #define | CAN_MCR_AWUM ((uint32_t)0x00000020) |
| #define | CAN_MCR_ABOM ((uint32_t)0x00000040) |
| #define | CAN_MCR_TTCM ((uint32_t)0x00000080) |
| #define | CAN_MCR_RESET ((uint32_t)0x00008000) |
| #define | CAN_MCR_DBF ((uint32_t)0x00010000) |
| #define | CAN_MSR_INAK ((uint32_t)0x00000001) |
| #define | CAN_MSR_SLAK ((uint32_t)0x00000002) |
| #define | CAN_MSR_ERRI ((uint32_t)0x00000004) |
| #define | CAN_MSR_WKUI ((uint32_t)0x00000008) |
| #define | CAN_MSR_SLAKI ((uint32_t)0x00000010) |
| #define | CAN_MSR_TXM ((uint32_t)0x00000100) |
| #define | CAN_MSR_RXM ((uint32_t)0x00000200) |
| #define | CAN_MSR_SAMP ((uint32_t)0x00000400) |
| #define | CAN_MSR_RX ((uint32_t)0x00000800) |
| #define | CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
| #define | CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
| #define | CAN_TSR_ALST0 ((uint32_t)0x00000004) |
| #define | CAN_TSR_TERR0 ((uint32_t)0x00000008) |
| #define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
| #define | CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
| #define | CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
| #define | CAN_TSR_ALST1 ((uint32_t)0x00000400) |
| #define | CAN_TSR_TERR1 ((uint32_t)0x00000800) |
| #define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
| #define | CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
| #define | CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
| #define | CAN_TSR_ALST2 ((uint32_t)0x00040000) |
| #define | CAN_TSR_TERR2 ((uint32_t)0x00080000) |
| #define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
| #define | CAN_TSR_CODE ((uint32_t)0x03000000) |
| #define | CAN_TSR_TME ((uint32_t)0x1C000000) |
| #define | CAN_TSR_TME0 ((uint32_t)0x04000000) |
| #define | CAN_TSR_TME1 ((uint32_t)0x08000000) |
| #define | CAN_TSR_TME2 ((uint32_t)0x10000000) |
| #define | CAN_TSR_LOW ((uint32_t)0xE0000000) |
| #define | CAN_TSR_LOW0 ((uint32_t)0x20000000) |
| #define | CAN_TSR_LOW1 ((uint32_t)0x40000000) |
| #define | CAN_TSR_LOW2 ((uint32_t)0x80000000) |
| #define | CAN_RF0R_FMP0 ((uint32_t)0x00000003) |
| #define | CAN_RF0R_FULL0 ((uint32_t)0x00000008) |
| #define | CAN_RF0R_FOVR0 ((uint32_t)0x00000010) |
| #define | CAN_RF0R_RFOM0 ((uint32_t)0x00000020) |
| #define | CAN_RF1R_FMP1 ((uint32_t)0x00000003) |
| #define | CAN_RF1R_FULL1 ((uint32_t)0x00000008) |
| #define | CAN_RF1R_FOVR1 ((uint32_t)0x00000010) |
| #define | CAN_RF1R_RFOM1 ((uint32_t)0x00000020) |
| #define | CAN_IER_TMEIE ((uint32_t)0x00000001) |
| #define | CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
| #define | CAN_IER_FFIE0 ((uint32_t)0x00000004) |
| #define | CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
| #define | CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
| #define | CAN_IER_FFIE1 ((uint32_t)0x00000020) |
| #define | CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
| #define | CAN_IER_EWGIE ((uint32_t)0x00000100) |
| #define | CAN_IER_EPVIE ((uint32_t)0x00000200) |
| #define | CAN_IER_BOFIE ((uint32_t)0x00000400) |
| #define | CAN_IER_LECIE ((uint32_t)0x00000800) |
| #define | CAN_IER_ERRIE ((uint32_t)0x00008000) |
| #define | CAN_IER_WKUIE ((uint32_t)0x00010000) |
| #define | CAN_IER_SLKIE ((uint32_t)0x00020000) |
| #define | CAN_ESR_EWGF ((uint32_t)0x00000001) |
| #define | CAN_ESR_EPVF ((uint32_t)0x00000002) |
| #define | CAN_ESR_BOFF ((uint32_t)0x00000004) |
| #define | CAN_ESR_LEC ((uint32_t)0x00000070) |
| #define | CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
| #define | CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
| #define | CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
| #define | CAN_ESR_TEC ((uint32_t)0x00FF0000) |
| #define | CAN_ESR_REC ((uint32_t)0xFF000000) |
| #define | CAN_BTR_BRP ((uint32_t)0x000003FF) |
| #define | CAN_BTR_TS1 ((uint32_t)0x000F0000) |
| #define | CAN_BTR_TS1_0 ((uint32_t)0x00010000) |
| #define | CAN_BTR_TS1_1 ((uint32_t)0x00020000) |
| #define | CAN_BTR_TS1_2 ((uint32_t)0x00040000) |
| #define | CAN_BTR_TS1_3 ((uint32_t)0x00080000) |
| #define | CAN_BTR_TS2 ((uint32_t)0x00700000) |
| #define | CAN_BTR_TS2_0 ((uint32_t)0x00100000) |
| #define | CAN_BTR_TS2_1 ((uint32_t)0x00200000) |
| #define | CAN_BTR_TS2_2 ((uint32_t)0x00400000) |
| #define | CAN_BTR_SJW ((uint32_t)0x03000000) |
| #define | CAN_BTR_SJW_0 ((uint32_t)0x01000000) |
| #define | CAN_BTR_SJW_1 ((uint32_t)0x02000000) |
| #define | CAN_BTR_LBKM ((uint32_t)0x40000000) |
| #define | CAN_BTR_SILM ((uint32_t)0x80000000) |
| #define | CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT0R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT1R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI2R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI2R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI2R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT2R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_FMR_FINIT ((uint32_t)0x00000001) |
| #define | CAN_FMR_CAN2SB ((uint32_t)0x00003F00) |
| #define | CAN_FM1R_FBM ((uint32_t)0x00003FFF) |
| #define | CAN_FM1R_FBM0 ((uint32_t)0x00000001) |
| #define | CAN_FM1R_FBM1 ((uint32_t)0x00000002) |
| #define | CAN_FM1R_FBM2 ((uint32_t)0x00000004) |
| #define | CAN_FM1R_FBM3 ((uint32_t)0x00000008) |
| #define | CAN_FM1R_FBM4 ((uint32_t)0x00000010) |
| #define | CAN_FM1R_FBM5 ((uint32_t)0x00000020) |
| #define | CAN_FM1R_FBM6 ((uint32_t)0x00000040) |
| #define | CAN_FM1R_FBM7 ((uint32_t)0x00000080) |
| #define | CAN_FM1R_FBM8 ((uint32_t)0x00000100) |
| #define | CAN_FM1R_FBM9 ((uint32_t)0x00000200) |
| #define | CAN_FM1R_FBM10 ((uint32_t)0x00000400) |
| #define | CAN_FM1R_FBM11 ((uint32_t)0x00000800) |
| #define | CAN_FM1R_FBM12 ((uint32_t)0x00001000) |
| #define | CAN_FM1R_FBM13 ((uint32_t)0x00002000) |
| #define | CAN_FS1R_FSC ((uint32_t)0x00003FFF) |
| #define | CAN_FS1R_FSC0 ((uint32_t)0x00000001) |
| #define | CAN_FS1R_FSC1 ((uint32_t)0x00000002) |
| #define | CAN_FS1R_FSC2 ((uint32_t)0x00000004) |
| #define | CAN_FS1R_FSC3 ((uint32_t)0x00000008) |
| #define | CAN_FS1R_FSC4 ((uint32_t)0x00000010) |
| #define | CAN_FS1R_FSC5 ((uint32_t)0x00000020) |
| #define | CAN_FS1R_FSC6 ((uint32_t)0x00000040) |
| #define | CAN_FS1R_FSC7 ((uint32_t)0x00000080) |
| #define | CAN_FS1R_FSC8 ((uint32_t)0x00000100) |
| #define | CAN_FS1R_FSC9 ((uint32_t)0x00000200) |
| #define | CAN_FS1R_FSC10 ((uint32_t)0x00000400) |
| #define | CAN_FS1R_FSC11 ((uint32_t)0x00000800) |
| #define | CAN_FS1R_FSC12 ((uint32_t)0x00001000) |
| #define | CAN_FS1R_FSC13 ((uint32_t)0x00002000) |
| #define | CAN_FFA1R_FFA ((uint32_t)0x00003FFF) |
| #define | CAN_FFA1R_FFA0 ((uint32_t)0x00000001) |
| #define | CAN_FFA1R_FFA1 ((uint32_t)0x00000002) |
| #define | CAN_FFA1R_FFA2 ((uint32_t)0x00000004) |
| #define | CAN_FFA1R_FFA3 ((uint32_t)0x00000008) |
| #define | CAN_FFA1R_FFA4 ((uint32_t)0x00000010) |
| #define | CAN_FFA1R_FFA5 ((uint32_t)0x00000020) |
| #define | CAN_FFA1R_FFA6 ((uint32_t)0x00000040) |
| #define | CAN_FFA1R_FFA7 ((uint32_t)0x00000080) |
| #define | CAN_FFA1R_FFA8 ((uint32_t)0x00000100) |
| #define | CAN_FFA1R_FFA9 ((uint32_t)0x00000200) |
| #define | CAN_FFA1R_FFA10 ((uint32_t)0x00000400) |
| #define | CAN_FFA1R_FFA11 ((uint32_t)0x00000800) |
| #define | CAN_FFA1R_FFA12 ((uint32_t)0x00001000) |
| #define | CAN_FFA1R_FFA13 ((uint32_t)0x00002000) |
| #define | CAN_FA1R_FACT ((uint32_t)0x00003FFF) |
| #define | CAN_FA1R_FACT0 ((uint32_t)0x00000001) |
| #define | CAN_FA1R_FACT1 ((uint32_t)0x00000002) |
| #define | CAN_FA1R_FACT2 ((uint32_t)0x00000004) |
| #define | CAN_FA1R_FACT3 ((uint32_t)0x00000008) |
| #define | CAN_FA1R_FACT4 ((uint32_t)0x00000010) |
| #define | CAN_FA1R_FACT5 ((uint32_t)0x00000020) |
| #define | CAN_FA1R_FACT6 ((uint32_t)0x00000040) |
| #define | CAN_FA1R_FACT7 ((uint32_t)0x00000080) |
| #define | CAN_FA1R_FACT8 ((uint32_t)0x00000100) |
| #define | CAN_FA1R_FACT9 ((uint32_t)0x00000200) |
| #define | CAN_FA1R_FACT10 ((uint32_t)0x00000400) |
| #define | CAN_FA1R_FACT11 ((uint32_t)0x00000800) |
| #define | CAN_FA1R_FACT12 ((uint32_t)0x00001000) |
| #define | CAN_FA1R_FACT13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F0R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R2_FB31 ((uint32_t)0x80000000) |
| #define | SPI_CR1_CPHA ((uint32_t)0x00000001) |
| #define | SPI_CR1_CPOL ((uint32_t)0x00000002) |
| #define | SPI_CR1_MSTR ((uint32_t)0x00000004) |
| #define | SPI_CR1_BR ((uint32_t)0x00000038) |
| #define | SPI_CR1_BR_0 ((uint32_t)0x00000008) |
| #define | SPI_CR1_BR_1 ((uint32_t)0x00000010) |
| #define | SPI_CR1_BR_2 ((uint32_t)0x00000020) |
| #define | SPI_CR1_SPE ((uint32_t)0x00000040) |
| #define | SPI_CR1_LSBFIRST ((uint32_t)0x00000080) |
| #define | SPI_CR1_SSI ((uint32_t)0x00000100) |
| #define | SPI_CR1_SSM ((uint32_t)0x00000200) |
| #define | SPI_CR1_RXONLY ((uint32_t)0x00000400) |
| #define | SPI_CR1_DFF ((uint32_t)0x00000800) |
| #define | SPI_CR1_CRCNEXT ((uint32_t)0x00001000) |
| #define | SPI_CR1_CRCEN ((uint32_t)0x00002000) |
| #define | SPI_CR1_BIDIOE ((uint32_t)0x00004000) |
| #define | SPI_CR1_BIDIMODE ((uint32_t)0x00008000) |
| #define | SPI_CR2_RXDMAEN ((uint32_t)0x00000001) |
| #define | SPI_CR2_TXDMAEN ((uint32_t)0x00000002) |
| #define | SPI_CR2_SSOE ((uint32_t)0x00000004) |
| #define | SPI_CR2_ERRIE ((uint32_t)0x00000020) |
| #define | SPI_CR2_RXNEIE ((uint32_t)0x00000040) |
| #define | SPI_CR2_TXEIE ((uint32_t)0x00000080) |
| #define | SPI_SR_RXNE ((uint32_t)0x00000001) |
| #define | SPI_SR_TXE ((uint32_t)0x00000002) |
| #define | SPI_SR_CHSIDE ((uint32_t)0x00000004) |
| #define | SPI_SR_UDR ((uint32_t)0x00000008) |
| #define | SPI_SR_CRCERR ((uint32_t)0x00000010) |
| #define | SPI_SR_MODF ((uint32_t)0x00000020) |
| #define | SPI_SR_OVR ((uint32_t)0x00000040) |
| #define | SPI_SR_BSY ((uint32_t)0x00000080) |
| #define | SPI_DR_DR ((uint32_t)0x0000FFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) |
| #define | SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) |
| #define | SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) |
| #define | SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) |
| #define | SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) |
| #define | SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) |
| #define | SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) |
| #define | SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) |
| #define | SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) |
| #define | SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) |
| #define | SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) |
| #define | SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) |
| #define | SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) |
| #define | SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) |
| #define | SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) |
| #define | SPI_I2SPR_ODD ((uint32_t)0x00000100) |
| #define | SPI_I2SPR_MCKOE ((uint32_t)0x00000200) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_SMBUS ((uint32_t)0x00000002) |
| #define | I2C_CR1_SMBTYPE ((uint32_t)0x00000008) |
| #define | I2C_CR1_ENARP ((uint32_t)0x00000010) |
| #define | I2C_CR1_ENPEC ((uint32_t)0x00000020) |
| #define | I2C_CR1_ENGC ((uint32_t)0x00000040) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) |
| #define | I2C_CR1_START ((uint32_t)0x00000100) |
| #define | I2C_CR1_STOP ((uint32_t)0x00000200) |
| #define | I2C_CR1_ACK ((uint32_t)0x00000400) |
| #define | I2C_CR1_POS ((uint32_t)0x00000800) |
| #define | I2C_CR1_PEC ((uint32_t)0x00001000) |
| #define | I2C_CR1_ALERT ((uint32_t)0x00002000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00008000) |
| #define | I2C_CR2_FREQ ((uint32_t)0x0000003F) |
| #define | I2C_CR2_FREQ_0 ((uint32_t)0x00000001) |
| #define | I2C_CR2_FREQ_1 ((uint32_t)0x00000002) |
| #define | I2C_CR2_FREQ_2 ((uint32_t)0x00000004) |
| #define | I2C_CR2_FREQ_3 ((uint32_t)0x00000008) |
| #define | I2C_CR2_FREQ_4 ((uint32_t)0x00000010) |
| #define | I2C_CR2_FREQ_5 ((uint32_t)0x00000020) |
| #define | I2C_CR2_ITERREN ((uint32_t)0x00000100) |
| #define | I2C_CR2_ITEVTEN ((uint32_t)0x00000200) |
| #define | I2C_CR2_ITBUFEN ((uint32_t)0x00000400) |
| #define | I2C_CR2_DMAEN ((uint32_t)0x00000800) |
| #define | I2C_CR2_LAST ((uint32_t)0x00001000) |
| #define | I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) |
| #define | I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) |
| #define | I2C_OAR1_ADD0 ((uint32_t)0x00000001) |
| #define | I2C_OAR1_ADD1 ((uint32_t)0x00000002) |
| #define | I2C_OAR1_ADD2 ((uint32_t)0x00000004) |
| #define | I2C_OAR1_ADD3 ((uint32_t)0x00000008) |
| #define | I2C_OAR1_ADD4 ((uint32_t)0x00000010) |
| #define | I2C_OAR1_ADD5 ((uint32_t)0x00000020) |
| #define | I2C_OAR1_ADD6 ((uint32_t)0x00000040) |
| #define | I2C_OAR1_ADD7 ((uint32_t)0x00000080) |
| #define | I2C_OAR1_ADD8 ((uint32_t)0x00000100) |
| #define | I2C_OAR1_ADD9 ((uint32_t)0x00000200) |
| #define | I2C_OAR1_ADDMODE ((uint32_t)0x00008000) |
| #define | I2C_OAR2_ENDUAL ((uint32_t)0x00000001) |
| #define | I2C_OAR2_ADD2 ((uint32_t)0x000000FE) |
| #define | I2C_SR1_SB ((uint32_t)0x00000001) |
| #define | I2C_SR1_ADDR ((uint32_t)0x00000002) |
| #define | I2C_SR1_BTF ((uint32_t)0x00000004) |
| #define | I2C_SR1_ADD10 ((uint32_t)0x00000008) |
| #define | I2C_SR1_STOPF ((uint32_t)0x00000010) |
| #define | I2C_SR1_RXNE ((uint32_t)0x00000040) |
| #define | I2C_SR1_TXE ((uint32_t)0x00000080) |
| #define | I2C_SR1_BERR ((uint32_t)0x00000100) |
| #define | I2C_SR1_ARLO ((uint32_t)0x00000200) |
| #define | I2C_SR1_AF ((uint32_t)0x00000400) |
| #define | I2C_SR1_OVR ((uint32_t)0x00000800) |
| #define | I2C_SR1_PECERR ((uint32_t)0x00001000) |
| #define | I2C_SR1_TIMEOUT ((uint32_t)0x00004000) |
| #define | I2C_SR1_SMBALERT ((uint32_t)0x00008000) |
| #define | I2C_SR2_MSL ((uint32_t)0x00000001) |
| #define | I2C_SR2_BUSY ((uint32_t)0x00000002) |
| #define | I2C_SR2_TRA ((uint32_t)0x00000004) |
| #define | I2C_SR2_GENCALL ((uint32_t)0x00000010) |
| #define | I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) |
| #define | I2C_SR2_SMBHOST ((uint32_t)0x00000040) |
| #define | I2C_SR2_DUALF ((uint32_t)0x00000080) |
| #define | I2C_SR2_PEC ((uint32_t)0x0000FF00) |
| #define | I2C_CCR_CCR ((uint32_t)0x00000FFF) |
| #define | I2C_CCR_DUTY ((uint32_t)0x00004000) |
| #define | I2C_CCR_FS ((uint32_t)0x00008000) |
| #define | I2C_TRISE_TRISE ((uint32_t)0x0000003F) |
| #define | USART_SR_PE ((uint32_t)0x00000001) |
| #define | USART_SR_FE ((uint32_t)0x00000002) |
| #define | USART_SR_NE ((uint32_t)0x00000004) |
| #define | USART_SR_ORE ((uint32_t)0x00000008) |
| #define | USART_SR_IDLE ((uint32_t)0x00000010) |
| #define | USART_SR_RXNE ((uint32_t)0x00000020) |
| #define | USART_SR_TC ((uint32_t)0x00000040) |
| #define | USART_SR_TXE ((uint32_t)0x00000080) |
| #define | USART_SR_LBD ((uint32_t)0x00000100) |
| #define | USART_SR_CTS ((uint32_t)0x00000200) |
| #define | USART_DR_DR ((uint32_t)0x000001FF) |
| #define | USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) |
| #define | USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) |
| #define | USART_CR1_SBK ((uint32_t)0x00000001) |
| #define | USART_CR1_RWU ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_UE ((uint32_t)0x00002000) |
| #define | USART_CR2_ADD ((uint32_t)0x0000000F) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_GTPR_PSC ((uint32_t)0x000000FF) |
| #define | USART_GTPR_PSC_0 ((uint32_t)0x00000001) |
| #define | USART_GTPR_PSC_1 ((uint32_t)0x00000002) |
| #define | USART_GTPR_PSC_2 ((uint32_t)0x00000004) |
| #define | USART_GTPR_PSC_3 ((uint32_t)0x00000008) |
| #define | USART_GTPR_PSC_4 ((uint32_t)0x00000010) |
| #define | USART_GTPR_PSC_5 ((uint32_t)0x00000020) |
| #define | USART_GTPR_PSC_6 ((uint32_t)0x00000040) |
| #define | USART_GTPR_PSC_7 ((uint32_t)0x00000080) |
| #define | USART_GTPR_GT ((uint32_t)0x0000FF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) |
| #define | DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) |
| #define | DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) |
| #define | DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) |
| #define | DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) |
| #define | DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) |
| #define | FLASH_ACR_HLFCYA ((uint32_t)0x00000008) |
| #define | FLASH_ACR_PRFTBE ((uint32_t)0x00000010) |
| #define | FLASH_ACR_PRFTBS ((uint32_t)0x00000020) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint32_t)0x000000A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT ((uint32_t)0x00000002) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) |
| #define | FLASH_OBR_USER ((uint32_t)0x0000001C) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) |
| #define | FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) |
| #define | FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) |
| #define | FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint32_t)0x000000FF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V2 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_2V3 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_2V4 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2V5 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_2V6 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | BKP_DR1_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR2_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR3_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR4_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR5_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR6_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR7_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR8_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR9_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR10_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR11_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR12_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR13_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR14_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR15_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR16_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR17_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR18_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR19_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR20_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR21_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR22_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR23_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR24_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR25_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR26_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR27_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR28_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR29_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR30_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR31_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR32_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR33_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR34_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR35_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR36_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR37_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR38_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR39_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR40_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR41_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR42_D ((uint32_t)0x0000FFFF) |
| #define | RTC_BKP_NUMBER 42 |
| #define | BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
| #define | BKP_RTCCR_CCO ((uint32_t)0x00000080) |
| #define | BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
| #define | BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
| #define | BKP_CR_TPE ((uint32_t)0x00000001) |
| #define | BKP_CR_TPAL ((uint32_t)0x00000002) |
| #define | BKP_CSR_CTE ((uint32_t)0x00000001) |
| #define | BKP_CSR_CTI ((uint32_t)0x00000002) |
| #define | BKP_CSR_TPIE ((uint32_t)0x00000004) |
| #define | BKP_CSR_TEF ((uint32_t)0x00000100) |
| #define | BKP_CSR_TIF ((uint32_t)0x00000200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_USBPRE ((uint32_t)0x00400000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) |
| #define | RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) |
| #define | RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) |
| #define | RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) |
| #define | RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) |
| #define | RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) |
| #define | RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) |
| #define | RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) |
| #define | RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
| #define | RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
| #define | RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) |
| #define | RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) |
| #define | RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) |
| #define | RCC_AHBENR_FSMCEN ((uint32_t)0x00000100) |
| #define | RCC_AHBENR_SDIOEN ((uint32_t)0x00000400) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) |
| #define | RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) |
| #define | RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) |
| #define | RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) |
| #define | RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) |
| #define | RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) |
| #define | RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) |
| #define | RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_USBEN ((uint32_t)0x00800000) |
| #define | RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
| #define | RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
| #define | RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) |
| #define | RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) |
| #define | RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint32_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint32_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint32_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint32_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint32_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint32_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint32_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint32_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint32_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint32_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint32_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint32_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint32_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint32_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint32_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint32_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint32_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint32_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint32_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint32_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint32_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint32_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint32_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint32_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint32_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint32_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint32_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint32_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint32_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint32_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint32_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint32_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint32_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint32_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint32_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint32_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint32_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint32_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint32_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint32_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint32_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint32_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint32_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint32_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint32_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint32_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint32_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint32_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
| #define | AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
| #define | AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
| #define | AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
| #define | AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
| #define | AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PORT ((uint32_t)0x00000070) |
| #define | AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
| #define | AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
| #define | AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
| #define | AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) |
| #define | AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) |
| #define | AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
| #define | AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) |
| #define | AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) |
| #define | AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) |
| #define | AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
| #define | AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) |
| #define | AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) |
| #define | AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) |
| #define | AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) |
| #define | AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) |
| #define | SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) |
| #define | SCB_SCR_SEVONPEND ((uint32_t)0x00000010) |
| #define | SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) |
| #define | SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) |
| #define | SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) |
| #define | SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) |
| #define | SCB_CCR_STKALIGN ((uint32_t)0x00000200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint32_t)0x00000001) |
| #define | SCB_DFSR_BKPT ((uint32_t)0x00000002) |
| #define | SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) |
| #define | SCB_DFSR_VCATCH ((uint32_t)0x00000008) |
| #define | SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
| #define | ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
| #define | ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
| #define | ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
| #define | ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) |
| #define | DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) |
| #define | DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) |
| #define | TIM_CR1_CEN ((uint32_t)0x00000001) |
| #define | TIM_CR1_UDIS ((uint32_t)0x00000002) |
| #define | TIM_CR1_URS ((uint32_t)0x00000004) |
| #define | TIM_CR1_OPM ((uint32_t)0x00000008) |
| #define | TIM_CR1_DIR ((uint32_t)0x00000010) |
| #define | TIM_CR1_CMS ((uint32_t)0x00000060) |
| #define | TIM_CR1_CMS_0 ((uint32_t)0x00000020) |
| #define | TIM_CR1_CMS_1 ((uint32_t)0x00000040) |
| #define | TIM_CR1_ARPE ((uint32_t)0x00000080) |
| #define | TIM_CR1_CKD ((uint32_t)0x00000300) |
| #define | TIM_CR1_CKD_0 ((uint32_t)0x00000100) |
| #define | TIM_CR1_CKD_1 ((uint32_t)0x00000200) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00000007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint32_t)0x00000001) |
| #define | TIM_DIER_CC1IE ((uint32_t)0x00000002) |
| #define | TIM_DIER_CC2IE ((uint32_t)0x00000004) |
| #define | TIM_DIER_CC3IE ((uint32_t)0x00000008) |
| #define | TIM_DIER_CC4IE ((uint32_t)0x00000010) |
| #define | TIM_DIER_COMIE ((uint32_t)0x00000020) |
| #define | TIM_DIER_TIE ((uint32_t)0x00000040) |
| #define | TIM_DIER_BIE ((uint32_t)0x00000080) |
| #define | TIM_DIER_UDE ((uint32_t)0x00000100) |
| #define | TIM_DIER_CC1DE ((uint32_t)0x00000200) |
| #define | TIM_DIER_CC2DE ((uint32_t)0x00000400) |
| #define | TIM_DIER_CC3DE ((uint32_t)0x00000800) |
| #define | TIM_DIER_CC4DE ((uint32_t)0x00001000) |
| #define | TIM_DIER_COMDE ((uint32_t)0x00002000) |
| #define | TIM_DIER_TDE ((uint32_t)0x00004000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_EGR_UG ((uint32_t)0x00000001) |
| #define | TIM_EGR_CC1G ((uint32_t)0x00000002) |
| #define | TIM_EGR_CC2G ((uint32_t)0x00000004) |
| #define | TIM_EGR_CC3G ((uint32_t)0x00000008) |
| #define | TIM_EGR_CC4G ((uint32_t)0x00000010) |
| #define | TIM_EGR_COMG ((uint32_t)0x00000020) |
| #define | TIM_EGR_TG ((uint32_t)0x00000040) |
| #define | TIM_EGR_BG ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00000070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x00007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_PSC_PSC ((uint32_t)0x0000FFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint32_t)0x000000FF) |
| #define | TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_DCR_DBA ((uint32_t)0x0000001F) |
| #define | TIM_DCR_DBA_0 ((uint32_t)0x00000001) |
| #define | TIM_DCR_DBA_1 ((uint32_t)0x00000002) |
| #define | TIM_DCR_DBA_2 ((uint32_t)0x00000004) |
| #define | TIM_DCR_DBA_3 ((uint32_t)0x00000008) |
| #define | TIM_DCR_DBA_4 ((uint32_t)0x00000010) |
| #define | TIM_DCR_DBL ((uint32_t)0x00001F00) |
| #define | TIM_DCR_DBL_0 ((uint32_t)0x00000100) |
| #define | TIM_DCR_DBL_1 ((uint32_t)0x00000200) |
| #define | TIM_DCR_DBL_2 ((uint32_t)0x00000400) |
| #define | TIM_DCR_DBL_3 ((uint32_t)0x00000800) |
| #define | TIM_DCR_DBL_4 ((uint32_t)0x00001000) |
| #define | TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) |
| #define | RTC_CRH_SECIE ((uint32_t)0x00000001) |
| #define | RTC_CRH_ALRIE ((uint32_t)0x00000002) |
| #define | RTC_CRH_OWIE ((uint32_t)0x00000004) |
| #define | RTC_CRL_SECF ((uint32_t)0x00000001) |
| #define | RTC_CRL_ALRF ((uint32_t)0x00000002) |
| #define | RTC_CRL_OWF ((uint32_t)0x00000004) |
| #define | RTC_CRL_RSF ((uint32_t)0x00000008) |
| #define | RTC_CRL_CNF ((uint32_t)0x00000010) |
| #define | RTC_CRL_RTOFF ((uint32_t)0x00000020) |
| #define | RTC_PRLH_PRL ((uint32_t)0x0000000F) |
| #define | RTC_PRLL_PRL ((uint32_t)0x0000FFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) |
| #define | RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | IWDG_KR_KEY ((uint32_t)0x0000FFFF) |
| #define | IWDG_PR_PR ((uint32_t)0x00000007) |
| #define | IWDG_PR_PR_0 ((uint32_t)0x00000001) |
| #define | IWDG_PR_PR_1 ((uint32_t)0x00000002) |
| #define | IWDG_PR_PR_2 ((uint32_t)0x00000004) |
| #define | IWDG_RLR_RL ((uint32_t)0x00000FFF) |
| #define | IWDG_SR_PVU ((uint32_t)0x00000001) |
| #define | IWDG_SR_RVU ((uint32_t)0x00000002) |
| #define | WWDG_CR_T ((uint32_t)0x0000007F) |
| #define | WWDG_CR_T0 ((uint32_t)0x00000001) |
| #define | WWDG_CR_T1 ((uint32_t)0x00000002) |
| #define | WWDG_CR_T2 ((uint32_t)0x00000004) |
| #define | WWDG_CR_T3 ((uint32_t)0x00000008) |
| #define | WWDG_CR_T4 ((uint32_t)0x00000010) |
| #define | WWDG_CR_T5 ((uint32_t)0x00000020) |
| #define | WWDG_CR_T6 ((uint32_t)0x00000040) |
| #define | WWDG_CR_WDGA ((uint32_t)0x00000080) |
| #define | WWDG_CFR_W ((uint32_t)0x0000007F) |
| #define | WWDG_CFR_W0 ((uint32_t)0x00000001) |
| #define | WWDG_CFR_W1 ((uint32_t)0x00000002) |
| #define | WWDG_CFR_W2 ((uint32_t)0x00000004) |
| #define | WWDG_CFR_W3 ((uint32_t)0x00000008) |
| #define | WWDG_CFR_W4 ((uint32_t)0x00000010) |
| #define | WWDG_CFR_W5 ((uint32_t)0x00000020) |
| #define | WWDG_CFR_W6 ((uint32_t)0x00000040) |
| #define | WWDG_CFR_WDGTB ((uint32_t)0x00000180) |
| #define | WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) |
| #define | WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) |
| #define | WWDG_CFR_EWI ((uint32_t)0x00000200) |
| #define | WWDG_SR_EWIF ((uint32_t)0x00000001) |
| #define | FSMC_BCRx_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCRx_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCRx_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCRx_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCRx_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCRx_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCRx_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCRx_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCRx_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCRx_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCRx_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCRx_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCRx_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCRx_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCRx_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCRx_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCRx_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BTRx_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTRx_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTRx_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTRx_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTRx_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTRx_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTRx_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTRx_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTRx_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTRx_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTRx_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTRx_DATAST_4 ((uint32_t)0x00001000) |
| #define | FSMC_BTRx_DATAST_5 ((uint32_t)0x00002000) |
| #define | FSMC_BTRx_DATAST_6 ((uint32_t)0x00004000) |
| #define | FSMC_BTRx_DATAST_7 ((uint32_t)0x00008000) |
| #define | FSMC_BTRx_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTRx_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTRx_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTRx_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTRx_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTRx_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTRx_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTRx_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTRx_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTRx_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTRx_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTRx_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTRx_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTRx_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTRx_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTRx_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTRx_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTRx_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTRx_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTRx_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTRx_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTRx_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTRx_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTRx_DATAST_4 ((uint32_t)0x00001000) |
| #define | FSMC_BWTRx_DATAST_5 ((uint32_t)0x00002000) |
| #define | FSMC_BWTRx_DATAST_6 ((uint32_t)0x00004000) |
| #define | FSMC_BWTRx_DATAST_7 ((uint32_t)0x00008000) |
| #define | FSMC_BWTRx_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BWTRx_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BWTRx_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BWTRx_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BWTRx_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BWTRx_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTRx_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTRx_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_PCRx_PWAITEN ((uint32_t)0x00000002) |
| #define | FSMC_PCRx_PBKEN ((uint32_t)0x00000004) |
| #define | FSMC_PCRx_PTYP ((uint32_t)0x00000008) |
| #define | FSMC_PCRx_PWID ((uint32_t)0x00000030) |
| #define | FSMC_PCRx_PWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_PCRx_PWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_PCRx_ECCEN ((uint32_t)0x00000040) |
| #define | FSMC_PCRx_TCLR ((uint32_t)0x00001E00) |
| #define | FSMC_PCRx_TCLR_0 ((uint32_t)0x00000200) |
| #define | FSMC_PCRx_TCLR_1 ((uint32_t)0x00000400) |
| #define | FSMC_PCRx_TCLR_2 ((uint32_t)0x00000800) |
| #define | FSMC_PCRx_TCLR_3 ((uint32_t)0x00001000) |
| #define | FSMC_PCRx_TAR ((uint32_t)0x0001E000) |
| #define | FSMC_PCRx_TAR_0 ((uint32_t)0x00002000) |
| #define | FSMC_PCRx_TAR_1 ((uint32_t)0x00004000) |
| #define | FSMC_PCRx_TAR_2 ((uint32_t)0x00008000) |
| #define | FSMC_PCRx_TAR_3 ((uint32_t)0x00010000) |
| #define | FSMC_PCRx_ECCPS ((uint32_t)0x000E0000) |
| #define | FSMC_PCRx_ECCPS_0 ((uint32_t)0x00020000) |
| #define | FSMC_PCRx_ECCPS_1 ((uint32_t)0x00040000) |
| #define | FSMC_PCRx_ECCPS_2 ((uint32_t)0x00080000) |
| #define | FSMC_SRx_IRS ((uint32_t)0x00000001) |
| #define | FSMC_SRx_ILS ((uint32_t)0x00000002) |
| #define | FSMC_SRx_IFS ((uint32_t)0x00000004) |
| #define | FSMC_SRx_IREN ((uint32_t)0x00000008) |
| #define | FSMC_SRx_ILEN ((uint32_t)0x00000010) |
| #define | FSMC_SRx_IFEN ((uint32_t)0x00000020) |
| #define | FSMC_SRx_FEMPT ((uint32_t)0x00000040) |
| #define | FSMC_PMEMx_MEMSETx ((uint32_t)0x000000FF) |
| #define | FSMC_PMEMx_MEMSETx_0 ((uint32_t)0x00000001) |
| #define | FSMC_PMEMx_MEMSETx_1 ((uint32_t)0x00000002) |
| #define | FSMC_PMEMx_MEMSETx_2 ((uint32_t)0x00000004) |
| #define | FSMC_PMEMx_MEMSETx_3 ((uint32_t)0x00000008) |
| #define | FSMC_PMEMx_MEMSETx_4 ((uint32_t)0x00000010) |
| #define | FSMC_PMEMx_MEMSETx_5 ((uint32_t)0x00000020) |
| #define | FSMC_PMEMx_MEMSETx_6 ((uint32_t)0x00000040) |
| #define | FSMC_PMEMx_MEMSETx_7 ((uint32_t)0x00000080) |
| #define | FSMC_PMEMx_MEMWAITx ((uint32_t)0x0000FF00) |
| #define | FSMC_PMEMx_MEMWAIT2_0 ((uint32_t)0x00000100) |
| #define | FSMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) |
| #define | FSMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) |
| #define | FSMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) |
| #define | FSMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) |
| #define | FSMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) |
| #define | FSMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) |
| #define | FSMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) |
| #define | FSMC_PMEMx_MEMHOLDx ((uint32_t)0x00FF0000) |
| #define | FSMC_PMEMx_MEMHOLDx_0 ((uint32_t)0x00010000) |
| #define | FSMC_PMEMx_MEMHOLDx_1 ((uint32_t)0x00020000) |
| #define | FSMC_PMEMx_MEMHOLDx_2 ((uint32_t)0x00040000) |
| #define | FSMC_PMEMx_MEMHOLDx_3 ((uint32_t)0x00080000) |
| #define | FSMC_PMEMx_MEMHOLDx_4 ((uint32_t)0x00100000) |
| #define | FSMC_PMEMx_MEMHOLDx_5 ((uint32_t)0x00200000) |
| #define | FSMC_PMEMx_MEMHOLDx_6 ((uint32_t)0x00400000) |
| #define | FSMC_PMEMx_MEMHOLDx_7 ((uint32_t)0x00800000) |
| #define | FSMC_PMEMx_MEMHIZx ((uint32_t)0xFF000000) |
| #define | FSMC_PMEMx_MEMHIZx_0 ((uint32_t)0x01000000) |
| #define | FSMC_PMEMx_MEMHIZx_1 ((uint32_t)0x02000000) |
| #define | FSMC_PMEMx_MEMHIZx_2 ((uint32_t)0x04000000) |
| #define | FSMC_PMEMx_MEMHIZx_3 ((uint32_t)0x08000000) |
| #define | FSMC_PMEMx_MEMHIZx_4 ((uint32_t)0x10000000) |
| #define | FSMC_PMEMx_MEMHIZx_5 ((uint32_t)0x20000000) |
| #define | FSMC_PMEMx_MEMHIZx_6 ((uint32_t)0x40000000) |
| #define | FSMC_PMEMx_MEMHIZx_7 ((uint32_t)0x80000000) |
| #define | FSMC_PATTx_ATTSETx ((uint32_t)0x000000FF) |
| #define | FSMC_PATTx_ATTSETx_0 ((uint32_t)0x00000001) |
| #define | FSMC_PATTx_ATTSETx_1 ((uint32_t)0x00000002) |
| #define | FSMC_PATTx_ATTSETx_2 ((uint32_t)0x00000004) |
| #define | FSMC_PATTx_ATTSETx_3 ((uint32_t)0x00000008) |
| #define | FSMC_PATTx_ATTSETx_4 ((uint32_t)0x00000010) |
| #define | FSMC_PATTx_ATTSETx_5 ((uint32_t)0x00000020) |
| #define | FSMC_PATTx_ATTSETx_6 ((uint32_t)0x00000040) |
| #define | FSMC_PATTx_ATTSETx_7 ((uint32_t)0x00000080) |
| #define | FSMC_PATTx_ATTWAITx ((uint32_t)0x0000FF00) |
| #define | FSMC_PATTx_ATTWAITx_0 ((uint32_t)0x00000100) |
| #define | FSMC_PATTx_ATTWAITx_1 ((uint32_t)0x00000200) |
| #define | FSMC_PATTx_ATTWAITx_2 ((uint32_t)0x00000400) |
| #define | FSMC_PATTx_ATTWAITx_3 ((uint32_t)0x00000800) |
| #define | FSMC_PATTx_ATTWAITx_4 ((uint32_t)0x00001000) |
| #define | FSMC_PATTx_ATTWAITx_5 ((uint32_t)0x00002000) |
| #define | FSMC_PATTx_ATTWAITx_6 ((uint32_t)0x00004000) |
| #define | FSMC_PATTx_ATTWAITx_7 ((uint32_t)0x00008000) |
| #define | FSMC_PATTx_ATTHOLDx ((uint32_t)0x00FF0000) |
| #define | FSMC_PATTx_ATTHOLDx_0 ((uint32_t)0x00010000) |
| #define | FSMC_PATTx_ATTHOLDx_1 ((uint32_t)0x00020000) |
| #define | FSMC_PATTx_ATTHOLDx_2 ((uint32_t)0x00040000) |
| #define | FSMC_PATTx_ATTHOLDx_3 ((uint32_t)0x00080000) |
| #define | FSMC_PATTx_ATTHOLDx_4 ((uint32_t)0x00100000) |
| #define | FSMC_PATTx_ATTHOLDx_5 ((uint32_t)0x00200000) |
| #define | FSMC_PATTx_ATTHOLDx_6 ((uint32_t)0x00400000) |
| #define | FSMC_PATTx_ATTHOLDx_7 ((uint32_t)0x00800000) |
| #define | FSMC_PATTx_ATTHIZx ((uint32_t)0xFF000000) |
| #define | FSMC_PATTx_ATTHIZx_0 ((uint32_t)0x01000000) |
| #define | FSMC_PATTx_ATTHIZx_1 ((uint32_t)0x02000000) |
| #define | FSMC_PATTx_ATTHIZx_2 ((uint32_t)0x04000000) |
| #define | FSMC_PATTx_ATTHIZx_3 ((uint32_t)0x08000000) |
| #define | FSMC_PATTx_ATTHIZx_4 ((uint32_t)0x10000000) |
| #define | FSMC_PATTx_ATTHIZx_5 ((uint32_t)0x20000000) |
| #define | FSMC_PATTx_ATTHIZx_6 ((uint32_t)0x40000000) |
| #define | FSMC_PATTx_ATTHIZx_7 ((uint32_t)0x80000000) |
| #define | FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) |
| #define | FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) |
| #define | FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) |
| #define | FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) |
| #define | FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) |
| #define | FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) |
| #define | FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) |
| #define | FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) |
| #define | FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) |
| #define | FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) |
| #define | FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) |
| #define | FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) |
| #define | FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) |
| #define | FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) |
| #define | FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) |
| #define | FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) |
| #define | FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) |
| #define | FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) |
| #define | FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) |
| #define | FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) |
| #define | FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) |
| #define | FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) |
| #define | FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) |
| #define | FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) |
| #define | FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) |
| #define | FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) |
| #define | FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) |
| #define | FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) |
| #define | FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) |
| #define | FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) |
| #define | FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) |
| #define | FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) |
| #define | FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) |
| #define | FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) |
| #define | FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) |
| #define | FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) |
| #define | FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) |
| #define | FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_POWER_PWRCTRL ((uint32_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint32_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint32_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint32_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint32_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint32_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint32_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint32_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint32_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint32_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint32_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint32_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint32_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint32_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint32_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint32_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | USB_EP0R USB_BASE |
| #define | USB_EP1R (USB_BASE + 0x00000004) |
| #define | USB_EP2R (USB_BASE + 0x00000008) |
| #define | USB_EP3R (USB_BASE + 0x0000000C) |
| #define | USB_EP4R (USB_BASE + 0x00000010) |
| #define | USB_EP5R (USB_BASE + 0x00000014) |
| #define | USB_EP6R (USB_BASE + 0x00000018) |
| #define | USB_EP7R (USB_BASE + 0x0000001C) |
| #define | USB_EP_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EPRX_STAT ((uint32_t)0x00003000) |
| #define | USB_EP_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP_T_FIELD ((uint32_t)0x00000600) |
| #define | USB_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EPTX_STAT ((uint32_t)0x00000030) |
| #define | USB_EPADDR_FIELD ((uint32_t)0x0000000F) |
| #define | USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) |
| #define | USB_EP_TYPE_MASK ((uint32_t)0x00000600) |
| #define | USB_EP_BULK ((uint32_t)0x00000000) |
| #define | USB_EP_CONTROL ((uint32_t)0x00000200) |
| #define | USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) |
| #define | USB_EP_INTERRUPT ((uint32_t)0x00000600) |
| #define | USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) |
| #define | USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) |
| #define | USB_EP_TX_DIS ((uint32_t)0x00000000) |
| #define | USB_EP_TX_STALL ((uint32_t)0x00000010) |
| #define | USB_EP_TX_NAK ((uint32_t)0x00000020) |
| #define | USB_EP_TX_VALID ((uint32_t)0x00000030) |
| #define | USB_EPTX_DTOG1 ((uint32_t)0x00000010) |
| #define | USB_EPTX_DTOG2 ((uint32_t)0x00000020) |
| #define | USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) |
| #define | USB_EP_RX_DIS ((uint32_t)0x00000000) |
| #define | USB_EP_RX_STALL ((uint32_t)0x00001000) |
| #define | USB_EP_RX_NAK ((uint32_t)0x00002000) |
| #define | USB_EP_RX_VALID ((uint32_t)0x00003000) |
| #define | USB_EPRX_DTOG1 ((uint32_t)0x00001000) |
| #define | USB_EPRX_DTOG2 ((uint32_t)0x00002000) |
| #define | USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) |
| #define | USB_EP0R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP0R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP0R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP0R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP0R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP0R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP0R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP0R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP0R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP0R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP1R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP1R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP1R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP1R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP1R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP1R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP1R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP1R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP1R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP1R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP2R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP2R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP2R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP2R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP2R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP2R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP2R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP2R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP2R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP2R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP3R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP3R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP3R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP3R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP3R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP3R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP3R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP3R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP3R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP3R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP4R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP4R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP4R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP4R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP4R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP4R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP4R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP4R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP4R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP4R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP5R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP5R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP5R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP5R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP5R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP5R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP5R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP5R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP5R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP5R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP6R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP6R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP6R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP6R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP6R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP6R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP6R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP6R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP6R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP6R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_EP7R_EA ((uint32_t)0x0000000F) |
| #define | USB_EP7R_STAT_TX ((uint32_t)0x00000030) |
| #define | USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) |
| #define | USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) |
| #define | USB_EP7R_DTOG_TX ((uint32_t)0x00000040) |
| #define | USB_EP7R_CTR_TX ((uint32_t)0x00000080) |
| #define | USB_EP7R_EP_KIND ((uint32_t)0x00000100) |
| #define | USB_EP7R_EP_TYPE ((uint32_t)0x00000600) |
| #define | USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) |
| #define | USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) |
| #define | USB_EP7R_SETUP ((uint32_t)0x00000800) |
| #define | USB_EP7R_STAT_RX ((uint32_t)0x00003000) |
| #define | USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) |
| #define | USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) |
| #define | USB_EP7R_DTOG_RX ((uint32_t)0x00004000) |
| #define | USB_EP7R_CTR_RX ((uint32_t)0x00008000) |
| #define | USB_CNTR_FRES ((uint32_t)0x00000001) |
| #define | USB_CNTR_PDWN ((uint32_t)0x00000002) |
| #define | USB_CNTR_LP_MODE ((uint32_t)0x00000004) |
| #define | USB_CNTR_FSUSP ((uint32_t)0x00000008) |
| #define | USB_CNTR_RESUME ((uint32_t)0x00000010) |
| #define | USB_CNTR_ESOFM ((uint32_t)0x00000100) |
| #define | USB_CNTR_SOFM ((uint32_t)0x00000200) |
| #define | USB_CNTR_RESETM ((uint32_t)0x00000400) |
| #define | USB_CNTR_SUSPM ((uint32_t)0x00000800) |
| #define | USB_CNTR_WKUPM ((uint32_t)0x00001000) |
| #define | USB_CNTR_ERRM ((uint32_t)0x00002000) |
| #define | USB_CNTR_PMAOVRM ((uint32_t)0x00004000) |
| #define | USB_CNTR_CTRM ((uint32_t)0x00008000) |
| #define | USB_ISTR_EP_ID ((uint32_t)0x0000000F) |
| #define | USB_ISTR_DIR ((uint32_t)0x00000010) |
| #define | USB_ISTR_ESOF ((uint32_t)0x00000100) |
| #define | USB_ISTR_SOF ((uint32_t)0x00000200) |
| #define | USB_ISTR_RESET ((uint32_t)0x00000400) |
| #define | USB_ISTR_SUSP ((uint32_t)0x00000800) |
| #define | USB_ISTR_WKUP ((uint32_t)0x00001000) |
| #define | USB_ISTR_ERR ((uint32_t)0x00002000) |
| #define | USB_ISTR_PMAOVR ((uint32_t)0x00004000) |
| #define | USB_ISTR_CTR ((uint32_t)0x00008000) |
| #define | USB_FNR_FN ((uint32_t)0x000007FF) |
| #define | USB_FNR_LSOF ((uint32_t)0x00001800) |
| #define | USB_FNR_LCK ((uint32_t)0x00002000) |
| #define | USB_FNR_RXDM ((uint32_t)0x00004000) |
| #define | USB_FNR_RXDP ((uint32_t)0x00008000) |
| #define | USB_DADDR_ADD ((uint32_t)0x0000007F) |
| #define | USB_DADDR_ADD0 ((uint32_t)0x00000001) |
| #define | USB_DADDR_ADD1 ((uint32_t)0x00000002) |
| #define | USB_DADDR_ADD2 ((uint32_t)0x00000004) |
| #define | USB_DADDR_ADD3 ((uint32_t)0x00000008) |
| #define | USB_DADDR_ADD4 ((uint32_t)0x00000010) |
| #define | USB_DADDR_ADD5 ((uint32_t)0x00000020) |
| #define | USB_DADDR_ADD6 ((uint32_t)0x00000040) |
| #define | USB_DADDR_EF ((uint32_t)0x00000080) |
| #define | USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) |
| #define | USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) |
| #define | USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) |
| #define | USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) |
| #define | USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) |
| #define | USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) |
| #define | USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | CAN_MCR_INRQ ((uint32_t)0x00000001) |
| #define | CAN_MCR_SLEEP ((uint32_t)0x00000002) |
| #define | CAN_MCR_TXFP ((uint32_t)0x00000004) |
| #define | CAN_MCR_RFLM ((uint32_t)0x00000008) |
| #define | CAN_MCR_NART ((uint32_t)0x00000010) |
| #define | CAN_MCR_AWUM ((uint32_t)0x00000020) |
| #define | CAN_MCR_ABOM ((uint32_t)0x00000040) |
| #define | CAN_MCR_TTCM ((uint32_t)0x00000080) |
| #define | CAN_MCR_RESET ((uint32_t)0x00008000) |
| #define | CAN_MCR_DBF ((uint32_t)0x00010000) |
| #define | CAN_MSR_INAK ((uint32_t)0x00000001) |
| #define | CAN_MSR_SLAK ((uint32_t)0x00000002) |
| #define | CAN_MSR_ERRI ((uint32_t)0x00000004) |
| #define | CAN_MSR_WKUI ((uint32_t)0x00000008) |
| #define | CAN_MSR_SLAKI ((uint32_t)0x00000010) |
| #define | CAN_MSR_TXM ((uint32_t)0x00000100) |
| #define | CAN_MSR_RXM ((uint32_t)0x00000200) |
| #define | CAN_MSR_SAMP ((uint32_t)0x00000400) |
| #define | CAN_MSR_RX ((uint32_t)0x00000800) |
| #define | CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
| #define | CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
| #define | CAN_TSR_ALST0 ((uint32_t)0x00000004) |
| #define | CAN_TSR_TERR0 ((uint32_t)0x00000008) |
| #define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
| #define | CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
| #define | CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
| #define | CAN_TSR_ALST1 ((uint32_t)0x00000400) |
| #define | CAN_TSR_TERR1 ((uint32_t)0x00000800) |
| #define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
| #define | CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
| #define | CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
| #define | CAN_TSR_ALST2 ((uint32_t)0x00040000) |
| #define | CAN_TSR_TERR2 ((uint32_t)0x00080000) |
| #define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
| #define | CAN_TSR_CODE ((uint32_t)0x03000000) |
| #define | CAN_TSR_TME ((uint32_t)0x1C000000) |
| #define | CAN_TSR_TME0 ((uint32_t)0x04000000) |
| #define | CAN_TSR_TME1 ((uint32_t)0x08000000) |
| #define | CAN_TSR_TME2 ((uint32_t)0x10000000) |
| #define | CAN_TSR_LOW ((uint32_t)0xE0000000) |
| #define | CAN_TSR_LOW0 ((uint32_t)0x20000000) |
| #define | CAN_TSR_LOW1 ((uint32_t)0x40000000) |
| #define | CAN_TSR_LOW2 ((uint32_t)0x80000000) |
| #define | CAN_RF0R_FMP0 ((uint32_t)0x00000003) |
| #define | CAN_RF0R_FULL0 ((uint32_t)0x00000008) |
| #define | CAN_RF0R_FOVR0 ((uint32_t)0x00000010) |
| #define | CAN_RF0R_RFOM0 ((uint32_t)0x00000020) |
| #define | CAN_RF1R_FMP1 ((uint32_t)0x00000003) |
| #define | CAN_RF1R_FULL1 ((uint32_t)0x00000008) |
| #define | CAN_RF1R_FOVR1 ((uint32_t)0x00000010) |
| #define | CAN_RF1R_RFOM1 ((uint32_t)0x00000020) |
| #define | CAN_IER_TMEIE ((uint32_t)0x00000001) |
| #define | CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
| #define | CAN_IER_FFIE0 ((uint32_t)0x00000004) |
| #define | CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
| #define | CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
| #define | CAN_IER_FFIE1 ((uint32_t)0x00000020) |
| #define | CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
| #define | CAN_IER_EWGIE ((uint32_t)0x00000100) |
| #define | CAN_IER_EPVIE ((uint32_t)0x00000200) |
| #define | CAN_IER_BOFIE ((uint32_t)0x00000400) |
| #define | CAN_IER_LECIE ((uint32_t)0x00000800) |
| #define | CAN_IER_ERRIE ((uint32_t)0x00008000) |
| #define | CAN_IER_WKUIE ((uint32_t)0x00010000) |
| #define | CAN_IER_SLKIE ((uint32_t)0x00020000) |
| #define | CAN_ESR_EWGF ((uint32_t)0x00000001) |
| #define | CAN_ESR_EPVF ((uint32_t)0x00000002) |
| #define | CAN_ESR_BOFF ((uint32_t)0x00000004) |
| #define | CAN_ESR_LEC ((uint32_t)0x00000070) |
| #define | CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
| #define | CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
| #define | CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
| #define | CAN_ESR_TEC ((uint32_t)0x00FF0000) |
| #define | CAN_ESR_REC ((uint32_t)0xFF000000) |
| #define | CAN_BTR_BRP ((uint32_t)0x000003FF) |
| #define | CAN_BTR_TS1 ((uint32_t)0x000F0000) |
| #define | CAN_BTR_TS1_0 ((uint32_t)0x00010000) |
| #define | CAN_BTR_TS1_1 ((uint32_t)0x00020000) |
| #define | CAN_BTR_TS1_2 ((uint32_t)0x00040000) |
| #define | CAN_BTR_TS1_3 ((uint32_t)0x00080000) |
| #define | CAN_BTR_TS2 ((uint32_t)0x00700000) |
| #define | CAN_BTR_TS2_0 ((uint32_t)0x00100000) |
| #define | CAN_BTR_TS2_1 ((uint32_t)0x00200000) |
| #define | CAN_BTR_TS2_2 ((uint32_t)0x00400000) |
| #define | CAN_BTR_SJW ((uint32_t)0x03000000) |
| #define | CAN_BTR_SJW_0 ((uint32_t)0x01000000) |
| #define | CAN_BTR_SJW_1 ((uint32_t)0x02000000) |
| #define | CAN_BTR_LBKM ((uint32_t)0x40000000) |
| #define | CAN_BTR_SILM ((uint32_t)0x80000000) |
| #define | CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT0R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT1R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI2R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI2R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI2R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT2R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_FMR_FINIT ((uint32_t)0x00000001) |
| #define | CAN_FMR_CAN2SB ((uint32_t)0x00003F00) |
| #define | CAN_FM1R_FBM ((uint32_t)0x00003FFF) |
| #define | CAN_FM1R_FBM0 ((uint32_t)0x00000001) |
| #define | CAN_FM1R_FBM1 ((uint32_t)0x00000002) |
| #define | CAN_FM1R_FBM2 ((uint32_t)0x00000004) |
| #define | CAN_FM1R_FBM3 ((uint32_t)0x00000008) |
| #define | CAN_FM1R_FBM4 ((uint32_t)0x00000010) |
| #define | CAN_FM1R_FBM5 ((uint32_t)0x00000020) |
| #define | CAN_FM1R_FBM6 ((uint32_t)0x00000040) |
| #define | CAN_FM1R_FBM7 ((uint32_t)0x00000080) |
| #define | CAN_FM1R_FBM8 ((uint32_t)0x00000100) |
| #define | CAN_FM1R_FBM9 ((uint32_t)0x00000200) |
| #define | CAN_FM1R_FBM10 ((uint32_t)0x00000400) |
| #define | CAN_FM1R_FBM11 ((uint32_t)0x00000800) |
| #define | CAN_FM1R_FBM12 ((uint32_t)0x00001000) |
| #define | CAN_FM1R_FBM13 ((uint32_t)0x00002000) |
| #define | CAN_FS1R_FSC ((uint32_t)0x00003FFF) |
| #define | CAN_FS1R_FSC0 ((uint32_t)0x00000001) |
| #define | CAN_FS1R_FSC1 ((uint32_t)0x00000002) |
| #define | CAN_FS1R_FSC2 ((uint32_t)0x00000004) |
| #define | CAN_FS1R_FSC3 ((uint32_t)0x00000008) |
| #define | CAN_FS1R_FSC4 ((uint32_t)0x00000010) |
| #define | CAN_FS1R_FSC5 ((uint32_t)0x00000020) |
| #define | CAN_FS1R_FSC6 ((uint32_t)0x00000040) |
| #define | CAN_FS1R_FSC7 ((uint32_t)0x00000080) |
| #define | CAN_FS1R_FSC8 ((uint32_t)0x00000100) |
| #define | CAN_FS1R_FSC9 ((uint32_t)0x00000200) |
| #define | CAN_FS1R_FSC10 ((uint32_t)0x00000400) |
| #define | CAN_FS1R_FSC11 ((uint32_t)0x00000800) |
| #define | CAN_FS1R_FSC12 ((uint32_t)0x00001000) |
| #define | CAN_FS1R_FSC13 ((uint32_t)0x00002000) |
| #define | CAN_FFA1R_FFA ((uint32_t)0x00003FFF) |
| #define | CAN_FFA1R_FFA0 ((uint32_t)0x00000001) |
| #define | CAN_FFA1R_FFA1 ((uint32_t)0x00000002) |
| #define | CAN_FFA1R_FFA2 ((uint32_t)0x00000004) |
| #define | CAN_FFA1R_FFA3 ((uint32_t)0x00000008) |
| #define | CAN_FFA1R_FFA4 ((uint32_t)0x00000010) |
| #define | CAN_FFA1R_FFA5 ((uint32_t)0x00000020) |
| #define | CAN_FFA1R_FFA6 ((uint32_t)0x00000040) |
| #define | CAN_FFA1R_FFA7 ((uint32_t)0x00000080) |
| #define | CAN_FFA1R_FFA8 ((uint32_t)0x00000100) |
| #define | CAN_FFA1R_FFA9 ((uint32_t)0x00000200) |
| #define | CAN_FFA1R_FFA10 ((uint32_t)0x00000400) |
| #define | CAN_FFA1R_FFA11 ((uint32_t)0x00000800) |
| #define | CAN_FFA1R_FFA12 ((uint32_t)0x00001000) |
| #define | CAN_FFA1R_FFA13 ((uint32_t)0x00002000) |
| #define | CAN_FA1R_FACT ((uint32_t)0x00003FFF) |
| #define | CAN_FA1R_FACT0 ((uint32_t)0x00000001) |
| #define | CAN_FA1R_FACT1 ((uint32_t)0x00000002) |
| #define | CAN_FA1R_FACT2 ((uint32_t)0x00000004) |
| #define | CAN_FA1R_FACT3 ((uint32_t)0x00000008) |
| #define | CAN_FA1R_FACT4 ((uint32_t)0x00000010) |
| #define | CAN_FA1R_FACT5 ((uint32_t)0x00000020) |
| #define | CAN_FA1R_FACT6 ((uint32_t)0x00000040) |
| #define | CAN_FA1R_FACT7 ((uint32_t)0x00000080) |
| #define | CAN_FA1R_FACT8 ((uint32_t)0x00000100) |
| #define | CAN_FA1R_FACT9 ((uint32_t)0x00000200) |
| #define | CAN_FA1R_FACT10 ((uint32_t)0x00000400) |
| #define | CAN_FA1R_FACT11 ((uint32_t)0x00000800) |
| #define | CAN_FA1R_FACT12 ((uint32_t)0x00001000) |
| #define | CAN_FA1R_FACT13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F0R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R2_FB31 ((uint32_t)0x80000000) |
| #define | SPI_CR1_CPHA ((uint32_t)0x00000001) |
| #define | SPI_CR1_CPOL ((uint32_t)0x00000002) |
| #define | SPI_CR1_MSTR ((uint32_t)0x00000004) |
| #define | SPI_CR1_BR ((uint32_t)0x00000038) |
| #define | SPI_CR1_BR_0 ((uint32_t)0x00000008) |
| #define | SPI_CR1_BR_1 ((uint32_t)0x00000010) |
| #define | SPI_CR1_BR_2 ((uint32_t)0x00000020) |
| #define | SPI_CR1_SPE ((uint32_t)0x00000040) |
| #define | SPI_CR1_LSBFIRST ((uint32_t)0x00000080) |
| #define | SPI_CR1_SSI ((uint32_t)0x00000100) |
| #define | SPI_CR1_SSM ((uint32_t)0x00000200) |
| #define | SPI_CR1_RXONLY ((uint32_t)0x00000400) |
| #define | SPI_CR1_DFF ((uint32_t)0x00000800) |
| #define | SPI_CR1_CRCNEXT ((uint32_t)0x00001000) |
| #define | SPI_CR1_CRCEN ((uint32_t)0x00002000) |
| #define | SPI_CR1_BIDIOE ((uint32_t)0x00004000) |
| #define | SPI_CR1_BIDIMODE ((uint32_t)0x00008000) |
| #define | SPI_CR2_RXDMAEN ((uint32_t)0x00000001) |
| #define | SPI_CR2_TXDMAEN ((uint32_t)0x00000002) |
| #define | SPI_CR2_SSOE ((uint32_t)0x00000004) |
| #define | SPI_CR2_ERRIE ((uint32_t)0x00000020) |
| #define | SPI_CR2_RXNEIE ((uint32_t)0x00000040) |
| #define | SPI_CR2_TXEIE ((uint32_t)0x00000080) |
| #define | SPI_SR_RXNE ((uint32_t)0x00000001) |
| #define | SPI_SR_TXE ((uint32_t)0x00000002) |
| #define | SPI_SR_CHSIDE ((uint32_t)0x00000004) |
| #define | SPI_SR_UDR ((uint32_t)0x00000008) |
| #define | SPI_SR_CRCERR ((uint32_t)0x00000010) |
| #define | SPI_SR_MODF ((uint32_t)0x00000020) |
| #define | SPI_SR_OVR ((uint32_t)0x00000040) |
| #define | SPI_SR_BSY ((uint32_t)0x00000080) |
| #define | SPI_DR_DR ((uint32_t)0x0000FFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) |
| #define | SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) |
| #define | SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) |
| #define | SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) |
| #define | SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) |
| #define | SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) |
| #define | SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) |
| #define | SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) |
| #define | SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) |
| #define | SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) |
| #define | SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) |
| #define | SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) |
| #define | SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) |
| #define | SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) |
| #define | SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) |
| #define | SPI_I2SPR_ODD ((uint32_t)0x00000100) |
| #define | SPI_I2SPR_MCKOE ((uint32_t)0x00000200) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_SMBUS ((uint32_t)0x00000002) |
| #define | I2C_CR1_SMBTYPE ((uint32_t)0x00000008) |
| #define | I2C_CR1_ENARP ((uint32_t)0x00000010) |
| #define | I2C_CR1_ENPEC ((uint32_t)0x00000020) |
| #define | I2C_CR1_ENGC ((uint32_t)0x00000040) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) |
| #define | I2C_CR1_START ((uint32_t)0x00000100) |
| #define | I2C_CR1_STOP ((uint32_t)0x00000200) |
| #define | I2C_CR1_ACK ((uint32_t)0x00000400) |
| #define | I2C_CR1_POS ((uint32_t)0x00000800) |
| #define | I2C_CR1_PEC ((uint32_t)0x00001000) |
| #define | I2C_CR1_ALERT ((uint32_t)0x00002000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00008000) |
| #define | I2C_CR2_FREQ ((uint32_t)0x0000003F) |
| #define | I2C_CR2_FREQ_0 ((uint32_t)0x00000001) |
| #define | I2C_CR2_FREQ_1 ((uint32_t)0x00000002) |
| #define | I2C_CR2_FREQ_2 ((uint32_t)0x00000004) |
| #define | I2C_CR2_FREQ_3 ((uint32_t)0x00000008) |
| #define | I2C_CR2_FREQ_4 ((uint32_t)0x00000010) |
| #define | I2C_CR2_FREQ_5 ((uint32_t)0x00000020) |
| #define | I2C_CR2_ITERREN ((uint32_t)0x00000100) |
| #define | I2C_CR2_ITEVTEN ((uint32_t)0x00000200) |
| #define | I2C_CR2_ITBUFEN ((uint32_t)0x00000400) |
| #define | I2C_CR2_DMAEN ((uint32_t)0x00000800) |
| #define | I2C_CR2_LAST ((uint32_t)0x00001000) |
| #define | I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) |
| #define | I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) |
| #define | I2C_OAR1_ADD0 ((uint32_t)0x00000001) |
| #define | I2C_OAR1_ADD1 ((uint32_t)0x00000002) |
| #define | I2C_OAR1_ADD2 ((uint32_t)0x00000004) |
| #define | I2C_OAR1_ADD3 ((uint32_t)0x00000008) |
| #define | I2C_OAR1_ADD4 ((uint32_t)0x00000010) |
| #define | I2C_OAR1_ADD5 ((uint32_t)0x00000020) |
| #define | I2C_OAR1_ADD6 ((uint32_t)0x00000040) |
| #define | I2C_OAR1_ADD7 ((uint32_t)0x00000080) |
| #define | I2C_OAR1_ADD8 ((uint32_t)0x00000100) |
| #define | I2C_OAR1_ADD9 ((uint32_t)0x00000200) |
| #define | I2C_OAR1_ADDMODE ((uint32_t)0x00008000) |
| #define | I2C_OAR2_ENDUAL ((uint32_t)0x00000001) |
| #define | I2C_OAR2_ADD2 ((uint32_t)0x000000FE) |
| #define | I2C_SR1_SB ((uint32_t)0x00000001) |
| #define | I2C_SR1_ADDR ((uint32_t)0x00000002) |
| #define | I2C_SR1_BTF ((uint32_t)0x00000004) |
| #define | I2C_SR1_ADD10 ((uint32_t)0x00000008) |
| #define | I2C_SR1_STOPF ((uint32_t)0x00000010) |
| #define | I2C_SR1_RXNE ((uint32_t)0x00000040) |
| #define | I2C_SR1_TXE ((uint32_t)0x00000080) |
| #define | I2C_SR1_BERR ((uint32_t)0x00000100) |
| #define | I2C_SR1_ARLO ((uint32_t)0x00000200) |
| #define | I2C_SR1_AF ((uint32_t)0x00000400) |
| #define | I2C_SR1_OVR ((uint32_t)0x00000800) |
| #define | I2C_SR1_PECERR ((uint32_t)0x00001000) |
| #define | I2C_SR1_TIMEOUT ((uint32_t)0x00004000) |
| #define | I2C_SR1_SMBALERT ((uint32_t)0x00008000) |
| #define | I2C_SR2_MSL ((uint32_t)0x00000001) |
| #define | I2C_SR2_BUSY ((uint32_t)0x00000002) |
| #define | I2C_SR2_TRA ((uint32_t)0x00000004) |
| #define | I2C_SR2_GENCALL ((uint32_t)0x00000010) |
| #define | I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) |
| #define | I2C_SR2_SMBHOST ((uint32_t)0x00000040) |
| #define | I2C_SR2_DUALF ((uint32_t)0x00000080) |
| #define | I2C_SR2_PEC ((uint32_t)0x0000FF00) |
| #define | I2C_CCR_CCR ((uint32_t)0x00000FFF) |
| #define | I2C_CCR_DUTY ((uint32_t)0x00004000) |
| #define | I2C_CCR_FS ((uint32_t)0x00008000) |
| #define | I2C_TRISE_TRISE ((uint32_t)0x0000003F) |
| #define | USART_SR_PE ((uint32_t)0x00000001) |
| #define | USART_SR_FE ((uint32_t)0x00000002) |
| #define | USART_SR_NE ((uint32_t)0x00000004) |
| #define | USART_SR_ORE ((uint32_t)0x00000008) |
| #define | USART_SR_IDLE ((uint32_t)0x00000010) |
| #define | USART_SR_RXNE ((uint32_t)0x00000020) |
| #define | USART_SR_TC ((uint32_t)0x00000040) |
| #define | USART_SR_TXE ((uint32_t)0x00000080) |
| #define | USART_SR_LBD ((uint32_t)0x00000100) |
| #define | USART_SR_CTS ((uint32_t)0x00000200) |
| #define | USART_DR_DR ((uint32_t)0x000001FF) |
| #define | USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) |
| #define | USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) |
| #define | USART_CR1_SBK ((uint32_t)0x00000001) |
| #define | USART_CR1_RWU ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_UE ((uint32_t)0x00002000) |
| #define | USART_CR2_ADD ((uint32_t)0x0000000F) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_GTPR_PSC ((uint32_t)0x000000FF) |
| #define | USART_GTPR_PSC_0 ((uint32_t)0x00000001) |
| #define | USART_GTPR_PSC_1 ((uint32_t)0x00000002) |
| #define | USART_GTPR_PSC_2 ((uint32_t)0x00000004) |
| #define | USART_GTPR_PSC_3 ((uint32_t)0x00000008) |
| #define | USART_GTPR_PSC_4 ((uint32_t)0x00000010) |
| #define | USART_GTPR_PSC_5 ((uint32_t)0x00000020) |
| #define | USART_GTPR_PSC_6 ((uint32_t)0x00000040) |
| #define | USART_GTPR_PSC_7 ((uint32_t)0x00000080) |
| #define | USART_GTPR_GT ((uint32_t)0x0000FF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) |
| #define | DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) |
| #define | DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) |
| #define | DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) |
| #define | DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) |
| #define | DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) |
| #define | DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) |
| #define | DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) |
| #define | DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) |
| #define | DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) |
| #define | DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) |
| #define | DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) |
| #define | FLASH_ACR_HLFCYA ((uint32_t)0x00000008) |
| #define | FLASH_ACR_PRFTBE ((uint32_t)0x00000010) |
| #define | FLASH_ACR_PRFTBS ((uint32_t)0x00000020) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint32_t)0x000000A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT ((uint32_t)0x00000002) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) |
| #define | FLASH_OBR_BFB2 ((uint32_t)0x00000020) |
| #define | FLASH_OBR_USER ((uint32_t)0x0000003C) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEYR_OPTKEYR2 ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_SR2_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR2_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR2_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR2_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR2_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR2_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR2_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR2_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR2_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR2_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR2_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR2 ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) |
| #define | FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) |
| #define | FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) |
| #define | FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint32_t)0x000000FF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V2 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_2V3 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_2V4 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2V5 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_2V6 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | BKP_DR1_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR2_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR3_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR4_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR5_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR6_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR7_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR8_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR9_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR10_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR11_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR12_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR13_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR14_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR15_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR16_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR17_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR18_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR19_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR20_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR21_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR22_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR23_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR24_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR25_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR26_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR27_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR28_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR29_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR30_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR31_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR32_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR33_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR34_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR35_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR36_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR37_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR38_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR39_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR40_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR41_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR42_D ((uint32_t)0x0000FFFF) |
| #define | RTC_BKP_NUMBER 42 |
| #define | BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
| #define | BKP_RTCCR_CCO ((uint32_t)0x00000080) |
| #define | BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
| #define | BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
| #define | BKP_CR_TPE ((uint32_t)0x00000001) |
| #define | BKP_CR_TPAL ((uint32_t)0x00000002) |
| #define | BKP_CSR_CTE ((uint32_t)0x00000001) |
| #define | BKP_CSR_CTI ((uint32_t)0x00000002) |
| #define | BKP_CSR_TPIE ((uint32_t)0x00000004) |
| #define | BKP_CSR_TEF ((uint32_t)0x00000100) |
| #define | BKP_CSR_TIF ((uint32_t)0x00000200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CR_PLL2ON ((uint32_t)0x04000000) |
| #define | RCC_CR_PLL2RDY ((uint32_t)0x08000000) |
| #define | RCC_CR_PLL3ON ((uint32_t)0x10000000) |
| #define | RCC_CR_PLL3RDY ((uint32_t)0x20000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x0F000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_3 ((uint32_t)0x08000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) |
| #define | RCC_CFGR_MCO_PLL3CLK_DIV2 ((uint32_t)0x09000000) |
| #define | RCC_CFGR_MCO_EXT_HSE ((uint32_t)0x0A000000) |
| #define | RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) |
| #define | RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) |
| #define | RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) |
| #define | RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) |
| #define | RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) |
| #define | RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
| #define | RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
| #define | RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) |
| #define | RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
| #define | RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
| #define | RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) |
| #define | RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) |
| #define | RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) |
| #define | RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) |
| #define | RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) |
| #define | RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) |
| #define | RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) |
| #define | RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) |
| #define | RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) |
| #define | RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) |
| #define | RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) |
| #define | RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) |
| #define | RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) |
| #define | RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) |
| #define | RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) |
| #define | RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) |
| #define | RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) |
| #define | RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) |
| #define | RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) |
| #define | RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) |
| #define | RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) |
| #define | RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) |
| #define | RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) |
| #define | RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) |
| #define | RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) |
| #define | RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) |
| #define | RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) |
| #define | RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) |
| #define | RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) |
| #define | RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) |
| #define | RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) |
| #define | RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) |
| #define | RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) |
| #define | RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) |
| #define | RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) |
| #define | RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) |
| #define | RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) |
| #define | RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) |
| #define | RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) |
| #define | RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) |
| #define | RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) |
| #define | RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) |
| #define | RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) |
| #define | RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) |
| #define | RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) |
| #define | RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) |
| #define | RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) |
| #define | RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) |
| #define | RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) |
| #define | RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) |
| #define | RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) |
| #define | RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) |
| #define | RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) |
| #define | RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) |
| #define | RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint32_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint32_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint32_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint32_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint32_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint32_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint32_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint32_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint32_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint32_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint32_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint32_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint32_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint32_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint32_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint32_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint32_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint32_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint32_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint32_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint32_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint32_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint32_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint32_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint32_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint32_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint32_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint32_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint32_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint32_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint32_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint32_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint32_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint32_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint32_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint32_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint32_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint32_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint32_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint32_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint32_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint32_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint32_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint32_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint32_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint32_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint32_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint32_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
| #define | AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
| #define | AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
| #define | AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
| #define | AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
| #define | AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PORT ((uint32_t)0x00000070) |
| #define | AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
| #define | AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
| #define | AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
| #define | AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) |
| #define | AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) |
| #define | AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) |
| #define | AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) |
| #define | AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) |
| #define | AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) |
| #define | AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) |
| #define | AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) |
| #define | SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) |
| #define | SCB_SCR_SEVONPEND ((uint32_t)0x00000010) |
| #define | SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) |
| #define | SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) |
| #define | SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) |
| #define | SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) |
| #define | SCB_CCR_STKALIGN ((uint32_t)0x00000200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint32_t)0x00000001) |
| #define | SCB_DFSR_BKPT ((uint32_t)0x00000002) |
| #define | SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) |
| #define | SCB_DFSR_VCATCH ((uint32_t)0x00000008) |
| #define | SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
| #define | ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
| #define | ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
| #define | ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
| #define | ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) |
| #define | DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) |
| #define | DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) |
| #define | TIM_CR1_CEN ((uint32_t)0x00000001) |
| #define | TIM_CR1_UDIS ((uint32_t)0x00000002) |
| #define | TIM_CR1_URS ((uint32_t)0x00000004) |
| #define | TIM_CR1_OPM ((uint32_t)0x00000008) |
| #define | TIM_CR1_DIR ((uint32_t)0x00000010) |
| #define | TIM_CR1_CMS ((uint32_t)0x00000060) |
| #define | TIM_CR1_CMS_0 ((uint32_t)0x00000020) |
| #define | TIM_CR1_CMS_1 ((uint32_t)0x00000040) |
| #define | TIM_CR1_ARPE ((uint32_t)0x00000080) |
| #define | TIM_CR1_CKD ((uint32_t)0x00000300) |
| #define | TIM_CR1_CKD_0 ((uint32_t)0x00000100) |
| #define | TIM_CR1_CKD_1 ((uint32_t)0x00000200) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00000007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint32_t)0x00000001) |
| #define | TIM_DIER_CC1IE ((uint32_t)0x00000002) |
| #define | TIM_DIER_CC2IE ((uint32_t)0x00000004) |
| #define | TIM_DIER_CC3IE ((uint32_t)0x00000008) |
| #define | TIM_DIER_CC4IE ((uint32_t)0x00000010) |
| #define | TIM_DIER_COMIE ((uint32_t)0x00000020) |
| #define | TIM_DIER_TIE ((uint32_t)0x00000040) |
| #define | TIM_DIER_BIE ((uint32_t)0x00000080) |
| #define | TIM_DIER_UDE ((uint32_t)0x00000100) |
| #define | TIM_DIER_CC1DE ((uint32_t)0x00000200) |
| #define | TIM_DIER_CC2DE ((uint32_t)0x00000400) |
| #define | TIM_DIER_CC3DE ((uint32_t)0x00000800) |
| #define | TIM_DIER_CC4DE ((uint32_t)0x00001000) |
| #define | TIM_DIER_COMDE ((uint32_t)0x00002000) |
| #define | TIM_DIER_TDE ((uint32_t)0x00004000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_EGR_UG ((uint32_t)0x00000001) |
| #define | TIM_EGR_CC1G ((uint32_t)0x00000002) |
| #define | TIM_EGR_CC2G ((uint32_t)0x00000004) |
| #define | TIM_EGR_CC3G ((uint32_t)0x00000008) |
| #define | TIM_EGR_CC4G ((uint32_t)0x00000010) |
| #define | TIM_EGR_COMG ((uint32_t)0x00000020) |
| #define | TIM_EGR_TG ((uint32_t)0x00000040) |
| #define | TIM_EGR_BG ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00000070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x00007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_PSC_PSC ((uint32_t)0x0000FFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint32_t)0x000000FF) |
| #define | TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_DCR_DBA ((uint32_t)0x0000001F) |
| #define | TIM_DCR_DBA_0 ((uint32_t)0x00000001) |
| #define | TIM_DCR_DBA_1 ((uint32_t)0x00000002) |
| #define | TIM_DCR_DBA_2 ((uint32_t)0x00000004) |
| #define | TIM_DCR_DBA_3 ((uint32_t)0x00000008) |
| #define | TIM_DCR_DBA_4 ((uint32_t)0x00000010) |
| #define | TIM_DCR_DBL ((uint32_t)0x00001F00) |
| #define | TIM_DCR_DBL_0 ((uint32_t)0x00000100) |
| #define | TIM_DCR_DBL_1 ((uint32_t)0x00000200) |
| #define | TIM_DCR_DBL_2 ((uint32_t)0x00000400) |
| #define | TIM_DCR_DBL_3 ((uint32_t)0x00000800) |
| #define | TIM_DCR_DBL_4 ((uint32_t)0x00001000) |
| #define | TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) |
| #define | RTC_CRH_SECIE ((uint32_t)0x00000001) |
| #define | RTC_CRH_ALRIE ((uint32_t)0x00000002) |
| #define | RTC_CRH_OWIE ((uint32_t)0x00000004) |
| #define | RTC_CRL_SECF ((uint32_t)0x00000001) |
| #define | RTC_CRL_ALRF ((uint32_t)0x00000002) |
| #define | RTC_CRL_OWF ((uint32_t)0x00000004) |
| #define | RTC_CRL_RSF ((uint32_t)0x00000008) |
| #define | RTC_CRL_CNF ((uint32_t)0x00000010) |
| #define | RTC_CRL_RTOFF ((uint32_t)0x00000020) |
| #define | RTC_PRLH_PRL ((uint32_t)0x0000000F) |
| #define | RTC_PRLL_PRL ((uint32_t)0x0000FFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) |
| #define | RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | IWDG_KR_KEY ((uint32_t)0x0000FFFF) |
| #define | IWDG_PR_PR ((uint32_t)0x00000007) |
| #define | IWDG_PR_PR_0 ((uint32_t)0x00000001) |
| #define | IWDG_PR_PR_1 ((uint32_t)0x00000002) |
| #define | IWDG_PR_PR_2 ((uint32_t)0x00000004) |
| #define | IWDG_RLR_RL ((uint32_t)0x00000FFF) |
| #define | IWDG_SR_PVU ((uint32_t)0x00000001) |
| #define | IWDG_SR_RVU ((uint32_t)0x00000002) |
| #define | WWDG_CR_T ((uint32_t)0x0000007F) |
| #define | WWDG_CR_T0 ((uint32_t)0x00000001) |
| #define | WWDG_CR_T1 ((uint32_t)0x00000002) |
| #define | WWDG_CR_T2 ((uint32_t)0x00000004) |
| #define | WWDG_CR_T3 ((uint32_t)0x00000008) |
| #define | WWDG_CR_T4 ((uint32_t)0x00000010) |
| #define | WWDG_CR_T5 ((uint32_t)0x00000020) |
| #define | WWDG_CR_T6 ((uint32_t)0x00000040) |
| #define | WWDG_CR_WDGA ((uint32_t)0x00000080) |
| #define | WWDG_CFR_W ((uint32_t)0x0000007F) |
| #define | WWDG_CFR_W0 ((uint32_t)0x00000001) |
| #define | WWDG_CFR_W1 ((uint32_t)0x00000002) |
| #define | WWDG_CFR_W2 ((uint32_t)0x00000004) |
| #define | WWDG_CFR_W3 ((uint32_t)0x00000008) |
| #define | WWDG_CFR_W4 ((uint32_t)0x00000010) |
| #define | WWDG_CFR_W5 ((uint32_t)0x00000020) |
| #define | WWDG_CFR_W6 ((uint32_t)0x00000040) |
| #define | WWDG_CFR_WDGTB ((uint32_t)0x00000180) |
| #define | WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) |
| #define | WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) |
| #define | WWDG_CFR_EWI ((uint32_t)0x00000200) |
| #define | WWDG_SR_EWIF ((uint32_t)0x00000001) |
| #define | SDIO_POWER_PWRCTRL ((uint32_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint32_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint32_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint32_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint32_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint32_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint32_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint32_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint32_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint32_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint32_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint32_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint32_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint32_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint32_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint32_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | CAN_MCR_INRQ ((uint32_t)0x00000001) |
| #define | CAN_MCR_SLEEP ((uint32_t)0x00000002) |
| #define | CAN_MCR_TXFP ((uint32_t)0x00000004) |
| #define | CAN_MCR_RFLM ((uint32_t)0x00000008) |
| #define | CAN_MCR_NART ((uint32_t)0x00000010) |
| #define | CAN_MCR_AWUM ((uint32_t)0x00000020) |
| #define | CAN_MCR_ABOM ((uint32_t)0x00000040) |
| #define | CAN_MCR_TTCM ((uint32_t)0x00000080) |
| #define | CAN_MCR_RESET ((uint32_t)0x00008000) |
| #define | CAN_MCR_DBF ((uint32_t)0x00010000) |
| #define | CAN_MSR_INAK ((uint32_t)0x00000001) |
| #define | CAN_MSR_SLAK ((uint32_t)0x00000002) |
| #define | CAN_MSR_ERRI ((uint32_t)0x00000004) |
| #define | CAN_MSR_WKUI ((uint32_t)0x00000008) |
| #define | CAN_MSR_SLAKI ((uint32_t)0x00000010) |
| #define | CAN_MSR_TXM ((uint32_t)0x00000100) |
| #define | CAN_MSR_RXM ((uint32_t)0x00000200) |
| #define | CAN_MSR_SAMP ((uint32_t)0x00000400) |
| #define | CAN_MSR_RX ((uint32_t)0x00000800) |
| #define | CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
| #define | CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
| #define | CAN_TSR_ALST0 ((uint32_t)0x00000004) |
| #define | CAN_TSR_TERR0 ((uint32_t)0x00000008) |
| #define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
| #define | CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
| #define | CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
| #define | CAN_TSR_ALST1 ((uint32_t)0x00000400) |
| #define | CAN_TSR_TERR1 ((uint32_t)0x00000800) |
| #define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
| #define | CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
| #define | CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
| #define | CAN_TSR_ALST2 ((uint32_t)0x00040000) |
| #define | CAN_TSR_TERR2 ((uint32_t)0x00080000) |
| #define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
| #define | CAN_TSR_CODE ((uint32_t)0x03000000) |
| #define | CAN_TSR_TME ((uint32_t)0x1C000000) |
| #define | CAN_TSR_TME0 ((uint32_t)0x04000000) |
| #define | CAN_TSR_TME1 ((uint32_t)0x08000000) |
| #define | CAN_TSR_TME2 ((uint32_t)0x10000000) |
| #define | CAN_TSR_LOW ((uint32_t)0xE0000000) |
| #define | CAN_TSR_LOW0 ((uint32_t)0x20000000) |
| #define | CAN_TSR_LOW1 ((uint32_t)0x40000000) |
| #define | CAN_TSR_LOW2 ((uint32_t)0x80000000) |
| #define | CAN_RF0R_FMP0 ((uint32_t)0x00000003) |
| #define | CAN_RF0R_FULL0 ((uint32_t)0x00000008) |
| #define | CAN_RF0R_FOVR0 ((uint32_t)0x00000010) |
| #define | CAN_RF0R_RFOM0 ((uint32_t)0x00000020) |
| #define | CAN_RF1R_FMP1 ((uint32_t)0x00000003) |
| #define | CAN_RF1R_FULL1 ((uint32_t)0x00000008) |
| #define | CAN_RF1R_FOVR1 ((uint32_t)0x00000010) |
| #define | CAN_RF1R_RFOM1 ((uint32_t)0x00000020) |
| #define | CAN_IER_TMEIE ((uint32_t)0x00000001) |
| #define | CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
| #define | CAN_IER_FFIE0 ((uint32_t)0x00000004) |
| #define | CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
| #define | CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
| #define | CAN_IER_FFIE1 ((uint32_t)0x00000020) |
| #define | CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
| #define | CAN_IER_EWGIE ((uint32_t)0x00000100) |
| #define | CAN_IER_EPVIE ((uint32_t)0x00000200) |
| #define | CAN_IER_BOFIE ((uint32_t)0x00000400) |
| #define | CAN_IER_LECIE ((uint32_t)0x00000800) |
| #define | CAN_IER_ERRIE ((uint32_t)0x00008000) |
| #define | CAN_IER_WKUIE ((uint32_t)0x00010000) |
| #define | CAN_IER_SLKIE ((uint32_t)0x00020000) |
| #define | CAN_ESR_EWGF ((uint32_t)0x00000001) |
| #define | CAN_ESR_EPVF ((uint32_t)0x00000002) |
| #define | CAN_ESR_BOFF ((uint32_t)0x00000004) |
| #define | CAN_ESR_LEC ((uint32_t)0x00000070) |
| #define | CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
| #define | CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
| #define | CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
| #define | CAN_ESR_TEC ((uint32_t)0x00FF0000) |
| #define | CAN_ESR_REC ((uint32_t)0xFF000000) |
| #define | CAN_BTR_BRP ((uint32_t)0x000003FF) |
| #define | CAN_BTR_TS1 ((uint32_t)0x000F0000) |
| #define | CAN_BTR_TS1_0 ((uint32_t)0x00010000) |
| #define | CAN_BTR_TS1_1 ((uint32_t)0x00020000) |
| #define | CAN_BTR_TS1_2 ((uint32_t)0x00040000) |
| #define | CAN_BTR_TS1_3 ((uint32_t)0x00080000) |
| #define | CAN_BTR_TS2 ((uint32_t)0x00700000) |
| #define | CAN_BTR_TS2_0 ((uint32_t)0x00100000) |
| #define | CAN_BTR_TS2_1 ((uint32_t)0x00200000) |
| #define | CAN_BTR_TS2_2 ((uint32_t)0x00400000) |
| #define | CAN_BTR_SJW ((uint32_t)0x03000000) |
| #define | CAN_BTR_SJW_0 ((uint32_t)0x01000000) |
| #define | CAN_BTR_SJW_1 ((uint32_t)0x02000000) |
| #define | CAN_BTR_LBKM ((uint32_t)0x40000000) |
| #define | CAN_BTR_SILM ((uint32_t)0x80000000) |
| #define | CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT0R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT1R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI2R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI2R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI2R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT2R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_FMR_FINIT ((uint32_t)0x00000001) |
| #define | CAN_FMR_CAN2SB ((uint32_t)0x00003F00) |
| #define | CAN_FM1R_FBM ((uint32_t)0x00003FFF) |
| #define | CAN_FM1R_FBM0 ((uint32_t)0x00000001) |
| #define | CAN_FM1R_FBM1 ((uint32_t)0x00000002) |
| #define | CAN_FM1R_FBM2 ((uint32_t)0x00000004) |
| #define | CAN_FM1R_FBM3 ((uint32_t)0x00000008) |
| #define | CAN_FM1R_FBM4 ((uint32_t)0x00000010) |
| #define | CAN_FM1R_FBM5 ((uint32_t)0x00000020) |
| #define | CAN_FM1R_FBM6 ((uint32_t)0x00000040) |
| #define | CAN_FM1R_FBM7 ((uint32_t)0x00000080) |
| #define | CAN_FM1R_FBM8 ((uint32_t)0x00000100) |
| #define | CAN_FM1R_FBM9 ((uint32_t)0x00000200) |
| #define | CAN_FM1R_FBM10 ((uint32_t)0x00000400) |
| #define | CAN_FM1R_FBM11 ((uint32_t)0x00000800) |
| #define | CAN_FM1R_FBM12 ((uint32_t)0x00001000) |
| #define | CAN_FM1R_FBM13 ((uint32_t)0x00002000) |
| #define | CAN_FM1R_FBM14 ((uint32_t)0x00004000) |
| #define | CAN_FM1R_FBM15 ((uint32_t)0x00008000) |
| #define | CAN_FM1R_FBM16 ((uint32_t)0x00010000) |
| #define | CAN_FM1R_FBM17 ((uint32_t)0x00020000) |
| #define | CAN_FM1R_FBM18 ((uint32_t)0x00040000) |
| #define | CAN_FM1R_FBM19 ((uint32_t)0x00080000) |
| #define | CAN_FM1R_FBM20 ((uint32_t)0x00100000) |
| #define | CAN_FM1R_FBM21 ((uint32_t)0x00200000) |
| #define | CAN_FM1R_FBM22 ((uint32_t)0x00400000) |
| #define | CAN_FM1R_FBM23 ((uint32_t)0x00800000) |
| #define | CAN_FM1R_FBM24 ((uint32_t)0x01000000) |
| #define | CAN_FM1R_FBM25 ((uint32_t)0x02000000) |
| #define | CAN_FM1R_FBM26 ((uint32_t)0x04000000) |
| #define | CAN_FM1R_FBM27 ((uint32_t)0x08000000) |
| #define | CAN_FS1R_FSC ((uint32_t)0x00003FFF) |
| #define | CAN_FS1R_FSC0 ((uint32_t)0x00000001) |
| #define | CAN_FS1R_FSC1 ((uint32_t)0x00000002) |
| #define | CAN_FS1R_FSC2 ((uint32_t)0x00000004) |
| #define | CAN_FS1R_FSC3 ((uint32_t)0x00000008) |
| #define | CAN_FS1R_FSC4 ((uint32_t)0x00000010) |
| #define | CAN_FS1R_FSC5 ((uint32_t)0x00000020) |
| #define | CAN_FS1R_FSC6 ((uint32_t)0x00000040) |
| #define | CAN_FS1R_FSC7 ((uint32_t)0x00000080) |
| #define | CAN_FS1R_FSC8 ((uint32_t)0x00000100) |
| #define | CAN_FS1R_FSC9 ((uint32_t)0x00000200) |
| #define | CAN_FS1R_FSC10 ((uint32_t)0x00000400) |
| #define | CAN_FS1R_FSC11 ((uint32_t)0x00000800) |
| #define | CAN_FS1R_FSC12 ((uint32_t)0x00001000) |
| #define | CAN_FS1R_FSC13 ((uint32_t)0x00002000) |
| #define | CAN_FS1R_FSC14 ((uint32_t)0x00004000) |
| #define | CAN_FS1R_FSC15 ((uint32_t)0x00008000) |
| #define | CAN_FS1R_FSC16 ((uint32_t)0x00010000) |
| #define | CAN_FS1R_FSC17 ((uint32_t)0x00020000) |
| #define | CAN_FS1R_FSC18 ((uint32_t)0x00040000) |
| #define | CAN_FS1R_FSC19 ((uint32_t)0x00080000) |
| #define | CAN_FS1R_FSC20 ((uint32_t)0x00100000) |
| #define | CAN_FS1R_FSC21 ((uint32_t)0x00200000) |
| #define | CAN_FS1R_FSC22 ((uint32_t)0x00400000) |
| #define | CAN_FS1R_FSC23 ((uint32_t)0x00800000) |
| #define | CAN_FS1R_FSC24 ((uint32_t)0x01000000) |
| #define | CAN_FS1R_FSC25 ((uint32_t)0x02000000) |
| #define | CAN_FS1R_FSC26 ((uint32_t)0x04000000) |
| #define | CAN_FS1R_FSC27 ((uint32_t)0x08000000) |
| #define | CAN_FFA1R_FFA ((uint32_t)0x00003FFF) |
| #define | CAN_FFA1R_FFA0 ((uint32_t)0x00000001) |
| #define | CAN_FFA1R_FFA1 ((uint32_t)0x00000002) |
| #define | CAN_FFA1R_FFA2 ((uint32_t)0x00000004) |
| #define | CAN_FFA1R_FFA3 ((uint32_t)0x00000008) |
| #define | CAN_FFA1R_FFA4 ((uint32_t)0x00000010) |
| #define | CAN_FFA1R_FFA5 ((uint32_t)0x00000020) |
| #define | CAN_FFA1R_FFA6 ((uint32_t)0x00000040) |
| #define | CAN_FFA1R_FFA7 ((uint32_t)0x00000080) |
| #define | CAN_FFA1R_FFA8 ((uint32_t)0x00000100) |
| #define | CAN_FFA1R_FFA9 ((uint32_t)0x00000200) |
| #define | CAN_FFA1R_FFA10 ((uint32_t)0x00000400) |
| #define | CAN_FFA1R_FFA11 ((uint32_t)0x00000800) |
| #define | CAN_FFA1R_FFA12 ((uint32_t)0x00001000) |
| #define | CAN_FFA1R_FFA13 ((uint32_t)0x00002000) |
| #define | CAN_FFA1_FFA14 ((uint32_t)0x00004000) |
| #define | CAN_FFA1_FFA15 ((uint32_t)0x00008000) |
| #define | CAN_FFA1_FFA16 ((uint32_t)0x00010000) |
| #define | CAN_FFA1_FFA17 ((uint32_t)0x00020000) |
| #define | CAN_FFA1_FFA18 ((uint32_t)0x00040000) |
| #define | CAN_FFA1_FFA19 ((uint32_t)0x00080000) |
| #define | CAN_FFA1_FFA20 ((uint32_t)0x00100000) |
| #define | CAN_FFA1_FFA21 ((uint32_t)0x00200000) |
| #define | CAN_FFA1_FFA22 ((uint32_t)0x00400000) |
| #define | CAN_FFA1_FFA23 ((uint32_t)0x00800000) |
| #define | CAN_FFA1_FFA24 ((uint32_t)0x01000000) |
| #define | CAN_FFA1_FFA25 ((uint32_t)0x02000000) |
| #define | CAN_FFA1_FFA26 ((uint32_t)0x04000000) |
| #define | CAN_FFA1_FFA27 ((uint32_t)0x08000000) |
| #define | CAN_FA1R_FACT ((uint32_t)0x00003FFF) |
| #define | CAN_FA1R_FACT0 ((uint32_t)0x00000001) |
| #define | CAN_FA1R_FACT1 ((uint32_t)0x00000002) |
| #define | CAN_FA1R_FACT2 ((uint32_t)0x00000004) |
| #define | CAN_FA1R_FACT3 ((uint32_t)0x00000008) |
| #define | CAN_FA1R_FACT4 ((uint32_t)0x00000010) |
| #define | CAN_FA1R_FACT5 ((uint32_t)0x00000020) |
| #define | CAN_FA1R_FACT6 ((uint32_t)0x00000040) |
| #define | CAN_FA1R_FACT7 ((uint32_t)0x00000080) |
| #define | CAN_FA1R_FACT8 ((uint32_t)0x00000100) |
| #define | CAN_FA1R_FACT9 ((uint32_t)0x00000200) |
| #define | CAN_FA1R_FACT10 ((uint32_t)0x00000400) |
| #define | CAN_FA1R_FACT11 ((uint32_t)0x00000800) |
| #define | CAN_FA1R_FACT12 ((uint32_t)0x00001000) |
| #define | CAN_FA1R_FACT13 ((uint32_t)0x00002000) |
| #define | CAN_FA1R_FACT14 ((uint32_t)0x00004000) |
| #define | CAN_FA1R_FACT15 ((uint32_t)0x00008000) |
| #define | CAN_FA1R_FACT16 ((uint32_t)0x00010000) |
| #define | CAN_FA1R_FACT17 ((uint32_t)0x00020000) |
| #define | CAN_FA1R_FACT18 ((uint32_t)0x00040000) |
| #define | CAN_FA1R_FACT19 ((uint32_t)0x00080000) |
| #define | CAN_FA1R_FACT20 ((uint32_t)0x00100000) |
| #define | CAN_FA1R_FACT21 ((uint32_t)0x00200000) |
| #define | CAN_FA1R_FACT22 ((uint32_t)0x00400000) |
| #define | CAN_FA1R_FACT23 ((uint32_t)0x00800000) |
| #define | CAN_FA1R_FACT24 ((uint32_t)0x01000000) |
| #define | CAN_FA1R_FACT25 ((uint32_t)0x02000000) |
| #define | CAN_FA1R_FACT26 ((uint32_t)0x04000000) |
| #define | CAN_FA1R_FACT27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F14R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F14R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F14R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F14R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F14R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F14R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F14R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F14R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F14R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F14R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F14R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F14R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F14R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F14R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F14R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F14R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F14R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F14R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F14R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F14R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F14R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F14R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F14R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F14R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F14R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F14R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F14R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F14R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F14R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F14R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F14R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F14R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F15R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F15R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F15R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F15R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F15R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F15R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F15R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F15R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F15R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F15R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F15R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F15R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F15R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F15R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F15R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F15R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F15R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F15R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F15R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F15R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F15R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F15R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F15R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F15R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F15R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F15R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F15R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F15R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F15R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F15R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F15R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F15R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F16R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F16R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F16R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F16R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F16R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F16R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F16R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F16R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F16R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F16R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F16R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F16R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F16R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F16R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F16R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F16R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F16R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F16R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F16R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F16R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F16R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F16R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F16R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F16R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F16R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F16R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F16R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F16R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F16R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F16R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F16R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F16R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F17R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F17R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F17R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F17R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F17R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F17R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F17R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F17R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F17R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F17R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F17R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F17R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F17R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F17R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F17R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F17R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F17R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F17R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F17R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F17R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F17R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F17R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F17R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F17R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F17R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F17R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F17R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F17R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F17R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F17R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F17R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F17R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F18R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F18R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F18R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F18R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F18R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F18R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F18R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F18R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F18R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F18R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F18R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F18R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F18R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F18R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F18R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F18R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F18R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F18R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F18R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F18R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F18R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F18R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F18R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F18R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F18R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F18R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F18R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F18R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F18R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F18R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F18R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F18R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F19R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F19R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F19R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F19R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F19R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F19R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F19R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F19R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F19R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F19R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F19R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F19R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F19R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F19R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F19R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F19R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F19R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F19R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F19R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F19R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F19R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F19R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F19R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F19R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F19R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F19R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F19R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F19R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F19R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F19R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F19R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F19R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F20R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F20R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F20R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F20R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F20R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F20R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F20R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F20R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F20R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F20R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F20R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F20R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F20R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F20R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F20R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F20R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F20R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F20R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F20R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F20R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F20R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F20R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F20R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F20R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F20R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F20R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F20R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F20R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F20R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F20R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F20R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F20R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F21R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F21R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F21R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F21R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F21R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F21R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F21R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F21R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F21R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F21R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F21R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F21R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F21R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F21R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F21R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F21R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F21R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F21R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F21R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F21R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F21R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F21R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F21R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F21R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F21R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F21R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F21R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F21R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F21R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F21R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F21R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F21R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F22R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F22R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F22R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F22R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F22R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F22R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F22R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F22R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F22R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F22R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F22R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F22R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F22R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F22R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F22R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F22R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F22R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F22R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F22R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F22R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F22R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F22R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F22R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F22R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F22R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F22R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F22R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F22R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F22R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F22R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F22R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F22R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F23R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F23R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F23R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F23R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F23R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F23R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F23R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F23R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F23R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F23R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F23R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F23R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F23R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F23R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F23R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F23R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F23R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F23R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F23R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F23R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F23R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F23R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F23R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F23R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F23R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F23R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F23R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F23R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F23R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F23R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F23R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F23R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F24R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F24R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F24R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F24R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F24R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F24R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F24R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F24R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F24R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F24R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F24R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F24R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F24R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F24R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F24R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F24R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F24R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F24R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F24R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F24R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F24R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F24R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F24R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F24R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F24R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F24R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F24R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F24R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F24R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F24R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F24R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F24R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F25R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F25R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F25R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F25R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F25R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F25R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F25R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F25R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F25R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F25R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F25R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F25R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F25R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F25R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F25R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F25R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F25R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F25R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F25R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F25R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F25R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F25R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F25R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F25R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F25R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F25R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F25R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F25R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F25R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F25R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F25R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F25R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F26R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F26R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F26R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F26R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F26R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F26R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F26R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F26R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F26R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F26R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F26R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F26R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F26R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F26R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F26R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F26R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F26R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F26R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F26R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F26R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F26R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F26R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F26R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F26R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F26R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F26R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F26R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F26R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F26R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F26R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F26R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F26R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F27R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F27R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F27R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F27R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F27R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F27R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F27R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F27R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F27R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F27R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F27R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F27R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F27R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F27R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F27R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F27R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F27R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F27R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F27R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F27R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F27R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F27R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F27R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F27R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F27R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F27R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F27R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F27R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F27R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F27R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F27R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F27R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F0R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F14R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F14R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F14R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F14R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F14R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F14R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F14R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F14R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F14R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F14R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F14R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F14R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F14R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F14R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F14R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F14R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F14R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F14R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F14R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F14R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F14R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F14R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F14R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F14R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F14R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F14R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F14R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F14R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F14R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F14R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F14R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F14R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F15R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F15R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F15R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F15R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F15R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F15R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F15R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F15R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F15R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F15R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F15R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F15R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F15R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F15R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F15R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F15R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F15R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F15R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F15R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F15R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F15R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F15R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F15R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F15R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F15R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F15R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F15R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F15R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F15R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F15R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F15R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F15R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F16R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F16R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F16R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F16R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F16R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F16R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F16R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F16R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F16R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F16R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F16R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F16R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F16R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F16R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F16R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F16R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F16R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F16R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F16R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F16R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F16R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F16R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F16R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F16R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F16R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F16R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F16R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F16R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F16R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F16R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F16R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F16R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F17R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F17R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F17R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F17R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F17R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F17R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F17R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F17R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F17R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F17R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F17R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F17R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F17R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F17R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F17R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F17R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F17R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F17R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F17R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F17R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F17R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F17R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F17R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F17R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F17R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F17R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F17R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F17R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F17R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F17R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F17R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F17R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F18R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F18R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F18R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F18R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F18R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F18R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F18R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F18R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F18R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F18R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F18R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F18R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F18R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F18R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F18R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F18R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F18R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F18R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F18R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F18R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F18R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F18R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F18R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F18R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F18R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F18R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F18R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F18R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F18R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F18R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F18R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F18R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F19R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F19R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F19R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F19R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F19R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F19R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F19R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F19R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F19R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F19R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F19R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F19R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F19R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F19R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F19R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F19R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F19R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F19R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F19R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F19R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F19R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F19R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F19R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F19R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F19R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F19R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F19R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F19R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F19R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F19R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F19R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F19R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F20R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F20R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F20R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F20R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F20R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F20R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F20R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F20R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F20R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F20R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F20R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F20R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F20R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F20R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F20R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F20R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F20R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F20R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F20R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F20R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F20R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F20R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F20R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F20R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F20R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F20R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F20R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F20R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F20R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F20R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F20R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F20R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F21R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F21R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F21R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F21R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F21R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F21R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F21R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F21R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F21R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F21R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F21R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F21R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F21R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F21R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F21R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F21R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F21R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F21R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F21R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F21R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F21R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F21R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F21R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F21R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F21R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F21R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F21R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F21R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F21R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F21R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F21R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F21R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F22R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F22R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F22R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F22R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F22R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F22R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F22R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F22R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F22R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F22R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F22R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F22R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F22R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F22R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F22R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F22R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F22R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F22R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F22R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F22R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F22R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F22R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F22R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F22R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F22R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F22R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F22R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F22R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F22R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F22R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F22R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F22R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F23R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F23R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F23R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F23R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F23R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F23R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F23R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F23R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F23R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F23R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F23R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F23R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F23R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F23R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F23R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F23R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F23R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F23R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F23R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F23R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F23R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F23R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F23R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F23R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F23R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F23R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F23R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F23R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F23R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F23R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F23R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F23R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F24R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F24R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F24R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F24R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F24R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F24R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F24R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F24R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F24R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F24R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F24R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F24R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F24R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F24R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F24R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F24R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F24R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F24R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F24R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F24R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F24R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F24R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F24R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F24R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F24R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F24R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F24R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F24R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F24R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F24R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F24R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F24R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F25R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F25R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F25R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F25R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F25R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F25R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F25R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F25R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F25R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F25R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F25R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F25R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F25R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F25R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F25R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F25R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F25R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F25R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F25R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F25R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F25R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F25R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F25R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F25R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F25R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F25R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F25R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F25R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F25R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F25R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F25R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F25R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F26R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F26R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F26R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F26R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F26R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F26R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F26R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F26R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F26R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F26R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F26R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F26R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F26R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F26R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F26R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F26R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F26R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F26R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F26R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F26R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F26R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F26R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F26R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F26R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F26R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F26R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F26R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F26R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F26R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F26R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F26R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F26R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F27R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F27R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F27R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F27R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F27R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F27R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F27R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F27R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F27R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F27R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F27R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F27R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F27R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F27R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F27R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F27R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F27R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F27R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F27R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F27R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F27R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F27R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F27R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F27R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F27R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F27R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F27R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F27R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F27R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F27R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F27R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F27R2_FB31 ((uint32_t)0x80000000) |
| #define | SPI_CR1_CPHA ((uint32_t)0x00000001) |
| #define | SPI_CR1_CPOL ((uint32_t)0x00000002) |
| #define | SPI_CR1_MSTR ((uint32_t)0x00000004) |
| #define | SPI_CR1_BR ((uint32_t)0x00000038) |
| #define | SPI_CR1_BR_0 ((uint32_t)0x00000008) |
| #define | SPI_CR1_BR_1 ((uint32_t)0x00000010) |
| #define | SPI_CR1_BR_2 ((uint32_t)0x00000020) |
| #define | SPI_CR1_SPE ((uint32_t)0x00000040) |
| #define | SPI_CR1_LSBFIRST ((uint32_t)0x00000080) |
| #define | SPI_CR1_SSI ((uint32_t)0x00000100) |
| #define | SPI_CR1_SSM ((uint32_t)0x00000200) |
| #define | SPI_CR1_RXONLY ((uint32_t)0x00000400) |
| #define | SPI_CR1_DFF ((uint32_t)0x00000800) |
| #define | SPI_CR1_CRCNEXT ((uint32_t)0x00001000) |
| #define | SPI_CR1_CRCEN ((uint32_t)0x00002000) |
| #define | SPI_CR1_BIDIOE ((uint32_t)0x00004000) |
| #define | SPI_CR1_BIDIMODE ((uint32_t)0x00008000) |
| #define | SPI_CR2_RXDMAEN ((uint32_t)0x00000001) |
| #define | SPI_CR2_TXDMAEN ((uint32_t)0x00000002) |
| #define | SPI_CR2_SSOE ((uint32_t)0x00000004) |
| #define | SPI_CR2_ERRIE ((uint32_t)0x00000020) |
| #define | SPI_CR2_RXNEIE ((uint32_t)0x00000040) |
| #define | SPI_CR2_TXEIE ((uint32_t)0x00000080) |
| #define | SPI_SR_RXNE ((uint32_t)0x00000001) |
| #define | SPI_SR_TXE ((uint32_t)0x00000002) |
| #define | SPI_SR_CHSIDE ((uint32_t)0x00000004) |
| #define | SPI_SR_UDR ((uint32_t)0x00000008) |
| #define | SPI_SR_CRCERR ((uint32_t)0x00000010) |
| #define | SPI_SR_MODF ((uint32_t)0x00000020) |
| #define | SPI_SR_OVR ((uint32_t)0x00000040) |
| #define | SPI_SR_BSY ((uint32_t)0x00000080) |
| #define | SPI_DR_DR ((uint32_t)0x0000FFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) |
| #define | SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) |
| #define | SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) |
| #define | SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) |
| #define | SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) |
| #define | SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) |
| #define | SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) |
| #define | SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) |
| #define | SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) |
| #define | SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) |
| #define | SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) |
| #define | SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) |
| #define | SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) |
| #define | SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) |
| #define | SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) |
| #define | SPI_I2SPR_ODD ((uint32_t)0x00000100) |
| #define | SPI_I2SPR_MCKOE ((uint32_t)0x00000200) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_SMBUS ((uint32_t)0x00000002) |
| #define | I2C_CR1_SMBTYPE ((uint32_t)0x00000008) |
| #define | I2C_CR1_ENARP ((uint32_t)0x00000010) |
| #define | I2C_CR1_ENPEC ((uint32_t)0x00000020) |
| #define | I2C_CR1_ENGC ((uint32_t)0x00000040) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) |
| #define | I2C_CR1_START ((uint32_t)0x00000100) |
| #define | I2C_CR1_STOP ((uint32_t)0x00000200) |
| #define | I2C_CR1_ACK ((uint32_t)0x00000400) |
| #define | I2C_CR1_POS ((uint32_t)0x00000800) |
| #define | I2C_CR1_PEC ((uint32_t)0x00001000) |
| #define | I2C_CR1_ALERT ((uint32_t)0x00002000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00008000) |
| #define | I2C_CR2_FREQ ((uint32_t)0x0000003F) |
| #define | I2C_CR2_FREQ_0 ((uint32_t)0x00000001) |
| #define | I2C_CR2_FREQ_1 ((uint32_t)0x00000002) |
| #define | I2C_CR2_FREQ_2 ((uint32_t)0x00000004) |
| #define | I2C_CR2_FREQ_3 ((uint32_t)0x00000008) |
| #define | I2C_CR2_FREQ_4 ((uint32_t)0x00000010) |
| #define | I2C_CR2_FREQ_5 ((uint32_t)0x00000020) |
| #define | I2C_CR2_ITERREN ((uint32_t)0x00000100) |
| #define | I2C_CR2_ITEVTEN ((uint32_t)0x00000200) |
| #define | I2C_CR2_ITBUFEN ((uint32_t)0x00000400) |
| #define | I2C_CR2_DMAEN ((uint32_t)0x00000800) |
| #define | I2C_CR2_LAST ((uint32_t)0x00001000) |
| #define | I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) |
| #define | I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) |
| #define | I2C_OAR1_ADD0 ((uint32_t)0x00000001) |
| #define | I2C_OAR1_ADD1 ((uint32_t)0x00000002) |
| #define | I2C_OAR1_ADD2 ((uint32_t)0x00000004) |
| #define | I2C_OAR1_ADD3 ((uint32_t)0x00000008) |
| #define | I2C_OAR1_ADD4 ((uint32_t)0x00000010) |
| #define | I2C_OAR1_ADD5 ((uint32_t)0x00000020) |
| #define | I2C_OAR1_ADD6 ((uint32_t)0x00000040) |
| #define | I2C_OAR1_ADD7 ((uint32_t)0x00000080) |
| #define | I2C_OAR1_ADD8 ((uint32_t)0x00000100) |
| #define | I2C_OAR1_ADD9 ((uint32_t)0x00000200) |
| #define | I2C_OAR1_ADDMODE ((uint32_t)0x00008000) |
| #define | I2C_OAR2_ENDUAL ((uint32_t)0x00000001) |
| #define | I2C_OAR2_ADD2 ((uint32_t)0x000000FE) |
| #define | I2C_SR1_SB ((uint32_t)0x00000001) |
| #define | I2C_SR1_ADDR ((uint32_t)0x00000002) |
| #define | I2C_SR1_BTF ((uint32_t)0x00000004) |
| #define | I2C_SR1_ADD10 ((uint32_t)0x00000008) |
| #define | I2C_SR1_STOPF ((uint32_t)0x00000010) |
| #define | I2C_SR1_RXNE ((uint32_t)0x00000040) |
| #define | I2C_SR1_TXE ((uint32_t)0x00000080) |
| #define | I2C_SR1_BERR ((uint32_t)0x00000100) |
| #define | I2C_SR1_ARLO ((uint32_t)0x00000200) |
| #define | I2C_SR1_AF ((uint32_t)0x00000400) |
| #define | I2C_SR1_OVR ((uint32_t)0x00000800) |
| #define | I2C_SR1_PECERR ((uint32_t)0x00001000) |
| #define | I2C_SR1_TIMEOUT ((uint32_t)0x00004000) |
| #define | I2C_SR1_SMBALERT ((uint32_t)0x00008000) |
| #define | I2C_SR2_MSL ((uint32_t)0x00000001) |
| #define | I2C_SR2_BUSY ((uint32_t)0x00000002) |
| #define | I2C_SR2_TRA ((uint32_t)0x00000004) |
| #define | I2C_SR2_GENCALL ((uint32_t)0x00000010) |
| #define | I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) |
| #define | I2C_SR2_SMBHOST ((uint32_t)0x00000040) |
| #define | I2C_SR2_DUALF ((uint32_t)0x00000080) |
| #define | I2C_SR2_PEC ((uint32_t)0x0000FF00) |
| #define | I2C_CCR_CCR ((uint32_t)0x00000FFF) |
| #define | I2C_CCR_DUTY ((uint32_t)0x00004000) |
| #define | I2C_CCR_FS ((uint32_t)0x00008000) |
| #define | I2C_TRISE_TRISE ((uint32_t)0x0000003F) |
| #define | USART_SR_PE ((uint32_t)0x00000001) |
| #define | USART_SR_FE ((uint32_t)0x00000002) |
| #define | USART_SR_NE ((uint32_t)0x00000004) |
| #define | USART_SR_ORE ((uint32_t)0x00000008) |
| #define | USART_SR_IDLE ((uint32_t)0x00000010) |
| #define | USART_SR_RXNE ((uint32_t)0x00000020) |
| #define | USART_SR_TC ((uint32_t)0x00000040) |
| #define | USART_SR_TXE ((uint32_t)0x00000080) |
| #define | USART_SR_LBD ((uint32_t)0x00000100) |
| #define | USART_SR_CTS ((uint32_t)0x00000200) |
| #define | USART_DR_DR ((uint32_t)0x000001FF) |
| #define | USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) |
| #define | USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) |
| #define | USART_CR1_SBK ((uint32_t)0x00000001) |
| #define | USART_CR1_RWU ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_UE ((uint32_t)0x00002000) |
| #define | USART_CR2_ADD ((uint32_t)0x0000000F) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_GTPR_PSC ((uint32_t)0x000000FF) |
| #define | USART_GTPR_PSC_0 ((uint32_t)0x00000001) |
| #define | USART_GTPR_PSC_1 ((uint32_t)0x00000002) |
| #define | USART_GTPR_PSC_2 ((uint32_t)0x00000004) |
| #define | USART_GTPR_PSC_3 ((uint32_t)0x00000008) |
| #define | USART_GTPR_PSC_4 ((uint32_t)0x00000010) |
| #define | USART_GTPR_PSC_5 ((uint32_t)0x00000020) |
| #define | USART_GTPR_PSC_6 ((uint32_t)0x00000040) |
| #define | USART_GTPR_PSC_7 ((uint32_t)0x00000080) |
| #define | USART_GTPR_GT ((uint32_t)0x0000FF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) |
| #define | DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) |
| #define | DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) |
| #define | DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) |
| #define | DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) |
| #define | DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) |
| #define | DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) |
| #define | DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) |
| #define | DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) |
| #define | FLASH_ACR_HLFCYA ((uint32_t)0x00000008) |
| #define | FLASH_ACR_PRFTBE ((uint32_t)0x00000010) |
| #define | FLASH_ACR_PRFTBS ((uint32_t)0x00000020) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint32_t)0x000000A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT ((uint32_t)0x00000002) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) |
| #define | FLASH_OBR_USER ((uint32_t)0x0000001C) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) |
| #define | FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) |
| #define | FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) |
| #define | FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) |
| #define | USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) |
| #define | USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) |
| #define | USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) |
| #define | USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) |
| #define | USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) |
| #define | USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) |
| #define | USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) |
| #define | USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) |
| #define | USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) |
| #define | USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) |
| #define | USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) |
| #define | USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) |
| #define | USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) |
| #define | USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) |
| #define | USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) |
| #define | USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) |
| #define | USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) |
| #define | USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) |
| #define | USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) |
| #define | USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) |
| #define | USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) |
| #define | USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) |
| #define | USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) |
| #define | USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) |
| #define | USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) |
| #define | USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) |
| #define | USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) |
| #define | USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) |
| #define | USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) |
| #define | USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) |
| #define | USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) |
| #define | USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) |
| #define | USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) |
| #define | USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) |
| #define | USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) |
| #define | USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) |
| #define | USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) |
| #define | USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) |
| #define | USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) |
| #define | USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) |
| #define | USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) |
| #define | USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) |
| #define | USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) |
| #define | USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) |
| #define | USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) |
| #define | USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) |
| #define | USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) |
| #define | USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) |
| #define | USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) |
| #define | USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) |
| #define | USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) |
| #define | USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) |
| #define | USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) |
| #define | USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) |
| #define | USB_OTG_DSTS_EERR ((uint32_t)0x00000008) |
| #define | USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) |
| #define | USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) |
| #define | USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) |
| #define | USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) |
| #define | USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) |
| #define | USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) |
| #define | USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) |
| #define | USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) |
| #define | USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) |
| #define | USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) |
| #define | USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) |
| #define | USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) |
| #define | USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) |
| #define | USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) |
| #define | USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) |
| #define | USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) |
| #define | USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) |
| #define | USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) |
| #define | USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) |
| #define | USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) |
| #define | USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) |
| #define | USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) |
| #define | USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) |
| #define | USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) |
| #define | USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) |
| #define | USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) |
| #define | USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) |
| #define | USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) |
| #define | USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) |
| #define | USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) |
| #define | USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) |
| #define | USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) |
| #define | USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) |
| #define | USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) |
| #define | USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) |
| #define | USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) |
| #define | USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) |
| #define | USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) |
| #define | USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) |
| #define | USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) |
| #define | USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) |
| #define | USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) |
| #define | USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) |
| #define | USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) |
| #define | USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) |
| #define | USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) |
| #define | USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) |
| #define | USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) |
| #define | USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) |
| #define | USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) |
| #define | USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) |
| #define | USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) |
| #define | USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) |
| #define | USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) |
| #define | USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) |
| #define | USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) |
| #define | USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) |
| #define | USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) |
| #define | USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) |
| #define | USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) |
| #define | USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) |
| #define | USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) |
| #define | USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) |
| #define | USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) |
| #define | USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) |
| #define | USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) |
| #define | USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) |
| #define | USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) |
| #define | USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) |
| #define | USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) |
| #define | USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) |
| #define | USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) |
| #define | USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) |
| #define | USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) |
| #define | USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) |
| #define | USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) |
| #define | USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) |
| #define | USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) |
| #define | USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) |
| #define | USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) |
| #define | USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) |
| #define | USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) |
| #define | USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) |
| #define | USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) |
| #define | USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) |
| #define | USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) |
| #define | USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) |
| #define | USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) |
| #define | USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) |
| #define | USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) |
| #define | USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) |
| #define | USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) |
| #define | USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) |
| #define | USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) |
| #define | USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) |
| #define | USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) |
| #define | USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) |
| #define | USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) |
| #define | USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) |
| #define | USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) |
| #define | USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) |
| #define | USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) |
| #define | USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) |
| #define | USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) |
| #define | USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) |
| #define | USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) |
| #define | USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) |
| #define | USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) |
| #define | USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) |
| #define | USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) |
| #define | USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) |
| #define | USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) |
| #define | USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) |
| #define | USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) |
| #define | USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) |
| #define | USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) |
| #define | USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) |
| #define | USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) |
| #define | USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) |
| #define | USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) |
| #define | USB_OTG_CHNUM ((uint32_t)0x0000000F) |
| #define | USB_OTG_CHNUM ((uint32_t)0x0000000F) |
| #define | USB_OTG_CHNUM_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_CHNUM_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_CHNUM_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_CHNUM_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_CHNUM_2 ((uint32_t)0x00000004) |
| #define | USB_OTG_CHNUM_2 ((uint32_t)0x00000004) |
| #define | USB_OTG_CHNUM_3 ((uint32_t)0x00000008) |
| #define | USB_OTG_CHNUM_3 ((uint32_t)0x00000008) |
| #define | USB_OTG_BCNT ((uint32_t)0x00007FF0) |
| #define | USB_OTG_BCNT ((uint32_t)0x00007FF0) |
| #define | USB_OTG_DPID ((uint32_t)0x00018000) |
| #define | USB_OTG_DPID ((uint32_t)0x00018000) |
| #define | USB_OTG_DPID_0 ((uint32_t)0x00008000) |
| #define | USB_OTG_DPID_0 ((uint32_t)0x00008000) |
| #define | USB_OTG_DPID_1 ((uint32_t)0x00010000) |
| #define | USB_OTG_DPID_1 ((uint32_t)0x00010000) |
| #define | USB_OTG_PKTSTS ((uint32_t)0x001E0000) |
| #define | USB_OTG_PKTSTS ((uint32_t)0x001E0000) |
| #define | USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) |
| #define | USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) |
| #define | USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) |
| #define | USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) |
| #define | USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) |
| #define | USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) |
| #define | USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) |
| #define | USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) |
| #define | USB_OTG_EPNUM ((uint32_t)0x0000000F) |
| #define | USB_OTG_EPNUM ((uint32_t)0x0000000F) |
| #define | USB_OTG_EPNUM_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_EPNUM_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_EPNUM_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_EPNUM_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_EPNUM_2 ((uint32_t)0x00000004) |
| #define | USB_OTG_EPNUM_2 ((uint32_t)0x00000004) |
| #define | USB_OTG_EPNUM_3 ((uint32_t)0x00000008) |
| #define | USB_OTG_EPNUM_3 ((uint32_t)0x00000008) |
| #define | USB_OTG_FRMNUM ((uint32_t)0x01E00000) |
| #define | USB_OTG_FRMNUM ((uint32_t)0x01E00000) |
| #define | USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) |
| #define | USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) |
| #define | USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) |
| #define | USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) |
| #define | USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) |
| #define | USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) |
| #define | USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) |
| #define | USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) |
| #define | USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) |
| #define | USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_TX0FD ((uint32_t)0xFFFF0000) |
| #define | USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) |
| #define | USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) |
| #define | USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) |
| #define | USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) |
| #define | USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) |
| #define | USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) |
| #define | USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) |
| #define | USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) |
| #define | USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) |
| #define | USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) |
| #define | USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) |
| #define | USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) |
| #define | USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) |
| #define | USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) |
| #define | USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) |
| #define | USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) |
| #define | USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) |
| #define | USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) |
| #define | USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) |
| #define | USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) |
| #define | USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) |
| #define | USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) |
| #define | USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) |
| #define | USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) |
| #define | USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) |
| #define | USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) |
| #define | USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) |
| #define | USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) |
| #define | USB_OTG_HPRT_PENA ((uint32_t)0x00000004) |
| #define | USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) |
| #define | USB_OTG_HPRT_POCA ((uint32_t)0x00000010) |
| #define | USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) |
| #define | USB_OTG_HPRT_PRES ((uint32_t)0x00000040) |
| #define | USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) |
| #define | USB_OTG_HPRT_PRST ((uint32_t)0x00000100) |
| #define | USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) |
| #define | USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) |
| #define | USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) |
| #define | USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) |
| #define | USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) |
| #define | USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) |
| #define | USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) |
| #define | USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) |
| #define | USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) |
| #define | USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) |
| #define | USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) |
| #define | USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) |
| #define | USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) |
| #define | USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) |
| #define | USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) |
| #define | USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) |
| #define | USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) |
| #define | USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) |
| #define | USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) |
| #define | USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) |
| #define | USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) |
| #define | USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) |
| #define | USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) |
| #define | USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) |
| #define | USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) |
| #define | USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) |
| #define | USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) |
| #define | USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) |
| #define | USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) |
| #define | USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) |
| #define | USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) |
| #define | USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) |
| #define | USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) |
| #define | USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) |
| #define | USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) |
| #define | USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) |
| #define | USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) |
| #define | USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) |
| #define | USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) |
| #define | USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) |
| #define | USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) |
| #define | USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) |
| #define | USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) |
| #define | USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) |
| #define | USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) |
| #define | USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) |
| #define | USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) |
| #define | USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) |
| #define | USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) |
| #define | USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) |
| #define | USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) |
| #define | USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) |
| #define | USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) |
| #define | USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) |
| #define | USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) |
| #define | USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) |
| #define | USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) |
| #define | USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) |
| #define | USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) |
| #define | USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) |
| #define | USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) |
| #define | USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) |
| #define | USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) |
| #define | USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) |
| #define | USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) |
| #define | USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) |
| #define | USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) |
| #define | USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) |
| #define | USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) |
| #define | USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) |
| #define | USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) |
| #define | USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) |
| #define | USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) |
| #define | USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) |
| #define | USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) |
| #define | USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) |
| #define | USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) |
| #define | USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) |
| #define | USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) |
| #define | USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) |
| #define | USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) |
| #define | USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) |
| #define | USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) |
| #define | USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) |
| #define | USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) |
| #define | USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) |
| #define | USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) |
| #define | USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) |
| #define | USB_OTG_HCINT_CHH ((uint32_t)0x00000002) |
| #define | USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) |
| #define | USB_OTG_HCINT_STALL ((uint32_t)0x00000008) |
| #define | USB_OTG_HCINT_NAK ((uint32_t)0x00000010) |
| #define | USB_OTG_HCINT_ACK ((uint32_t)0x00000020) |
| #define | USB_OTG_HCINT_NYET ((uint32_t)0x00000040) |
| #define | USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) |
| #define | USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) |
| #define | USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) |
| #define | USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) |
| #define | USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) |
| #define | USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) |
| #define | USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) |
| #define | USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) |
| #define | USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) |
| #define | USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) |
| #define | USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) |
| #define | USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) |
| #define | USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) |
| #define | USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) |
| #define | USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) |
| #define | USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) |
| #define | USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) |
| #define | USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) |
| #define | USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) |
| #define | USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) |
| #define | USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) |
| #define | USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) |
| #define | USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) |
| #define | USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) |
| #define | USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) |
| #define | USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) |
| #define | USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) |
| #define | USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) |
| #define | USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) |
| #define | USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) |
| #define | USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) |
| #define | USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) |
| #define | USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) |
| #define | USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) |
| #define | USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) |
| #define | USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) |
| #define | USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) |
| #define | USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) |
| #define | USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) |
| #define | USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) |
| #define | USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) |
| #define | USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) |
| #define | USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) |
| #define | USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) |
| #define | USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) |
| #define | USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) |
| #define | USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) |
| #define | USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) |
| #define | USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) |
| #define | USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) |
| #define | USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) |
| #define | USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) |
| #define | USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) |
| #define | USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) |
| #define | USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) |
| #define | USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) |
| #define | USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) |
| #define | USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) |
| #define | USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) |
| #define | USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) |
| #define | USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) |
| #define | USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) |
| #define | USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) |
| #define | USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) |
| #define | USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) |
| #define | USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint32_t)0x000000FF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V2 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_2V3 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_2V4 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2V5 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_2V6 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | BKP_DR1_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR2_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR3_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR4_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR5_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR6_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR7_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR8_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR9_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR10_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR11_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR12_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR13_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR14_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR15_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR16_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR17_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR18_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR19_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR20_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR21_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR22_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR23_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR24_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR25_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR26_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR27_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR28_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR29_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR30_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR31_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR32_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR33_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR34_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR35_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR36_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR37_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR38_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR39_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR40_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR41_D ((uint32_t)0x0000FFFF) |
| #define | BKP_DR42_D ((uint32_t)0x0000FFFF) |
| #define | RTC_BKP_NUMBER 42 |
| #define | BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
| #define | BKP_RTCCR_CCO ((uint32_t)0x00000080) |
| #define | BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
| #define | BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
| #define | BKP_CR_TPE ((uint32_t)0x00000001) |
| #define | BKP_CR_TPAL ((uint32_t)0x00000002) |
| #define | BKP_CSR_CTE ((uint32_t)0x00000001) |
| #define | BKP_CSR_CTI ((uint32_t)0x00000002) |
| #define | BKP_CSR_TPIE ((uint32_t)0x00000004) |
| #define | BKP_CSR_TEF ((uint32_t)0x00000100) |
| #define | BKP_CSR_TIF ((uint32_t)0x00000200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CR_PLL2ON ((uint32_t)0x04000000) |
| #define | RCC_CR_PLL2RDY ((uint32_t)0x08000000) |
| #define | RCC_CR_PLL3ON ((uint32_t)0x10000000) |
| #define | RCC_CR_PLL3RDY ((uint32_t)0x20000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x0F000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_3 ((uint32_t)0x08000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) |
| #define | RCC_CFGR_MCO_PLL3CLK_DIV2 ((uint32_t)0x09000000) |
| #define | RCC_CFGR_MCO_EXT_HSE ((uint32_t)0x0A000000) |
| #define | RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) |
| #define | RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) |
| #define | RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) |
| #define | RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) |
| #define | RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) |
| #define | RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
| #define | RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
| #define | RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) |
| #define | RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) |
| #define | RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) |
| #define | RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) |
| #define | RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
| #define | RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
| #define | RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) |
| #define | RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) |
| #define | RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) |
| #define | RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) |
| #define | RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) |
| #define | RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) |
| #define | RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) |
| #define | RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) |
| #define | RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) |
| #define | RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) |
| #define | RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) |
| #define | RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) |
| #define | RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) |
| #define | RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) |
| #define | RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) |
| #define | RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) |
| #define | RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) |
| #define | RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) |
| #define | RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) |
| #define | RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) |
| #define | RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) |
| #define | RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) |
| #define | RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) |
| #define | RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) |
| #define | RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) |
| #define | RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) |
| #define | RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) |
| #define | RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) |
| #define | RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) |
| #define | RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) |
| #define | RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) |
| #define | RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) |
| #define | RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) |
| #define | RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) |
| #define | RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) |
| #define | RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) |
| #define | RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) |
| #define | RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) |
| #define | RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) |
| #define | RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) |
| #define | RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) |
| #define | RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) |
| #define | RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) |
| #define | RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) |
| #define | RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) |
| #define | RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) |
| #define | RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) |
| #define | RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) |
| #define | RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) |
| #define | RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) |
| #define | RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) |
| #define | RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) |
| #define | RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) |
| #define | RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) |
| #define | RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) |
| #define | RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint32_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint32_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint32_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint32_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint32_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint32_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint32_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint32_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint32_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint32_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint32_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint32_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint32_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint32_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint32_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint32_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint32_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint32_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint32_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint32_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint32_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint32_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint32_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint32_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint32_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint32_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint32_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint32_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint32_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint32_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint32_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint32_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint32_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint32_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint32_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint32_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint32_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint32_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint32_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint32_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint32_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint32_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint32_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint32_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint32_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint32_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint32_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint32_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
| #define | AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
| #define | AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
| #define | AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
| #define | AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
| #define | AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
| #define | AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
| #define | AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
| #define | AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
| #define | AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
| #define | AFIO_EVCR_PORT ((uint32_t)0x00000070) |
| #define | AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
| #define | AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
| #define | AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
| #define | AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
| #define | AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
| #define | AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
| #define | AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
| #define | AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) |
| #define | AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) |
| #define | AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) |
| #define | AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) |
| #define | AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) |
| #define | AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) |
| #define | AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) |
| #define | AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) |
| #define | SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) |
| #define | SCB_SCR_SEVONPEND ((uint32_t)0x00000010) |
| #define | SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) |
| #define | SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) |
| #define | SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) |
| #define | SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) |
| #define | SCB_CCR_STKALIGN ((uint32_t)0x00000200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint32_t)0x00000001) |
| #define | SCB_DFSR_BKPT ((uint32_t)0x00000002) |
| #define | SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) |
| #define | SCB_DFSR_VCATCH ((uint32_t)0x00000008) |
| #define | SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
| #define | ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
| #define | ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
| #define | ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
| #define | ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) |
| #define | DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) |
| #define | DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) |
| #define | TIM_CR1_CEN ((uint32_t)0x00000001) |
| #define | TIM_CR1_UDIS ((uint32_t)0x00000002) |
| #define | TIM_CR1_URS ((uint32_t)0x00000004) |
| #define | TIM_CR1_OPM ((uint32_t)0x00000008) |
| #define | TIM_CR1_DIR ((uint32_t)0x00000010) |
| #define | TIM_CR1_CMS ((uint32_t)0x00000060) |
| #define | TIM_CR1_CMS_0 ((uint32_t)0x00000020) |
| #define | TIM_CR1_CMS_1 ((uint32_t)0x00000040) |
| #define | TIM_CR1_ARPE ((uint32_t)0x00000080) |
| #define | TIM_CR1_CKD ((uint32_t)0x00000300) |
| #define | TIM_CR1_CKD_0 ((uint32_t)0x00000100) |
| #define | TIM_CR1_CKD_1 ((uint32_t)0x00000200) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00000007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint32_t)0x00000001) |
| #define | TIM_DIER_CC1IE ((uint32_t)0x00000002) |
| #define | TIM_DIER_CC2IE ((uint32_t)0x00000004) |
| #define | TIM_DIER_CC3IE ((uint32_t)0x00000008) |
| #define | TIM_DIER_CC4IE ((uint32_t)0x00000010) |
| #define | TIM_DIER_COMIE ((uint32_t)0x00000020) |
| #define | TIM_DIER_TIE ((uint32_t)0x00000040) |
| #define | TIM_DIER_BIE ((uint32_t)0x00000080) |
| #define | TIM_DIER_UDE ((uint32_t)0x00000100) |
| #define | TIM_DIER_CC1DE ((uint32_t)0x00000200) |
| #define | TIM_DIER_CC2DE ((uint32_t)0x00000400) |
| #define | TIM_DIER_CC3DE ((uint32_t)0x00000800) |
| #define | TIM_DIER_CC4DE ((uint32_t)0x00001000) |
| #define | TIM_DIER_COMDE ((uint32_t)0x00002000) |
| #define | TIM_DIER_TDE ((uint32_t)0x00004000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_EGR_UG ((uint32_t)0x00000001) |
| #define | TIM_EGR_CC1G ((uint32_t)0x00000002) |
| #define | TIM_EGR_CC2G ((uint32_t)0x00000004) |
| #define | TIM_EGR_CC3G ((uint32_t)0x00000008) |
| #define | TIM_EGR_CC4G ((uint32_t)0x00000010) |
| #define | TIM_EGR_COMG ((uint32_t)0x00000020) |
| #define | TIM_EGR_TG ((uint32_t)0x00000040) |
| #define | TIM_EGR_BG ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00000070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x00007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_PSC_PSC ((uint32_t)0x0000FFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint32_t)0x000000FF) |
| #define | TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) |
| #define | TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_DCR_DBA ((uint32_t)0x0000001F) |
| #define | TIM_DCR_DBA_0 ((uint32_t)0x00000001) |
| #define | TIM_DCR_DBA_1 ((uint32_t)0x00000002) |
| #define | TIM_DCR_DBA_2 ((uint32_t)0x00000004) |
| #define | TIM_DCR_DBA_3 ((uint32_t)0x00000008) |
| #define | TIM_DCR_DBA_4 ((uint32_t)0x00000010) |
| #define | TIM_DCR_DBL ((uint32_t)0x00001F00) |
| #define | TIM_DCR_DBL_0 ((uint32_t)0x00000100) |
| #define | TIM_DCR_DBL_1 ((uint32_t)0x00000200) |
| #define | TIM_DCR_DBL_2 ((uint32_t)0x00000400) |
| #define | TIM_DCR_DBL_3 ((uint32_t)0x00000800) |
| #define | TIM_DCR_DBL_4 ((uint32_t)0x00001000) |
| #define | TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) |
| #define | RTC_CRH_SECIE ((uint32_t)0x00000001) |
| #define | RTC_CRH_ALRIE ((uint32_t)0x00000002) |
| #define | RTC_CRH_OWIE ((uint32_t)0x00000004) |
| #define | RTC_CRL_SECF ((uint32_t)0x00000001) |
| #define | RTC_CRL_ALRF ((uint32_t)0x00000002) |
| #define | RTC_CRL_OWF ((uint32_t)0x00000004) |
| #define | RTC_CRL_RSF ((uint32_t)0x00000008) |
| #define | RTC_CRL_CNF ((uint32_t)0x00000010) |
| #define | RTC_CRL_RTOFF ((uint32_t)0x00000020) |
| #define | RTC_PRLH_PRL ((uint32_t)0x0000000F) |
| #define | RTC_PRLL_PRL ((uint32_t)0x0000FFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) |
| #define | RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) |
| #define | IWDG_KR_KEY ((uint32_t)0x0000FFFF) |
| #define | IWDG_PR_PR ((uint32_t)0x00000007) |
| #define | IWDG_PR_PR_0 ((uint32_t)0x00000001) |
| #define | IWDG_PR_PR_1 ((uint32_t)0x00000002) |
| #define | IWDG_PR_PR_2 ((uint32_t)0x00000004) |
| #define | IWDG_RLR_RL ((uint32_t)0x00000FFF) |
| #define | IWDG_SR_PVU ((uint32_t)0x00000001) |
| #define | IWDG_SR_RVU ((uint32_t)0x00000002) |
| #define | WWDG_CR_T ((uint32_t)0x0000007F) |
| #define | WWDG_CR_T0 ((uint32_t)0x00000001) |
| #define | WWDG_CR_T1 ((uint32_t)0x00000002) |
| #define | WWDG_CR_T2 ((uint32_t)0x00000004) |
| #define | WWDG_CR_T3 ((uint32_t)0x00000008) |
| #define | WWDG_CR_T4 ((uint32_t)0x00000010) |
| #define | WWDG_CR_T5 ((uint32_t)0x00000020) |
| #define | WWDG_CR_T6 ((uint32_t)0x00000040) |
| #define | WWDG_CR_WDGA ((uint32_t)0x00000080) |
| #define | WWDG_CFR_W ((uint32_t)0x0000007F) |
| #define | WWDG_CFR_W0 ((uint32_t)0x00000001) |
| #define | WWDG_CFR_W1 ((uint32_t)0x00000002) |
| #define | WWDG_CFR_W2 ((uint32_t)0x00000004) |
| #define | WWDG_CFR_W3 ((uint32_t)0x00000008) |
| #define | WWDG_CFR_W4 ((uint32_t)0x00000010) |
| #define | WWDG_CFR_W5 ((uint32_t)0x00000020) |
| #define | WWDG_CFR_W6 ((uint32_t)0x00000040) |
| #define | WWDG_CFR_WDGTB ((uint32_t)0x00000180) |
| #define | WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) |
| #define | WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) |
| #define | WWDG_CFR_EWI ((uint32_t)0x00000200) |
| #define | WWDG_SR_EWIF ((uint32_t)0x00000001) |
| #define | SDIO_POWER_PWRCTRL ((uint32_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint32_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint32_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint32_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint32_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint32_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint32_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint32_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint32_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint32_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint32_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint32_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint32_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint32_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint32_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint32_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | CAN_MCR_INRQ ((uint32_t)0x00000001) |
| #define | CAN_MCR_SLEEP ((uint32_t)0x00000002) |
| #define | CAN_MCR_TXFP ((uint32_t)0x00000004) |
| #define | CAN_MCR_RFLM ((uint32_t)0x00000008) |
| #define | CAN_MCR_NART ((uint32_t)0x00000010) |
| #define | CAN_MCR_AWUM ((uint32_t)0x00000020) |
| #define | CAN_MCR_ABOM ((uint32_t)0x00000040) |
| #define | CAN_MCR_TTCM ((uint32_t)0x00000080) |
| #define | CAN_MCR_RESET ((uint32_t)0x00008000) |
| #define | CAN_MCR_DBF ((uint32_t)0x00010000) |
| #define | CAN_MSR_INAK ((uint32_t)0x00000001) |
| #define | CAN_MSR_SLAK ((uint32_t)0x00000002) |
| #define | CAN_MSR_ERRI ((uint32_t)0x00000004) |
| #define | CAN_MSR_WKUI ((uint32_t)0x00000008) |
| #define | CAN_MSR_SLAKI ((uint32_t)0x00000010) |
| #define | CAN_MSR_TXM ((uint32_t)0x00000100) |
| #define | CAN_MSR_RXM ((uint32_t)0x00000200) |
| #define | CAN_MSR_SAMP ((uint32_t)0x00000400) |
| #define | CAN_MSR_RX ((uint32_t)0x00000800) |
| #define | CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
| #define | CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
| #define | CAN_TSR_ALST0 ((uint32_t)0x00000004) |
| #define | CAN_TSR_TERR0 ((uint32_t)0x00000008) |
| #define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
| #define | CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
| #define | CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
| #define | CAN_TSR_ALST1 ((uint32_t)0x00000400) |
| #define | CAN_TSR_TERR1 ((uint32_t)0x00000800) |
| #define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
| #define | CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
| #define | CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
| #define | CAN_TSR_ALST2 ((uint32_t)0x00040000) |
| #define | CAN_TSR_TERR2 ((uint32_t)0x00080000) |
| #define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
| #define | CAN_TSR_CODE ((uint32_t)0x03000000) |
| #define | CAN_TSR_TME ((uint32_t)0x1C000000) |
| #define | CAN_TSR_TME0 ((uint32_t)0x04000000) |
| #define | CAN_TSR_TME1 ((uint32_t)0x08000000) |
| #define | CAN_TSR_TME2 ((uint32_t)0x10000000) |
| #define | CAN_TSR_LOW ((uint32_t)0xE0000000) |
| #define | CAN_TSR_LOW0 ((uint32_t)0x20000000) |
| #define | CAN_TSR_LOW1 ((uint32_t)0x40000000) |
| #define | CAN_TSR_LOW2 ((uint32_t)0x80000000) |
| #define | CAN_RF0R_FMP0 ((uint32_t)0x00000003) |
| #define | CAN_RF0R_FULL0 ((uint32_t)0x00000008) |
| #define | CAN_RF0R_FOVR0 ((uint32_t)0x00000010) |
| #define | CAN_RF0R_RFOM0 ((uint32_t)0x00000020) |
| #define | CAN_RF1R_FMP1 ((uint32_t)0x00000003) |
| #define | CAN_RF1R_FULL1 ((uint32_t)0x00000008) |
| #define | CAN_RF1R_FOVR1 ((uint32_t)0x00000010) |
| #define | CAN_RF1R_RFOM1 ((uint32_t)0x00000020) |
| #define | CAN_IER_TMEIE ((uint32_t)0x00000001) |
| #define | CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
| #define | CAN_IER_FFIE0 ((uint32_t)0x00000004) |
| #define | CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
| #define | CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
| #define | CAN_IER_FFIE1 ((uint32_t)0x00000020) |
| #define | CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
| #define | CAN_IER_EWGIE ((uint32_t)0x00000100) |
| #define | CAN_IER_EPVIE ((uint32_t)0x00000200) |
| #define | CAN_IER_BOFIE ((uint32_t)0x00000400) |
| #define | CAN_IER_LECIE ((uint32_t)0x00000800) |
| #define | CAN_IER_ERRIE ((uint32_t)0x00008000) |
| #define | CAN_IER_WKUIE ((uint32_t)0x00010000) |
| #define | CAN_IER_SLKIE ((uint32_t)0x00020000) |
| #define | CAN_ESR_EWGF ((uint32_t)0x00000001) |
| #define | CAN_ESR_EPVF ((uint32_t)0x00000002) |
| #define | CAN_ESR_BOFF ((uint32_t)0x00000004) |
| #define | CAN_ESR_LEC ((uint32_t)0x00000070) |
| #define | CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
| #define | CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
| #define | CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
| #define | CAN_ESR_TEC ((uint32_t)0x00FF0000) |
| #define | CAN_ESR_REC ((uint32_t)0xFF000000) |
| #define | CAN_BTR_BRP ((uint32_t)0x000003FF) |
| #define | CAN_BTR_TS1 ((uint32_t)0x000F0000) |
| #define | CAN_BTR_TS1_0 ((uint32_t)0x00010000) |
| #define | CAN_BTR_TS1_1 ((uint32_t)0x00020000) |
| #define | CAN_BTR_TS1_2 ((uint32_t)0x00040000) |
| #define | CAN_BTR_TS1_3 ((uint32_t)0x00080000) |
| #define | CAN_BTR_TS2 ((uint32_t)0x00700000) |
| #define | CAN_BTR_TS2_0 ((uint32_t)0x00100000) |
| #define | CAN_BTR_TS2_1 ((uint32_t)0x00200000) |
| #define | CAN_BTR_TS2_2 ((uint32_t)0x00400000) |
| #define | CAN_BTR_SJW ((uint32_t)0x03000000) |
| #define | CAN_BTR_SJW_0 ((uint32_t)0x01000000) |
| #define | CAN_BTR_SJW_1 ((uint32_t)0x02000000) |
| #define | CAN_BTR_LBKM ((uint32_t)0x40000000) |
| #define | CAN_BTR_SILM ((uint32_t)0x80000000) |
| #define | CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT0R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT1R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI2R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI2R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI2R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT2R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_FMR_FINIT ((uint32_t)0x00000001) |
| #define | CAN_FMR_CAN2SB ((uint32_t)0x00003F00) |
| #define | CAN_FM1R_FBM ((uint32_t)0x00003FFF) |
| #define | CAN_FM1R_FBM0 ((uint32_t)0x00000001) |
| #define | CAN_FM1R_FBM1 ((uint32_t)0x00000002) |
| #define | CAN_FM1R_FBM2 ((uint32_t)0x00000004) |
| #define | CAN_FM1R_FBM3 ((uint32_t)0x00000008) |
| #define | CAN_FM1R_FBM4 ((uint32_t)0x00000010) |
| #define | CAN_FM1R_FBM5 ((uint32_t)0x00000020) |
| #define | CAN_FM1R_FBM6 ((uint32_t)0x00000040) |
| #define | CAN_FM1R_FBM7 ((uint32_t)0x00000080) |
| #define | CAN_FM1R_FBM8 ((uint32_t)0x00000100) |
| #define | CAN_FM1R_FBM9 ((uint32_t)0x00000200) |
| #define | CAN_FM1R_FBM10 ((uint32_t)0x00000400) |
| #define | CAN_FM1R_FBM11 ((uint32_t)0x00000800) |
| #define | CAN_FM1R_FBM12 ((uint32_t)0x00001000) |
| #define | CAN_FM1R_FBM13 ((uint32_t)0x00002000) |
| #define | CAN_FM1R_FBM14 ((uint32_t)0x00004000) |
| #define | CAN_FM1R_FBM15 ((uint32_t)0x00008000) |
| #define | CAN_FM1R_FBM16 ((uint32_t)0x00010000) |
| #define | CAN_FM1R_FBM17 ((uint32_t)0x00020000) |
| #define | CAN_FM1R_FBM18 ((uint32_t)0x00040000) |
| #define | CAN_FM1R_FBM19 ((uint32_t)0x00080000) |
| #define | CAN_FM1R_FBM20 ((uint32_t)0x00100000) |
| #define | CAN_FM1R_FBM21 ((uint32_t)0x00200000) |
| #define | CAN_FM1R_FBM22 ((uint32_t)0x00400000) |
| #define | CAN_FM1R_FBM23 ((uint32_t)0x00800000) |
| #define | CAN_FM1R_FBM24 ((uint32_t)0x01000000) |
| #define | CAN_FM1R_FBM25 ((uint32_t)0x02000000) |
| #define | CAN_FM1R_FBM26 ((uint32_t)0x04000000) |
| #define | CAN_FM1R_FBM27 ((uint32_t)0x08000000) |
| #define | CAN_FS1R_FSC ((uint32_t)0x00003FFF) |
| #define | CAN_FS1R_FSC0 ((uint32_t)0x00000001) |
| #define | CAN_FS1R_FSC1 ((uint32_t)0x00000002) |
| #define | CAN_FS1R_FSC2 ((uint32_t)0x00000004) |
| #define | CAN_FS1R_FSC3 ((uint32_t)0x00000008) |
| #define | CAN_FS1R_FSC4 ((uint32_t)0x00000010) |
| #define | CAN_FS1R_FSC5 ((uint32_t)0x00000020) |
| #define | CAN_FS1R_FSC6 ((uint32_t)0x00000040) |
| #define | CAN_FS1R_FSC7 ((uint32_t)0x00000080) |
| #define | CAN_FS1R_FSC8 ((uint32_t)0x00000100) |
| #define | CAN_FS1R_FSC9 ((uint32_t)0x00000200) |
| #define | CAN_FS1R_FSC10 ((uint32_t)0x00000400) |
| #define | CAN_FS1R_FSC11 ((uint32_t)0x00000800) |
| #define | CAN_FS1R_FSC12 ((uint32_t)0x00001000) |
| #define | CAN_FS1R_FSC13 ((uint32_t)0x00002000) |
| #define | CAN_FS1R_FSC14 ((uint32_t)0x00004000) |
| #define | CAN_FS1R_FSC15 ((uint32_t)0x00008000) |
| #define | CAN_FS1R_FSC16 ((uint32_t)0x00010000) |
| #define | CAN_FS1R_FSC17 ((uint32_t)0x00020000) |
| #define | CAN_FS1R_FSC18 ((uint32_t)0x00040000) |
| #define | CAN_FS1R_FSC19 ((uint32_t)0x00080000) |
| #define | CAN_FS1R_FSC20 ((uint32_t)0x00100000) |
| #define | CAN_FS1R_FSC21 ((uint32_t)0x00200000) |
| #define | CAN_FS1R_FSC22 ((uint32_t)0x00400000) |
| #define | CAN_FS1R_FSC23 ((uint32_t)0x00800000) |
| #define | CAN_FS1R_FSC24 ((uint32_t)0x01000000) |
| #define | CAN_FS1R_FSC25 ((uint32_t)0x02000000) |
| #define | CAN_FS1R_FSC26 ((uint32_t)0x04000000) |
| #define | CAN_FS1R_FSC27 ((uint32_t)0x08000000) |
| #define | CAN_FFA1R_FFA ((uint32_t)0x00003FFF) |
| #define | CAN_FFA1R_FFA0 ((uint32_t)0x00000001) |
| #define | CAN_FFA1R_FFA1 ((uint32_t)0x00000002) |
| #define | CAN_FFA1R_FFA2 ((uint32_t)0x00000004) |
| #define | CAN_FFA1R_FFA3 ((uint32_t)0x00000008) |
| #define | CAN_FFA1R_FFA4 ((uint32_t)0x00000010) |
| #define | CAN_FFA1R_FFA5 ((uint32_t)0x00000020) |
| #define | CAN_FFA1R_FFA6 ((uint32_t)0x00000040) |
| #define | CAN_FFA1R_FFA7 ((uint32_t)0x00000080) |
| #define | CAN_FFA1R_FFA8 ((uint32_t)0x00000100) |
| #define | CAN_FFA1R_FFA9 ((uint32_t)0x00000200) |
| #define | CAN_FFA1R_FFA10 ((uint32_t)0x00000400) |
| #define | CAN_FFA1R_FFA11 ((uint32_t)0x00000800) |
| #define | CAN_FFA1R_FFA12 ((uint32_t)0x00001000) |
| #define | CAN_FFA1R_FFA13 ((uint32_t)0x00002000) |
| #define | CAN_FFA1_FFA14 ((uint32_t)0x00004000) |
| #define | CAN_FFA1_FFA15 ((uint32_t)0x00008000) |
| #define | CAN_FFA1_FFA16 ((uint32_t)0x00010000) |
| #define | CAN_FFA1_FFA17 ((uint32_t)0x00020000) |
| #define | CAN_FFA1_FFA18 ((uint32_t)0x00040000) |
| #define | CAN_FFA1_FFA19 ((uint32_t)0x00080000) |
| #define | CAN_FFA1_FFA20 ((uint32_t)0x00100000) |
| #define | CAN_FFA1_FFA21 ((uint32_t)0x00200000) |
| #define | CAN_FFA1_FFA22 ((uint32_t)0x00400000) |
| #define | CAN_FFA1_FFA23 ((uint32_t)0x00800000) |
| #define | CAN_FFA1_FFA24 ((uint32_t)0x01000000) |
| #define | CAN_FFA1_FFA25 ((uint32_t)0x02000000) |
| #define | CAN_FFA1_FFA26 ((uint32_t)0x04000000) |
| #define | CAN_FFA1_FFA27 ((uint32_t)0x08000000) |
| #define | CAN_FA1R_FACT ((uint32_t)0x00003FFF) |
| #define | CAN_FA1R_FACT0 ((uint32_t)0x00000001) |
| #define | CAN_FA1R_FACT1 ((uint32_t)0x00000002) |
| #define | CAN_FA1R_FACT2 ((uint32_t)0x00000004) |
| #define | CAN_FA1R_FACT3 ((uint32_t)0x00000008) |
| #define | CAN_FA1R_FACT4 ((uint32_t)0x00000010) |
| #define | CAN_FA1R_FACT5 ((uint32_t)0x00000020) |
| #define | CAN_FA1R_FACT6 ((uint32_t)0x00000040) |
| #define | CAN_FA1R_FACT7 ((uint32_t)0x00000080) |
| #define | CAN_FA1R_FACT8 ((uint32_t)0x00000100) |
| #define | CAN_FA1R_FACT9 ((uint32_t)0x00000200) |
| #define | CAN_FA1R_FACT10 ((uint32_t)0x00000400) |
| #define | CAN_FA1R_FACT11 ((uint32_t)0x00000800) |
| #define | CAN_FA1R_FACT12 ((uint32_t)0x00001000) |
| #define | CAN_FA1R_FACT13 ((uint32_t)0x00002000) |
| #define | CAN_FA1R_FACT14 ((uint32_t)0x00004000) |
| #define | CAN_FA1R_FACT15 ((uint32_t)0x00008000) |
| #define | CAN_FA1R_FACT16 ((uint32_t)0x00010000) |
| #define | CAN_FA1R_FACT17 ((uint32_t)0x00020000) |
| #define | CAN_FA1R_FACT18 ((uint32_t)0x00040000) |
| #define | CAN_FA1R_FACT19 ((uint32_t)0x00080000) |
| #define | CAN_FA1R_FACT20 ((uint32_t)0x00100000) |
| #define | CAN_FA1R_FACT21 ((uint32_t)0x00200000) |
| #define | CAN_FA1R_FACT22 ((uint32_t)0x00400000) |
| #define | CAN_FA1R_FACT23 ((uint32_t)0x00800000) |
| #define | CAN_FA1R_FACT24 ((uint32_t)0x01000000) |
| #define | CAN_FA1R_FACT25 ((uint32_t)0x02000000) |
| #define | CAN_FA1R_FACT26 ((uint32_t)0x04000000) |
| #define | CAN_FA1R_FACT27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F14R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F14R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F14R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F14R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F14R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F14R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F14R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F14R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F14R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F14R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F14R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F14R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F14R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F14R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F14R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F14R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F14R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F14R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F14R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F14R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F14R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F14R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F14R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F14R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F14R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F14R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F14R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F14R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F14R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F14R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F14R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F14R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F15R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F15R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F15R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F15R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F15R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F15R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F15R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F15R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F15R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F15R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F15R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F15R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F15R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F15R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F15R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F15R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F15R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F15R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F15R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F15R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F15R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F15R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F15R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F15R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F15R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F15R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F15R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F15R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F15R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F15R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F15R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F15R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F16R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F16R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F16R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F16R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F16R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F16R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F16R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F16R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F16R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F16R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F16R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F16R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F16R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F16R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F16R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F16R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F16R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F16R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F16R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F16R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F16R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F16R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F16R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F16R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F16R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F16R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F16R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F16R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F16R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F16R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F16R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F16R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F17R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F17R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F17R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F17R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F17R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F17R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F17R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F17R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F17R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F17R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F17R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F17R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F17R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F17R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F17R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F17R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F17R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F17R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F17R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F17R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F17R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F17R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F17R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F17R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F17R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F17R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F17R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F17R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F17R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F17R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F17R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F17R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F18R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F18R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F18R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F18R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F18R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F18R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F18R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F18R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F18R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F18R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F18R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F18R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F18R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F18R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F18R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F18R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F18R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F18R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F18R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F18R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F18R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F18R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F18R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F18R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F18R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F18R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F18R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F18R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F18R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F18R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F18R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F18R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F19R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F19R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F19R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F19R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F19R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F19R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F19R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F19R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F19R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F19R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F19R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F19R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F19R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F19R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F19R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F19R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F19R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F19R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F19R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F19R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F19R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F19R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F19R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F19R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F19R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F19R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F19R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F19R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F19R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F19R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F19R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F19R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F20R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F20R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F20R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F20R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F20R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F20R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F20R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F20R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F20R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F20R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F20R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F20R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F20R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F20R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F20R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F20R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F20R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F20R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F20R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F20R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F20R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F20R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F20R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F20R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F20R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F20R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F20R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F20R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F20R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F20R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F20R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F20R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F21R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F21R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F21R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F21R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F21R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F21R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F21R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F21R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F21R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F21R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F21R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F21R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F21R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F21R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F21R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F21R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F21R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F21R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F21R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F21R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F21R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F21R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F21R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F21R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F21R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F21R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F21R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F21R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F21R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F21R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F21R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F21R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F22R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F22R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F22R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F22R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F22R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F22R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F22R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F22R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F22R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F22R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F22R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F22R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F22R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F22R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F22R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F22R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F22R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F22R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F22R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F22R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F22R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F22R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F22R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F22R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F22R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F22R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F22R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F22R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F22R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F22R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F22R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F22R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F23R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F23R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F23R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F23R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F23R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F23R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F23R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F23R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F23R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F23R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F23R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F23R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F23R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F23R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F23R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F23R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F23R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F23R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F23R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F23R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F23R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F23R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F23R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F23R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F23R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F23R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F23R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F23R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F23R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F23R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F23R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F23R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F24R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F24R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F24R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F24R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F24R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F24R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F24R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F24R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F24R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F24R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F24R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F24R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F24R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F24R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F24R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F24R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F24R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F24R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F24R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F24R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F24R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F24R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F24R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F24R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F24R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F24R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F24R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F24R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F24R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F24R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F24R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F24R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F25R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F25R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F25R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F25R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F25R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F25R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F25R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F25R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F25R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F25R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F25R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F25R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F25R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F25R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F25R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F25R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F25R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F25R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F25R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F25R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F25R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F25R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F25R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F25R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F25R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F25R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F25R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F25R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F25R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F25R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F25R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F25R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F26R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F26R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F26R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F26R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F26R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F26R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F26R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F26R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F26R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F26R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F26R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F26R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F26R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F26R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F26R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F26R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F26R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F26R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F26R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F26R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F26R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F26R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F26R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F26R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F26R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F26R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F26R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F26R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F26R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F26R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F26R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F26R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F27R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F27R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F27R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F27R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F27R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F27R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F27R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F27R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F27R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F27R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F27R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F27R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F27R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F27R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F27R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F27R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F27R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F27R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F27R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F27R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F27R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F27R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F27R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F27R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F27R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F27R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F27R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F27R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F27R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F27R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F27R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F27R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F0R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F14R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F14R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F14R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F14R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F14R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F14R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F14R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F14R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F14R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F14R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F14R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F14R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F14R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F14R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F14R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F14R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F14R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F14R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F14R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F14R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F14R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F14R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F14R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F14R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F14R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F14R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F14R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F14R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F14R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F14R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F14R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F14R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F15R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F15R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F15R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F15R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F15R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F15R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F15R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F15R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F15R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F15R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F15R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F15R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F15R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F15R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F15R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F15R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F15R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F15R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F15R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F15R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F15R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F15R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F15R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F15R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F15R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F15R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F15R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F15R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F15R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F15R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F15R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F15R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F16R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F16R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F16R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F16R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F16R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F16R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F16R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F16R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F16R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F16R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F16R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F16R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F16R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F16R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F16R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F16R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F16R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F16R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F16R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F16R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F16R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F16R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F16R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F16R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F16R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F16R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F16R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F16R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F16R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F16R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F16R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F16R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F17R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F17R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F17R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F17R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F17R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F17R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F17R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F17R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F17R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F17R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F17R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F17R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F17R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F17R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F17R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F17R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F17R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F17R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F17R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F17R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F17R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F17R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F17R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F17R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F17R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F17R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F17R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F17R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F17R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F17R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F17R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F17R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F18R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F18R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F18R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F18R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F18R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F18R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F18R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F18R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F18R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F18R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F18R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F18R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F18R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F18R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F18R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F18R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F18R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F18R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F18R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F18R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F18R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F18R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F18R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F18R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F18R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F18R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F18R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F18R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F18R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F18R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F18R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F18R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F19R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F19R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F19R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F19R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F19R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F19R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F19R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F19R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F19R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F19R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F19R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F19R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F19R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F19R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F19R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F19R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F19R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F19R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F19R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F19R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F19R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F19R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F19R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F19R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F19R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F19R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F19R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F19R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F19R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F19R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F19R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F19R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F20R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F20R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F20R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F20R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F20R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F20R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F20R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F20R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F20R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F20R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F20R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F20R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F20R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F20R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F20R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F20R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F20R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F20R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F20R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F20R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F20R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F20R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F20R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F20R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F20R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F20R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F20R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F20R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F20R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F20R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F20R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F20R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F21R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F21R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F21R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F21R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F21R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F21R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F21R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F21R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F21R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F21R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F21R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F21R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F21R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F21R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F21R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F21R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F21R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F21R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F21R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F21R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F21R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F21R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F21R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F21R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F21R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F21R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F21R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F21R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F21R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F21R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F21R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F21R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F22R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F22R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F22R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F22R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F22R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F22R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F22R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F22R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F22R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F22R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F22R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F22R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F22R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F22R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F22R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F22R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F22R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F22R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F22R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F22R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F22R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F22R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F22R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F22R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F22R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F22R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F22R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F22R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F22R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F22R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F22R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F22R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F23R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F23R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F23R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F23R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F23R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F23R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F23R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F23R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F23R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F23R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F23R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F23R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F23R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F23R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F23R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F23R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F23R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F23R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F23R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F23R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F23R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F23R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F23R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F23R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F23R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F23R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F23R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F23R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F23R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F23R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F23R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F23R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F24R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F24R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F24R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F24R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F24R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F24R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F24R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F24R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F24R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F24R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F24R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F24R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F24R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F24R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F24R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F24R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F24R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F24R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F24R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F24R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F24R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F24R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F24R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F24R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F24R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F24R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F24R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F24R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F24R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F24R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F24R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F24R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F25R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F25R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F25R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F25R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F25R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F25R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F25R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F25R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F25R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F25R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F25R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F25R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F25R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F25R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F25R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F25R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F25R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F25R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F25R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F25R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F25R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F25R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F25R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F25R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F25R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F25R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F25R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F25R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F25R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F25R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F25R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F25R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F26R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F26R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F26R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F26R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F26R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F26R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F26R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F26R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F26R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F26R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F26R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F26R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F26R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F26R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F26R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F26R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F26R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F26R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F26R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F26R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F26R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F26R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F26R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F26R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F26R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F26R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F26R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F26R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F26R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F26R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F26R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F26R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F27R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F27R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F27R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F27R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F27R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F27R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F27R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F27R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F27R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F27R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F27R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F27R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F27R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F27R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F27R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F27R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F27R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F27R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F27R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F27R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F27R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F27R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F27R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F27R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F27R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F27R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F27R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F27R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F27R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F27R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F27R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F27R2_FB31 ((uint32_t)0x80000000) |
| #define | SPI_CR1_CPHA ((uint32_t)0x00000001) |
| #define | SPI_CR1_CPOL ((uint32_t)0x00000002) |
| #define | SPI_CR1_MSTR ((uint32_t)0x00000004) |
| #define | SPI_CR1_BR ((uint32_t)0x00000038) |
| #define | SPI_CR1_BR_0 ((uint32_t)0x00000008) |
| #define | SPI_CR1_BR_1 ((uint32_t)0x00000010) |
| #define | SPI_CR1_BR_2 ((uint32_t)0x00000020) |
| #define | SPI_CR1_SPE ((uint32_t)0x00000040) |
| #define | SPI_CR1_LSBFIRST ((uint32_t)0x00000080) |
| #define | SPI_CR1_SSI ((uint32_t)0x00000100) |
| #define | SPI_CR1_SSM ((uint32_t)0x00000200) |
| #define | SPI_CR1_RXONLY ((uint32_t)0x00000400) |
| #define | SPI_CR1_DFF ((uint32_t)0x00000800) |
| #define | SPI_CR1_CRCNEXT ((uint32_t)0x00001000) |
| #define | SPI_CR1_CRCEN ((uint32_t)0x00002000) |
| #define | SPI_CR1_BIDIOE ((uint32_t)0x00004000) |
| #define | SPI_CR1_BIDIMODE ((uint32_t)0x00008000) |
| #define | SPI_CR2_RXDMAEN ((uint32_t)0x00000001) |
| #define | SPI_CR2_TXDMAEN ((uint32_t)0x00000002) |
| #define | SPI_CR2_SSOE ((uint32_t)0x00000004) |
| #define | SPI_CR2_ERRIE ((uint32_t)0x00000020) |
| #define | SPI_CR2_RXNEIE ((uint32_t)0x00000040) |
| #define | SPI_CR2_TXEIE ((uint32_t)0x00000080) |
| #define | SPI_SR_RXNE ((uint32_t)0x00000001) |
| #define | SPI_SR_TXE ((uint32_t)0x00000002) |
| #define | SPI_SR_CHSIDE ((uint32_t)0x00000004) |
| #define | SPI_SR_UDR ((uint32_t)0x00000008) |
| #define | SPI_SR_CRCERR ((uint32_t)0x00000010) |
| #define | SPI_SR_MODF ((uint32_t)0x00000020) |
| #define | SPI_SR_OVR ((uint32_t)0x00000040) |
| #define | SPI_SR_BSY ((uint32_t)0x00000080) |
| #define | SPI_DR_DR ((uint32_t)0x0000FFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) |
| #define | SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) |
| #define | SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) |
| #define | SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) |
| #define | SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) |
| #define | SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) |
| #define | SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) |
| #define | SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) |
| #define | SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) |
| #define | SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) |
| #define | SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) |
| #define | SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) |
| #define | SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) |
| #define | SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) |
| #define | SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) |
| #define | SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) |
| #define | SPI_I2SPR_ODD ((uint32_t)0x00000100) |
| #define | SPI_I2SPR_MCKOE ((uint32_t)0x00000200) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_SMBUS ((uint32_t)0x00000002) |
| #define | I2C_CR1_SMBTYPE ((uint32_t)0x00000008) |
| #define | I2C_CR1_ENARP ((uint32_t)0x00000010) |
| #define | I2C_CR1_ENPEC ((uint32_t)0x00000020) |
| #define | I2C_CR1_ENGC ((uint32_t)0x00000040) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) |
| #define | I2C_CR1_START ((uint32_t)0x00000100) |
| #define | I2C_CR1_STOP ((uint32_t)0x00000200) |
| #define | I2C_CR1_ACK ((uint32_t)0x00000400) |
| #define | I2C_CR1_POS ((uint32_t)0x00000800) |
| #define | I2C_CR1_PEC ((uint32_t)0x00001000) |
| #define | I2C_CR1_ALERT ((uint32_t)0x00002000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00008000) |
| #define | I2C_CR2_FREQ ((uint32_t)0x0000003F) |
| #define | I2C_CR2_FREQ_0 ((uint32_t)0x00000001) |
| #define | I2C_CR2_FREQ_1 ((uint32_t)0x00000002) |
| #define | I2C_CR2_FREQ_2 ((uint32_t)0x00000004) |
| #define | I2C_CR2_FREQ_3 ((uint32_t)0x00000008) |
| #define | I2C_CR2_FREQ_4 ((uint32_t)0x00000010) |
| #define | I2C_CR2_FREQ_5 ((uint32_t)0x00000020) |
| #define | I2C_CR2_ITERREN ((uint32_t)0x00000100) |
| #define | I2C_CR2_ITEVTEN ((uint32_t)0x00000200) |
| #define | I2C_CR2_ITBUFEN ((uint32_t)0x00000400) |
| #define | I2C_CR2_DMAEN ((uint32_t)0x00000800) |
| #define | I2C_CR2_LAST ((uint32_t)0x00001000) |
| #define | I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) |
| #define | I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) |
| #define | I2C_OAR1_ADD0 ((uint32_t)0x00000001) |
| #define | I2C_OAR1_ADD1 ((uint32_t)0x00000002) |
| #define | I2C_OAR1_ADD2 ((uint32_t)0x00000004) |
| #define | I2C_OAR1_ADD3 ((uint32_t)0x00000008) |
| #define | I2C_OAR1_ADD4 ((uint32_t)0x00000010) |
| #define | I2C_OAR1_ADD5 ((uint32_t)0x00000020) |
| #define | I2C_OAR1_ADD6 ((uint32_t)0x00000040) |
| #define | I2C_OAR1_ADD7 ((uint32_t)0x00000080) |
| #define | I2C_OAR1_ADD8 ((uint32_t)0x00000100) |
| #define | I2C_OAR1_ADD9 ((uint32_t)0x00000200) |
| #define | I2C_OAR1_ADDMODE ((uint32_t)0x00008000) |
| #define | I2C_OAR2_ENDUAL ((uint32_t)0x00000001) |
| #define | I2C_OAR2_ADD2 ((uint32_t)0x000000FE) |
| #define | I2C_SR1_SB ((uint32_t)0x00000001) |
| #define | I2C_SR1_ADDR ((uint32_t)0x00000002) |
| #define | I2C_SR1_BTF ((uint32_t)0x00000004) |
| #define | I2C_SR1_ADD10 ((uint32_t)0x00000008) |
| #define | I2C_SR1_STOPF ((uint32_t)0x00000010) |
| #define | I2C_SR1_RXNE ((uint32_t)0x00000040) |
| #define | I2C_SR1_TXE ((uint32_t)0x00000080) |
| #define | I2C_SR1_BERR ((uint32_t)0x00000100) |
| #define | I2C_SR1_ARLO ((uint32_t)0x00000200) |
| #define | I2C_SR1_AF ((uint32_t)0x00000400) |
| #define | I2C_SR1_OVR ((uint32_t)0x00000800) |
| #define | I2C_SR1_PECERR ((uint32_t)0x00001000) |
| #define | I2C_SR1_TIMEOUT ((uint32_t)0x00004000) |
| #define | I2C_SR1_SMBALERT ((uint32_t)0x00008000) |
| #define | I2C_SR2_MSL ((uint32_t)0x00000001) |
| #define | I2C_SR2_BUSY ((uint32_t)0x00000002) |
| #define | I2C_SR2_TRA ((uint32_t)0x00000004) |
| #define | I2C_SR2_GENCALL ((uint32_t)0x00000010) |
| #define | I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) |
| #define | I2C_SR2_SMBHOST ((uint32_t)0x00000040) |
| #define | I2C_SR2_DUALF ((uint32_t)0x00000080) |
| #define | I2C_SR2_PEC ((uint32_t)0x0000FF00) |
| #define | I2C_CCR_CCR ((uint32_t)0x00000FFF) |
| #define | I2C_CCR_DUTY ((uint32_t)0x00004000) |
| #define | I2C_CCR_FS ((uint32_t)0x00008000) |
| #define | I2C_TRISE_TRISE ((uint32_t)0x0000003F) |
| #define | USART_SR_PE ((uint32_t)0x00000001) |
| #define | USART_SR_FE ((uint32_t)0x00000002) |
| #define | USART_SR_NE ((uint32_t)0x00000004) |
| #define | USART_SR_ORE ((uint32_t)0x00000008) |
| #define | USART_SR_IDLE ((uint32_t)0x00000010) |
| #define | USART_SR_RXNE ((uint32_t)0x00000020) |
| #define | USART_SR_TC ((uint32_t)0x00000040) |
| #define | USART_SR_TXE ((uint32_t)0x00000080) |
| #define | USART_SR_LBD ((uint32_t)0x00000100) |
| #define | USART_SR_CTS ((uint32_t)0x00000200) |
| #define | USART_DR_DR ((uint32_t)0x000001FF) |
| #define | USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) |
| #define | USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) |
| #define | USART_CR1_SBK ((uint32_t)0x00000001) |
| #define | USART_CR1_RWU ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_UE ((uint32_t)0x00002000) |
| #define | USART_CR2_ADD ((uint32_t)0x0000000F) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_GTPR_PSC ((uint32_t)0x000000FF) |
| #define | USART_GTPR_PSC_0 ((uint32_t)0x00000001) |
| #define | USART_GTPR_PSC_1 ((uint32_t)0x00000002) |
| #define | USART_GTPR_PSC_2 ((uint32_t)0x00000004) |
| #define | USART_GTPR_PSC_3 ((uint32_t)0x00000008) |
| #define | USART_GTPR_PSC_4 ((uint32_t)0x00000010) |
| #define | USART_GTPR_PSC_5 ((uint32_t)0x00000020) |
| #define | USART_GTPR_PSC_6 ((uint32_t)0x00000040) |
| #define | USART_GTPR_PSC_7 ((uint32_t)0x00000080) |
| #define | USART_GTPR_GT ((uint32_t)0x0000FF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) |
| #define | DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) |
| #define | DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) |
| #define | DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) |
| #define | DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) |
| #define | DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) |
| #define | DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) |
| #define | DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) |
| #define | DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) |
| #define | FLASH_ACR_HLFCYA ((uint32_t)0x00000008) |
| #define | FLASH_ACR_PRFTBE ((uint32_t)0x00000010) |
| #define | FLASH_ACR_PRFTBS ((uint32_t)0x00000020) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint32_t)0x000000A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPRTERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT ((uint32_t)0x00000002) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) |
| #define | FLASH_OBR_USER ((uint32_t)0x0000001C) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) |
| #define | FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) |
| #define | FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) |
| #define | FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ |
| #define | ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ |
| #define | ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ |
| #define | ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ |
| #define | ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ |
| #define | ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ |
| #define | ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ |
| #define | ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ |
| #define | ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ |
| #define | ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ |
| #define | ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ |
| #define | ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ |
| #define | ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ |
| #define | ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ |
| #define | ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ |
| #define | ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ |
| #define | ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ |
| #define | ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ |
| #define | ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ |
| #define | ETH_MACCR_BL |
| #define | ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ |
| #define | ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ |
| #define | ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ |
| #define | ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ |
| #define | ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ |
| #define | ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ |
| #define | ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ |
| #define | ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ |
| #define | ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ |
| #define | ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ |
| #define | ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ |
| #define | ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ |
| #define | ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ |
| #define | ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ |
| #define | ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ |
| #define | ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ |
| #define | ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ |
| #define | ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ |
| #define | ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ |
| #define | ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ |
| #define | ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ |
| #define | ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ |
| #define | ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ |
| #define | ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ |
| #define | ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ |
| #define | ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ |
| #define | ETH_MACMIIAR_CR_DIV42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ |
| #define | ETH_MACMIIAR_CR_DIV16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
| #define | ETH_MACMIIAR_CR_DIV26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
| #define | ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ |
| #define | ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ |
| #define | ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ |
| #define | ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ |
| #define | ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ |
| #define | ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ |
| #define | ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ |
| #define | ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ |
| #define | ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ |
| #define | ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ |
| #define | ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ |
| #define | ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ |
| #define | ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ |
| #define | ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ |
| #define | ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ |
| #define | ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ |
| #define | ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ |
| #define | ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ |
| #define | ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ |
| #define | ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ |
| #define | ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ |
| #define | ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ |
| #define | ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ |
| #define | ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ |
| #define | ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ |
| #define | ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ |
| #define | ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ |
| #define | ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ |
| #define | ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ |
| #define | ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ |
| #define | ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ |
| #define | ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ |
| #define | ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ |
| #define | ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
| #define | ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ |
| #define | ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
| #define | ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ |
| #define | ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
| #define | ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
| #define | ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
| #define | ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ |
| #define | ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
| #define | ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
| #define | ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ |
| #define | ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ |
| #define | ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ |
| #define | ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ |
| #define | ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ |
| #define | ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ |
| #define | ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ |
| #define | ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ |
| #define | ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
| #define | ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
| #define | ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
| #define | ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ |
| #define | ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ |
| #define | ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ |
| #define | ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ |
| #define | ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ |
| #define | ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ |
| #define | ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ |
| #define | ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ |
| #define | ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ |
| #define | ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ |
| #define | ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ |
| #define | ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ |
| #define | ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ |
| #define | ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ |
| #define | ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ |
| #define | ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ |
| #define | ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ |
| #define | ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ |
| #define | ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ |
| #define | ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ |
| #define | ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ |
| #define | ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ |
| #define | ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ |
| #define | ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ |
| #define | ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
| #define | ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
| #define | ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| #define | ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| #define | ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| #define | ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| #define | ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| #define | ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| #define | ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| #define | ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| #define | ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
| #define | ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
| #define | ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ |
| #define | ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ |
| #define | ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
| #define | ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
| #define | ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| #define | ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| #define | ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| #define | ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| #define | ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| #define | ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| #define | ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| #define | ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| #define | ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
| #define | ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
| #define | ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ |
| #define | ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ |
| #define | ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ |
| #define | ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ |
| #define | ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ |
| #define | ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ |
| #define | ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ |
| #define | ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ |
| #define | ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ |
| #define | ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ |
| #define | ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ |
| #define | ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ |
| #define | ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ |
| #define | ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ |
| #define | ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ |
| #define | ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ |
| #define | ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ |
| #define | ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ |
| #define | ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ |
| #define | ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ |
| #define | ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ |
| #define | ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ |
| #define | ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ |
| #define | ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ |
| #define | ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ |
| #define | ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ |
| #define | ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ |
| #define | ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ |
| #define | ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ |
| #define | ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ |
| #define | ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ |
| #define | ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ |
| #define | ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ |
| #define | ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ |
| #define | ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ |
| #define | ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ |
| #define | ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ |
| #define | ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ |
| #define | ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ |
| #define | ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ |
| #define | ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ |
| #define | ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ |
| #define | ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ |
| #define | ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ |
| #define | ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ |
| #define | ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ |
| #define | ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ |
| #define | ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ |
| #define | ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ |
| #define | ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
| #define | ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
| #define | ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
| #define | ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
| #define | ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
| #define | ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
| #define | ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
| #define | ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
| #define | ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ |
| #define | ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ |
| #define | ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ |
| #define | ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ |
| #define | ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
| #define | ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
| #define | ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
| #define | ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
| #define | ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ |
| #define | ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ |
| #define | ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ |
| #define | ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ |
| #define | ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ |
| #define | ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ |
| #define | ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ |
| #define | ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ |
| #define | ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ |
| #define | ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ |
| #define | ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ |
| #define | ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ |
| #define | ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ |
| #define | ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ |
| #define | ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ |
| #define | ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ |
| #define | ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ |
| #define | ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ |
| #define | ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ |
| #define | ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ |
| #define | ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ |
| #define | ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ |
| #define | ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ |
| #define | ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ |
| #define | ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ |
| #define | USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) |
| #define | USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) |
| #define | USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) |
| #define | USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) |
| #define | USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) |
| #define | USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) |
| #define | USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) |
| #define | USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) |
| #define | USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) |
| #define | USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) |
| #define | USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) |
| #define | USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) |
| #define | USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) |
| #define | USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) |
| #define | USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) |
| #define | USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) |
| #define | USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) |
| #define | USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) |
| #define | USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) |
| #define | USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) |
| #define | USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) |
| #define | USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) |
| #define | USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) |
| #define | USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) |
| #define | USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) |
| #define | USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) |
| #define | USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) |
| #define | USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) |
| #define | USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) |
| #define | USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) |
| #define | USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) |
| #define | USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) |
| #define | USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) |
| #define | USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) |
| #define | USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) |
| #define | USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) |
| #define | USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) |
| #define | USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) |
| #define | USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) |
| #define | USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) |
| #define | USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) |
| #define | USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) |
| #define | USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) |
| #define | USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) |
| #define | USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) |
| #define | USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) |
| #define | USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) |
| #define | USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) |
| #define | USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) |
| #define | USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) |
| #define | USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) |
| #define | USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) |
| #define | USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) |
| #define | USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) |
| #define | USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) |
| #define | USB_OTG_DSTS_EERR ((uint32_t)0x00000008) |
| #define | USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) |
| #define | USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) |
| #define | USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) |
| #define | USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) |
| #define | USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) |
| #define | USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) |
| #define | USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) |
| #define | USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) |
| #define | USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) |
| #define | USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) |
| #define | USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) |
| #define | USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) |
| #define | USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) |
| #define | USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) |
| #define | USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) |
| #define | USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) |
| #define | USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) |
| #define | USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) |
| #define | USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) |
| #define | USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) |
| #define | USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) |
| #define | USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) |
| #define | USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) |
| #define | USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) |
| #define | USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) |
| #define | USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) |
| #define | USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) |
| #define | USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) |
| #define | USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) |
| #define | USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) |
| #define | USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) |
| #define | USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) |
| #define | USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) |
| #define | USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) |
| #define | USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) |
| #define | USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) |
| #define | USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) |
| #define | USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) |
| #define | USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) |
| #define | USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) |
| #define | USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) |
| #define | USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) |
| #define | USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) |
| #define | USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) |
| #define | USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) |
| #define | USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) |
| #define | USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) |
| #define | USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) |
| #define | USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) |
| #define | USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) |
| #define | USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) |
| #define | USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) |
| #define | USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) |
| #define | USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) |
| #define | USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) |
| #define | USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) |
| #define | USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) |
| #define | USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) |
| #define | USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) |
| #define | USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) |
| #define | USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) |
| #define | USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) |
| #define | USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) |
| #define | USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) |
| #define | USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) |
| #define | USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) |
| #define | USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) |
| #define | USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) |
| #define | USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) |
| #define | USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) |
| #define | USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) |
| #define | USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) |
| #define | USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) |
| #define | USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) |
| #define | USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) |
| #define | USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) |
| #define | USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) |
| #define | USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) |
| #define | USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) |
| #define | USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) |
| #define | USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) |
| #define | USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) |
| #define | USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) |
| #define | USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) |
| #define | USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) |
| #define | USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) |
| #define | USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) |
| #define | USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) |
| #define | USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) |
| #define | USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) |
| #define | USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) |
| #define | USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) |
| #define | USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) |
| #define | USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) |
| #define | USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) |
| #define | USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) |
| #define | USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) |
| #define | USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) |
| #define | USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) |
| #define | USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) |
| #define | USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) |
| #define | USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) |
| #define | USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) |
| #define | USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) |
| #define | USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) |
| #define | USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) |
| #define | USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) |
| #define | USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) |
| #define | USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) |
| #define | USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) |
| #define | USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) |
| #define | USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) |
| #define | USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) |
| #define | USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) |
| #define | USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) |
| #define | USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) |
| #define | USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) |
| #define | USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) |
| #define | USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) |
| #define | USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) |
| #define | USB_OTG_CHNUM ((uint32_t)0x0000000F) |
| #define | USB_OTG_CHNUM ((uint32_t)0x0000000F) |
| #define | USB_OTG_CHNUM_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_CHNUM_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_CHNUM_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_CHNUM_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_CHNUM_2 ((uint32_t)0x00000004) |
| #define | USB_OTG_CHNUM_2 ((uint32_t)0x00000004) |
| #define | USB_OTG_CHNUM_3 ((uint32_t)0x00000008) |
| #define | USB_OTG_CHNUM_3 ((uint32_t)0x00000008) |
| #define | USB_OTG_BCNT ((uint32_t)0x00007FF0) |
| #define | USB_OTG_BCNT ((uint32_t)0x00007FF0) |
| #define | USB_OTG_DPID ((uint32_t)0x00018000) |
| #define | USB_OTG_DPID ((uint32_t)0x00018000) |
| #define | USB_OTG_DPID_0 ((uint32_t)0x00008000) |
| #define | USB_OTG_DPID_0 ((uint32_t)0x00008000) |
| #define | USB_OTG_DPID_1 ((uint32_t)0x00010000) |
| #define | USB_OTG_DPID_1 ((uint32_t)0x00010000) |
| #define | USB_OTG_PKTSTS ((uint32_t)0x001E0000) |
| #define | USB_OTG_PKTSTS ((uint32_t)0x001E0000) |
| #define | USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) |
| #define | USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) |
| #define | USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) |
| #define | USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) |
| #define | USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) |
| #define | USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) |
| #define | USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) |
| #define | USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) |
| #define | USB_OTG_EPNUM ((uint32_t)0x0000000F) |
| #define | USB_OTG_EPNUM ((uint32_t)0x0000000F) |
| #define | USB_OTG_EPNUM_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_EPNUM_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_EPNUM_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_EPNUM_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_EPNUM_2 ((uint32_t)0x00000004) |
| #define | USB_OTG_EPNUM_2 ((uint32_t)0x00000004) |
| #define | USB_OTG_EPNUM_3 ((uint32_t)0x00000008) |
| #define | USB_OTG_EPNUM_3 ((uint32_t)0x00000008) |
| #define | USB_OTG_FRMNUM ((uint32_t)0x01E00000) |
| #define | USB_OTG_FRMNUM ((uint32_t)0x01E00000) |
| #define | USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) |
| #define | USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) |
| #define | USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) |
| #define | USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) |
| #define | USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) |
| #define | USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) |
| #define | USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) |
| #define | USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) |
| #define | USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) |
| #define | USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_TX0FD ((uint32_t)0xFFFF0000) |
| #define | USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) |
| #define | USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) |
| #define | USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) |
| #define | USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) |
| #define | USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) |
| #define | USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) |
| #define | USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) |
| #define | USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) |
| #define | USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) |
| #define | USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) |
| #define | USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) |
| #define | USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) |
| #define | USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) |
| #define | USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) |
| #define | USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) |
| #define | USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) |
| #define | USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) |
| #define | USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) |
| #define | USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) |
| #define | USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) |
| #define | USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) |
| #define | USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) |
| #define | USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) |
| #define | USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) |
| #define | USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) |
| #define | USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) |
| #define | USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) |
| #define | USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) |
| #define | USB_OTG_HPRT_PENA ((uint32_t)0x00000004) |
| #define | USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) |
| #define | USB_OTG_HPRT_POCA ((uint32_t)0x00000010) |
| #define | USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) |
| #define | USB_OTG_HPRT_PRES ((uint32_t)0x00000040) |
| #define | USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) |
| #define | USB_OTG_HPRT_PRST ((uint32_t)0x00000100) |
| #define | USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) |
| #define | USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) |
| #define | USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) |
| #define | USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) |
| #define | USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) |
| #define | USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) |
| #define | USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) |
| #define | USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) |
| #define | USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) |
| #define | USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) |
| #define | USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) |
| #define | USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) |
| #define | USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) |
| #define | USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) |
| #define | USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) |
| #define | USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) |
| #define | USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) |
| #define | USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) |
| #define | USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) |
| #define | USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) |
| #define | USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) |
| #define | USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) |
| #define | USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) |
| #define | USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) |
| #define | USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) |
| #define | USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) |
| #define | USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) |
| #define | USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) |
| #define | USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) |
| #define | USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) |
| #define | USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) |
| #define | USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) |
| #define | USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) |
| #define | USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) |
| #define | USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) |
| #define | USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) |
| #define | USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) |
| #define | USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) |
| #define | USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) |
| #define | USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) |
| #define | USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) |
| #define | USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) |
| #define | USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) |
| #define | USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) |
| #define | USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) |
| #define | USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) |
| #define | USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) |
| #define | USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) |
| #define | USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) |
| #define | USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) |
| #define | USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) |
| #define | USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) |
| #define | USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) |
| #define | USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) |
| #define | USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) |
| #define | USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) |
| #define | USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) |
| #define | USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) |
| #define | USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) |
| #define | USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) |
| #define | USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) |
| #define | USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) |
| #define | USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) |
| #define | USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) |
| #define | USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) |
| #define | USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) |
| #define | USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) |
| #define | USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) |
| #define | USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) |
| #define | USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) |
| #define | USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) |
| #define | USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) |
| #define | USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) |
| #define | USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) |
| #define | USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) |
| #define | USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) |
| #define | USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) |
| #define | USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) |
| #define | USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) |
| #define | USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) |
| #define | USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) |
| #define | USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) |
| #define | USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) |
| #define | USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) |
| #define | USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) |
| #define | USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) |
| #define | USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) |
| #define | USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) |
| #define | USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) |
| #define | USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) |
| #define | USB_OTG_HCINT_CHH ((uint32_t)0x00000002) |
| #define | USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) |
| #define | USB_OTG_HCINT_STALL ((uint32_t)0x00000008) |
| #define | USB_OTG_HCINT_NAK ((uint32_t)0x00000010) |
| #define | USB_OTG_HCINT_ACK ((uint32_t)0x00000020) |
| #define | USB_OTG_HCINT_NYET ((uint32_t)0x00000040) |
| #define | USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) |
| #define | USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) |
| #define | USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) |
| #define | USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) |
| #define | USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) |
| #define | USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) |
| #define | USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) |
| #define | USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) |
| #define | USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) |
| #define | USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) |
| #define | USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) |
| #define | USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) |
| #define | USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) |
| #define | USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) |
| #define | USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) |
| #define | USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) |
| #define | USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) |
| #define | USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) |
| #define | USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) |
| #define | USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) |
| #define | USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) |
| #define | USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) |
| #define | USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) |
| #define | USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) |
| #define | USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) |
| #define | USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) |
| #define | USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) |
| #define | USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) |
| #define | USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) |
| #define | USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) |
| #define | USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) |
| #define | USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) |
| #define | USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) |
| #define | USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) |
| #define | USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) |
| #define | USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) |
| #define | USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) |
| #define | USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) |
| #define | USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) |
| #define | USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) |
| #define | USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) |
| #define | USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) |
| #define | USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) |
| #define | USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) |
| #define | USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) |
| #define | USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) |
| #define | USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) |
| #define | USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) |
| #define | USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) |
| #define | USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) |
| #define | USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) |
| #define | USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) |
| #define | USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) |
| #define | USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) |
| #define | USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) |
| #define | USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) |
| #define | USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) |
| #define | USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) |
| #define | USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) |
| #define | USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) |
| #define | USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) |
| #define | USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) |
| #define | USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) |
| #define | USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) |
| #define | USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) |
| #define | USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) |
| #define | USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) |
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
Analog Watchdog interrupt enable
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
Analog Watchdog interrupt enable
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
Analog Watchdog interrupt enable
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
Analog Watchdog interrupt enable
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
Analog Watchdog interrupt enable
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
Analog Watchdog interrupt enable
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
Analog Watchdog interrupt enable
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
Analog Watchdog interrupt enable
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
Analog Watchdog interrupt enable
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
Analog Watchdog interrupt enable
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
Analog Watchdog interrupt enable
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
Analog Watchdog interrupt enable
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
Analog Watchdog interrupt enable
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
Analog Watchdog interrupt enable
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
| #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
DUALMOD[3:0] bits (Dual mode selection)
| #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
DUALMOD[3:0] bits (Dual mode selection)
| #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
DUALMOD[3:0] bits (Dual mode selection)
| #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
DUALMOD[3:0] bits (Dual mode selection)
| #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
DUALMOD[3:0] bits (Dual mode selection)
| #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
DUALMOD[3:0] bits (Dual mode selection)
| #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
DUALMOD[3:0] bits (Dual mode selection)
| #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
Bit 0
| #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
Bit 0
| #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
Bit 0
| #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
Bit 0
| #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
Bit 0
| #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
Bit 0
| #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
Bit 0
| #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
Bit 1
| #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
Bit 1
| #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
Bit 1
| #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
Bit 1
| #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
Bit 1
| #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
Bit 1
| #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
Bit 1
| #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
Bit 2
| #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
Bit 2
| #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
Bit 2
| #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
Bit 2
| #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
Bit 2
| #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
Bit 2
| #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
Bit 2
| #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
Bit 3
| #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
Bit 3
| #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
Bit 3
| #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
Bit 3
| #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
Bit 3
| #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
Bit 3
| #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
Bit 3
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
A/D Converter ON / OFF
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
| #define ADC_CR2_CAL ((uint32_t)0x00000004) |
A/D Calibration
| #define ADC_CR2_CAL ((uint32_t)0x00000004) |
A/D Calibration
| #define ADC_CR2_CAL ((uint32_t)0x00000004) |
A/D Calibration
| #define ADC_CR2_CAL ((uint32_t)0x00000004) |
A/D Calibration
| #define ADC_CR2_CAL ((uint32_t)0x00000004) |
A/D Calibration
| #define ADC_CR2_CAL ((uint32_t)0x00000004) |
A/D Calibration
| #define ADC_CR2_CAL ((uint32_t)0x00000004) |
A/D Calibration
| #define ADC_CR2_CAL ((uint32_t)0x00000004) |
A/D Calibration
| #define ADC_CR2_CAL ((uint32_t)0x00000004) |
A/D Calibration
| #define ADC_CR2_CAL ((uint32_t)0x00000004) |
A/D Calibration
| #define ADC_CR2_CAL ((uint32_t)0x00000004) |
A/D Calibration
| #define ADC_CR2_CAL ((uint32_t)0x00000004) |
A/D Calibration
| #define ADC_CR2_CAL ((uint32_t)0x00000004) |
A/D Calibration
| #define ADC_CR2_CAL ((uint32_t)0x00000004) |
A/D Calibration
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
Direct Memory access mode
| #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
EXTSEL[2:0] bits (External Event Select for regular group)
| #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
EXTSEL[2:0] bits (External Event Select for regular group)
| #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
EXTSEL[2:0] bits (External Event Select for regular group)
| #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
EXTSEL[2:0] bits (External Event Select for regular group)
| #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
EXTSEL[2:0] bits (External Event Select for regular group)
| #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
EXTSEL[2:0] bits (External Event Select for regular group)
| #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
EXTSEL[2:0] bits (External Event Select for regular group)
| #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
EXTSEL[2:0] bits (External Event Select for regular group)
| #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
EXTSEL[2:0] bits (External Event Select for regular group)
| #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
EXTSEL[2:0] bits (External Event Select for regular group)
| #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
EXTSEL[2:0] bits (External Event Select for regular group)
| #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
EXTSEL[2:0] bits (External Event Select for regular group)
| #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
EXTSEL[2:0] bits (External Event Select for regular group)
| #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
EXTSEL[2:0] bits (External Event Select for regular group)
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
Bit 0
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
Bit 0
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
Bit 0
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
Bit 0
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
Bit 0
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
Bit 0
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
Bit 0
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
Bit 0
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
Bit 0
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
Bit 0
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
Bit 0
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
Bit 0
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
Bit 0
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
Bit 0
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
Bit 1
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
Bit 1
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
Bit 1
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
Bit 1
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
Bit 1
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
Bit 1
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
Bit 1
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
Bit 1
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
Bit 1
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
Bit 1
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
Bit 1
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
Bit 1
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
Bit 1
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
Bit 1
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
Bit 2
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
Bit 2
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
Bit 2
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
Bit 2
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
Bit 2
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
Bit 2
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
Bit 2
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
Bit 2
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
Bit 2
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
Bit 2
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
Bit 2
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
Bit 2
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
Bit 2
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
Bit 2
| #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
External Trigger Conversion mode for regular channels
| #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
External Trigger Conversion mode for regular channels
| #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
External Trigger Conversion mode for regular channels
| #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
External Trigger Conversion mode for regular channels
| #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
External Trigger Conversion mode for regular channels
| #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
External Trigger Conversion mode for regular channels
| #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
External Trigger Conversion mode for regular channels
| #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
External Trigger Conversion mode for regular channels
| #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
External Trigger Conversion mode for regular channels
| #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
External Trigger Conversion mode for regular channels
| #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
External Trigger Conversion mode for regular channels
| #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
External Trigger Conversion mode for regular channels
| #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
External Trigger Conversion mode for regular channels
| #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
External Trigger Conversion mode for regular channels
| #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
JEXTSEL[2:0] bits (External event select for injected group)
| #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
JEXTSEL[2:0] bits (External event select for injected group)
| #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
JEXTSEL[2:0] bits (External event select for injected group)
| #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
JEXTSEL[2:0] bits (External event select for injected group)
| #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
JEXTSEL[2:0] bits (External event select for injected group)
| #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
JEXTSEL[2:0] bits (External event select for injected group)
| #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
JEXTSEL[2:0] bits (External event select for injected group)
| #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
JEXTSEL[2:0] bits (External event select for injected group)
| #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
JEXTSEL[2:0] bits (External event select for injected group)
| #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
JEXTSEL[2:0] bits (External event select for injected group)
| #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
JEXTSEL[2:0] bits (External event select for injected group)
| #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
JEXTSEL[2:0] bits (External event select for injected group)
| #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
JEXTSEL[2:0] bits (External event select for injected group)
| #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
JEXTSEL[2:0] bits (External event select for injected group)
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
External Trigger Conversion mode for injected channels
| #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
External Trigger Conversion mode for injected channels
| #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
External Trigger Conversion mode for injected channels
| #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
External Trigger Conversion mode for injected channels
| #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
External Trigger Conversion mode for injected channels
| #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
External Trigger Conversion mode for injected channels
| #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
External Trigger Conversion mode for injected channels
| #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
External Trigger Conversion mode for injected channels
| #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
External Trigger Conversion mode for injected channels
| #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
External Trigger Conversion mode for injected channels
| #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
External Trigger Conversion mode for injected channels
| #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
External Trigger Conversion mode for injected channels
| #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
External Trigger Conversion mode for injected channels
| #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
External Trigger Conversion mode for injected channels
| #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
Start Conversion of injected channels
| #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
Start Conversion of injected channels
| #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
Start Conversion of injected channels
| #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
Start Conversion of injected channels
| #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
Start Conversion of injected channels
| #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
Start Conversion of injected channels
| #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
Start Conversion of injected channels
| #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
Start Conversion of injected channels
| #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
Start Conversion of injected channels
| #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
Start Conversion of injected channels
| #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
Start Conversion of injected channels
| #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
Start Conversion of injected channels
| #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
Start Conversion of injected channels
| #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
Start Conversion of injected channels
| #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
Reset Calibration
| #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
Reset Calibration
| #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
Reset Calibration
| #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
Reset Calibration
| #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
Reset Calibration
| #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
Reset Calibration
| #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
Reset Calibration
| #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
Reset Calibration
| #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
Reset Calibration
| #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
Reset Calibration
| #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
Reset Calibration
| #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
Reset Calibration
| #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
Reset Calibration
| #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
Reset Calibration
| #define ADC_CR2_SWSTART ((uint32_t)0x00400000) |
Start Conversion of regular channels
| #define ADC_CR2_SWSTART ((uint32_t)0x00400000) |
Start Conversion of regular channels
| #define ADC_CR2_SWSTART ((uint32_t)0x00400000) |
Start Conversion of regular channels
| #define ADC_CR2_SWSTART ((uint32_t)0x00400000) |
Start Conversion of regular channels
| #define ADC_CR2_SWSTART ((uint32_t)0x00400000) |
Start Conversion of regular channels
| #define ADC_CR2_SWSTART ((uint32_t)0x00400000) |
Start Conversion of regular channels
| #define ADC_CR2_SWSTART ((uint32_t)0x00400000) |
Start Conversion of regular channels
| #define ADC_CR2_SWSTART ((uint32_t)0x00400000) |
Start Conversion of regular channels
| #define ADC_CR2_SWSTART ((uint32_t)0x00400000) |
Start Conversion of regular channels
| #define ADC_CR2_SWSTART ((uint32_t)0x00400000) |
Start Conversion of regular channels
| #define ADC_CR2_SWSTART ((uint32_t)0x00400000) |
Start Conversion of regular channels
| #define ADC_CR2_SWSTART ((uint32_t)0x00400000) |
Start Conversion of regular channels
| #define ADC_CR2_SWSTART ((uint32_t)0x00400000) |
Start Conversion of regular channels
| #define ADC_CR2_SWSTART ((uint32_t)0x00400000) |
Start Conversion of regular channels
| #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
| #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
| #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
| #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
| #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
| #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
| #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
| #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
| #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
| #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
| #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
| #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
| #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
| #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
| #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
ADC2 data
| #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
ADC2 data
| #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
ADC2 data
| #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
ADC2 data
| #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
ADC2 data
| #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
ADC2 data
| #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
ADC2 data
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
| #define ADC_HTR_HT ((uint32_t)0x00000FFF) |
Analog watchdog high threshold
| #define ADC_HTR_HT ((uint32_t)0x00000FFF) |
Analog watchdog high threshold
| #define ADC_HTR_HT ((uint32_t)0x00000FFF) |
Analog watchdog high threshold
| #define ADC_HTR_HT ((uint32_t)0x00000FFF) |
Analog watchdog high threshold
| #define ADC_HTR_HT ((uint32_t)0x00000FFF) |
Analog watchdog high threshold
| #define ADC_HTR_HT ((uint32_t)0x00000FFF) |
Analog watchdog high threshold
| #define ADC_HTR_HT ((uint32_t)0x00000FFF) |
Analog watchdog high threshold
| #define ADC_HTR_HT ((uint32_t)0x00000FFF) |
Analog watchdog high threshold
| #define ADC_HTR_HT ((uint32_t)0x00000FFF) |
Analog watchdog high threshold
| #define ADC_HTR_HT ((uint32_t)0x00000FFF) |
Analog watchdog high threshold
| #define ADC_HTR_HT ((uint32_t)0x00000FFF) |
Analog watchdog high threshold
| #define ADC_HTR_HT ((uint32_t)0x00000FFF) |
Analog watchdog high threshold
| #define ADC_HTR_HT ((uint32_t)0x00000FFF) |
Analog watchdog high threshold
| #define ADC_HTR_HT ((uint32_t)0x00000FFF) |
Analog watchdog high threshold
| #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
Injected data
| #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
Data offset for injected channel 1
| #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
Data offset for injected channel 1
| #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
Data offset for injected channel 1
| #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
Data offset for injected channel 1
| #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
Data offset for injected channel 1
| #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
Data offset for injected channel 1
| #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
Data offset for injected channel 1
| #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
Data offset for injected channel 1
| #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
Data offset for injected channel 1
| #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
Data offset for injected channel 1
| #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
Data offset for injected channel 1
| #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
Data offset for injected channel 1
| #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
Data offset for injected channel 1
| #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
Data offset for injected channel 1
| #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
Data offset for injected channel 2
| #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
Data offset for injected channel 2
| #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
Data offset for injected channel 2
| #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
Data offset for injected channel 2
| #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
Data offset for injected channel 2
| #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
Data offset for injected channel 2
| #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
Data offset for injected channel 2
| #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
Data offset for injected channel 2
| #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
Data offset for injected channel 2
| #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
Data offset for injected channel 2
| #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
Data offset for injected channel 2
| #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
Data offset for injected channel 2
| #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
Data offset for injected channel 2
| #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
Data offset for injected channel 2
| #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
Data offset for injected channel 3
| #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
Data offset for injected channel 3
| #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
Data offset for injected channel 3
| #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
Data offset for injected channel 3
| #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
Data offset for injected channel 3
| #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
Data offset for injected channel 3
| #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
Data offset for injected channel 3
| #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
Data offset for injected channel 3
| #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
Data offset for injected channel 3
| #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
Data offset for injected channel 3
| #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
Data offset for injected channel 3
| #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
Data offset for injected channel 3
| #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
Data offset for injected channel 3
| #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
Data offset for injected channel 3
| #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
Data offset for injected channel 4
| #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
Data offset for injected channel 4
| #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
Data offset for injected channel 4
| #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
Data offset for injected channel 4
| #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
Data offset for injected channel 4
| #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
Data offset for injected channel 4
| #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
Data offset for injected channel 4
| #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
Data offset for injected channel 4
| #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
Data offset for injected channel 4
| #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
Data offset for injected channel 4
| #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
Data offset for injected channel 4
| #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
Data offset for injected channel 4
| #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
Data offset for injected channel 4
| #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
Data offset for injected channel 4
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_LTR_LT ((uint32_t)0x00000FFF) |
Analog watchdog low threshold
| #define ADC_LTR_LT ((uint32_t)0x00000FFF) |
Analog watchdog low threshold
| #define ADC_LTR_LT ((uint32_t)0x00000FFF) |
Analog watchdog low threshold
| #define ADC_LTR_LT ((uint32_t)0x00000FFF) |
Analog watchdog low threshold
| #define ADC_LTR_LT ((uint32_t)0x00000FFF) |
Analog watchdog low threshold
| #define ADC_LTR_LT ((uint32_t)0x00000FFF) |
Analog watchdog low threshold
| #define ADC_LTR_LT ((uint32_t)0x00000FFF) |
Analog watchdog low threshold
| #define ADC_LTR_LT ((uint32_t)0x00000FFF) |
Analog watchdog low threshold
| #define ADC_LTR_LT ((uint32_t)0x00000FFF) |
Analog watchdog low threshold
| #define ADC_LTR_LT ((uint32_t)0x00000FFF) |
Analog watchdog low threshold
| #define ADC_LTR_LT ((uint32_t)0x00000FFF) |
Analog watchdog low threshold
| #define ADC_LTR_LT ((uint32_t)0x00000FFF) |
Analog watchdog low threshold
| #define ADC_LTR_LT ((uint32_t)0x00000FFF) |
Analog watchdog low threshold
| #define ADC_LTR_LT ((uint32_t)0x00000FFF) |
Analog watchdog low threshold
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
| #define ADC_SR_AWD ((uint32_t)0x00000001) |
Analog watchdog flag
| #define ADC_SR_AWD ((uint32_t)0x00000001) |
Analog watchdog flag
| #define ADC_SR_AWD ((uint32_t)0x00000001) |
Analog watchdog flag
| #define ADC_SR_AWD ((uint32_t)0x00000001) |
Analog watchdog flag
| #define ADC_SR_AWD ((uint32_t)0x00000001) |
Analog watchdog flag
| #define ADC_SR_AWD ((uint32_t)0x00000001) |
Analog watchdog flag
| #define ADC_SR_AWD ((uint32_t)0x00000001) |
Analog watchdog flag
| #define ADC_SR_AWD ((uint32_t)0x00000001) |
Analog watchdog flag
| #define ADC_SR_AWD ((uint32_t)0x00000001) |
Analog watchdog flag
| #define ADC_SR_AWD ((uint32_t)0x00000001) |
Analog watchdog flag
| #define ADC_SR_AWD ((uint32_t)0x00000001) |
Analog watchdog flag
| #define ADC_SR_AWD ((uint32_t)0x00000001) |
Analog watchdog flag
| #define ADC_SR_AWD ((uint32_t)0x00000001) |
Analog watchdog flag
| #define ADC_SR_AWD ((uint32_t)0x00000001) |
Analog watchdog flag
| #define ADC_SR_EOC ((uint32_t)0x00000002) |
End of conversion
| #define ADC_SR_EOC ((uint32_t)0x00000002) |
End of conversion
| #define ADC_SR_EOC ((uint32_t)0x00000002) |
End of conversion
| #define ADC_SR_EOC ((uint32_t)0x00000002) |
End of conversion
| #define ADC_SR_EOC ((uint32_t)0x00000002) |
End of conversion
| #define ADC_SR_EOC ((uint32_t)0x00000002) |
End of conversion
| #define ADC_SR_EOC ((uint32_t)0x00000002) |
End of conversion
| #define ADC_SR_EOC ((uint32_t)0x00000002) |
End of conversion
| #define ADC_SR_EOC ((uint32_t)0x00000002) |
End of conversion
| #define ADC_SR_EOC ((uint32_t)0x00000002) |
End of conversion
| #define ADC_SR_EOC ((uint32_t)0x00000002) |
End of conversion
| #define ADC_SR_EOC ((uint32_t)0x00000002) |
End of conversion
| #define ADC_SR_EOC ((uint32_t)0x00000002) |
End of conversion
| #define ADC_SR_EOC ((uint32_t)0x00000002) |
End of conversion
| #define ADC_SR_JEOC ((uint32_t)0x00000004) |
Injected channel end of conversion
| #define ADC_SR_JEOC ((uint32_t)0x00000004) |
Injected channel end of conversion
| #define ADC_SR_JEOC ((uint32_t)0x00000004) |
Injected channel end of conversion
| #define ADC_SR_JEOC ((uint32_t)0x00000004) |
Injected channel end of conversion
| #define ADC_SR_JEOC ((uint32_t)0x00000004) |
Injected channel end of conversion
| #define ADC_SR_JEOC ((uint32_t)0x00000004) |
Injected channel end of conversion
| #define ADC_SR_JEOC ((uint32_t)0x00000004) |
Injected channel end of conversion
| #define ADC_SR_JEOC ((uint32_t)0x00000004) |
Injected channel end of conversion
| #define ADC_SR_JEOC ((uint32_t)0x00000004) |
Injected channel end of conversion
| #define ADC_SR_JEOC ((uint32_t)0x00000004) |
Injected channel end of conversion
| #define ADC_SR_JEOC ((uint32_t)0x00000004) |
Injected channel end of conversion
| #define ADC_SR_JEOC ((uint32_t)0x00000004) |
Injected channel end of conversion
| #define ADC_SR_JEOC ((uint32_t)0x00000004) |
Injected channel end of conversion
| #define ADC_SR_JEOC ((uint32_t)0x00000004) |
Injected channel end of conversion
| #define ADC_SR_JSTRT ((uint32_t)0x00000008) |
Injected channel Start flag
| #define ADC_SR_JSTRT ((uint32_t)0x00000008) |
Injected channel Start flag
| #define ADC_SR_JSTRT ((uint32_t)0x00000008) |
Injected channel Start flag
| #define ADC_SR_JSTRT ((uint32_t)0x00000008) |
Injected channel Start flag
| #define ADC_SR_JSTRT ((uint32_t)0x00000008) |
Injected channel Start flag
| #define ADC_SR_JSTRT ((uint32_t)0x00000008) |
Injected channel Start flag
| #define ADC_SR_JSTRT ((uint32_t)0x00000008) |
Injected channel Start flag
| #define ADC_SR_JSTRT ((uint32_t)0x00000008) |
Injected channel Start flag
| #define ADC_SR_JSTRT ((uint32_t)0x00000008) |
Injected channel Start flag
| #define ADC_SR_JSTRT ((uint32_t)0x00000008) |
Injected channel Start flag
| #define ADC_SR_JSTRT ((uint32_t)0x00000008) |
Injected channel Start flag
| #define ADC_SR_JSTRT ((uint32_t)0x00000008) |
Injected channel Start flag
| #define ADC_SR_JSTRT ((uint32_t)0x00000008) |
Injected channel Start flag
| #define ADC_SR_JSTRT ((uint32_t)0x00000008) |
Injected channel Start flag
| #define ADC_SR_STRT ((uint32_t)0x00000010) |
Regular channel Start flag
| #define ADC_SR_STRT ((uint32_t)0x00000010) |
Regular channel Start flag
| #define ADC_SR_STRT ((uint32_t)0x00000010) |
Regular channel Start flag
| #define ADC_SR_STRT ((uint32_t)0x00000010) |
Regular channel Start flag
| #define ADC_SR_STRT ((uint32_t)0x00000010) |
Regular channel Start flag
| #define ADC_SR_STRT ((uint32_t)0x00000010) |
Regular channel Start flag
| #define ADC_SR_STRT ((uint32_t)0x00000010) |
Regular channel Start flag
| #define ADC_SR_STRT ((uint32_t)0x00000010) |
Regular channel Start flag
| #define ADC_SR_STRT ((uint32_t)0x00000010) |
Regular channel Start flag
| #define ADC_SR_STRT ((uint32_t)0x00000010) |
Regular channel Start flag
| #define ADC_SR_STRT ((uint32_t)0x00000010) |
Regular channel Start flag
| #define ADC_SR_STRT ((uint32_t)0x00000010) |
Regular channel Start flag
| #define ADC_SR_STRT ((uint32_t)0x00000010) |
Regular channel Start flag
| #define ADC_SR_STRT ((uint32_t)0x00000010) |
Regular channel Start flag
| #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
Event Output Enable
| #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
Event Output Enable
| #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
Event Output Enable
| #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
Event Output Enable
| #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
Event Output Enable
| #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
Event Output Enable
| #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
Event Output Enable
| #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
Event Output Enable
| #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
Event Output Enable
| #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
Event Output Enable
| #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
Event Output Enable
| #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
Event Output Enable
| #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
Event Output Enable
| #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) |
Event Output Enable
| #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
PIN[3:0] bits (Pin selection)
| #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
PIN[3:0] bits (Pin selection)
| #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
PIN[3:0] bits (Pin selection)
| #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
PIN[3:0] bits (Pin selection)
| #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
PIN[3:0] bits (Pin selection)
| #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
PIN[3:0] bits (Pin selection)
| #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
PIN[3:0] bits (Pin selection)
| #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
PIN[3:0] bits (Pin selection)
| #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
PIN[3:0] bits (Pin selection)
| #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
PIN[3:0] bits (Pin selection)
| #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
PIN[3:0] bits (Pin selection)
| #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
PIN[3:0] bits (Pin selection)
| #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
PIN[3:0] bits (Pin selection)
| #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) |
PIN[3:0] bits (Pin selection)
| #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
Bit 0
| #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
Bit 0
| #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
Bit 0
| #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
Bit 0
| #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
Bit 0
| #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
Bit 0
| #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
Bit 0
| #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
Bit 0
| #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
Bit 0
| #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
Bit 0
| #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
Bit 0
| #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
Bit 0
| #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
Bit 0
| #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) |
Bit 0
| #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
Bit 1
| #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
Bit 1
| #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
Bit 1
| #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
Bit 1
| #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
Bit 1
| #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
Bit 1
| #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
Bit 1
| #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
Bit 1
| #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
Bit 1
| #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
Bit 1
| #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
Bit 1
| #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
Bit 1
| #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
Bit 1
| #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) |
Bit 1
| #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
Bit 2
| #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
Bit 2
| #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
Bit 2
| #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
Bit 2
| #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
Bit 2
| #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
Bit 2
| #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
Bit 2
| #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
Bit 2
| #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
Bit 2
| #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
Bit 2
| #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
Bit 2
| #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
Bit 2
| #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
Bit 2
| #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) |
Bit 2
| #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
Bit 3 PIN configuration
| #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
Bit 3 PIN configuration
| #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
Bit 3 PIN configuration
| #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
Bit 3 PIN configuration
| #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
Bit 3 PIN configuration
| #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
Bit 3 PIN configuration
| #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
Bit 3 PIN configuration
| #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
Bit 3 PIN configuration
| #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
Bit 3 PIN configuration
| #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
Bit 3 PIN configuration
| #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
Bit 3 PIN configuration
| #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
Bit 3 PIN configuration
| #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
Bit 3 PIN configuration
| #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) |
Bit 3 PIN configuration
| #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
Pin 0 selected
| #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
Pin 0 selected
| #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
Pin 0 selected
| #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
Pin 0 selected
| #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
Pin 0 selected
| #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
Pin 0 selected
| #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
Pin 0 selected
| #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
Pin 0 selected
| #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
Pin 0 selected
| #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
Pin 0 selected
| #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
Pin 0 selected
| #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
Pin 0 selected
| #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
Pin 0 selected
| #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) |
Pin 0 selected
| #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
Pin 1 selected
| #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
Pin 1 selected
| #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
Pin 1 selected
| #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
Pin 1 selected
| #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
Pin 1 selected
| #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
Pin 1 selected
| #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
Pin 1 selected
| #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
Pin 1 selected
| #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
Pin 1 selected
| #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
Pin 1 selected
| #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
Pin 1 selected
| #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
Pin 1 selected
| #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
Pin 1 selected
| #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) |
Pin 1 selected
| #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
Pin 10 selected
| #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
Pin 10 selected
| #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
Pin 10 selected
| #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
Pin 10 selected
| #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
Pin 10 selected
| #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
Pin 10 selected
| #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
Pin 10 selected
| #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
Pin 10 selected
| #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
Pin 10 selected
| #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
Pin 10 selected
| #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
Pin 10 selected
| #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
Pin 10 selected
| #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
Pin 10 selected
| #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) |
Pin 10 selected
| #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
Pin 11 selected
| #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
Pin 11 selected
| #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
Pin 11 selected
| #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
Pin 11 selected
| #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
Pin 11 selected
| #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
Pin 11 selected
| #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
Pin 11 selected
| #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
Pin 11 selected
| #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
Pin 11 selected
| #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
Pin 11 selected
| #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
Pin 11 selected
| #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
Pin 11 selected
| #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
Pin 11 selected
| #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) |
Pin 11 selected
| #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
Pin 12 selected
| #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
Pin 12 selected
| #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
Pin 12 selected
| #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
Pin 12 selected
| #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
Pin 12 selected
| #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
Pin 12 selected
| #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
Pin 12 selected
| #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
Pin 12 selected
| #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
Pin 12 selected
| #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
Pin 12 selected
| #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
Pin 12 selected
| #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
Pin 12 selected
| #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
Pin 12 selected
| #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) |
Pin 12 selected
| #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
Pin 13 selected
| #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
Pin 13 selected
| #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
Pin 13 selected
| #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
Pin 13 selected
| #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
Pin 13 selected
| #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
Pin 13 selected
| #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
Pin 13 selected
| #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
Pin 13 selected
| #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
Pin 13 selected
| #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
Pin 13 selected
| #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
Pin 13 selected
| #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
Pin 13 selected
| #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
Pin 13 selected
| #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) |
Pin 13 selected
| #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
Pin 14 selected
| #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
Pin 14 selected
| #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
Pin 14 selected
| #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
Pin 14 selected
| #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
Pin 14 selected
| #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
Pin 14 selected
| #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
Pin 14 selected
| #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
Pin 14 selected
| #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
Pin 14 selected
| #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
Pin 14 selected
| #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
Pin 14 selected
| #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
Pin 14 selected
| #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
Pin 14 selected
| #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) |
Pin 14 selected
| #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
Pin 15 selected
| #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
Pin 15 selected
| #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
Pin 15 selected
| #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
Pin 15 selected
| #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
Pin 15 selected
| #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
Pin 15 selected
| #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
Pin 15 selected
| #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
Pin 15 selected
| #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
Pin 15 selected
| #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
Pin 15 selected
| #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
Pin 15 selected
| #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
Pin 15 selected
| #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
Pin 15 selected
| #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) |
Pin 15 selected
| #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
Pin 2 selected
| #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
Pin 2 selected
| #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
Pin 2 selected
| #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
Pin 2 selected
| #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
Pin 2 selected
| #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
Pin 2 selected
| #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
Pin 2 selected
| #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
Pin 2 selected
| #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
Pin 2 selected
| #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
Pin 2 selected
| #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
Pin 2 selected
| #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
Pin 2 selected
| #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
Pin 2 selected
| #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) |
Pin 2 selected
| #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
Pin 3 selected
| #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
Pin 3 selected
| #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
Pin 3 selected
| #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
Pin 3 selected
| #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
Pin 3 selected
| #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
Pin 3 selected
| #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
Pin 3 selected
| #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
Pin 3 selected
| #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
Pin 3 selected
| #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
Pin 3 selected
| #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
Pin 3 selected
| #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
Pin 3 selected
| #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
Pin 3 selected
| #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) |
Pin 3 selected
| #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
Pin 4 selected
| #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
Pin 4 selected
| #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
Pin 4 selected
| #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
Pin 4 selected
| #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
Pin 4 selected
| #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
Pin 4 selected
| #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
Pin 4 selected
| #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
Pin 4 selected
| #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
Pin 4 selected
| #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
Pin 4 selected
| #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
Pin 4 selected
| #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
Pin 4 selected
| #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
Pin 4 selected
| #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) |
Pin 4 selected
| #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
Pin 5 selected
| #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
Pin 5 selected
| #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
Pin 5 selected
| #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
Pin 5 selected
| #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
Pin 5 selected
| #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
Pin 5 selected
| #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
Pin 5 selected
| #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
Pin 5 selected
| #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
Pin 5 selected
| #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
Pin 5 selected
| #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
Pin 5 selected
| #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
Pin 5 selected
| #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
Pin 5 selected
| #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) |
Pin 5 selected
| #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
Pin 6 selected
| #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
Pin 6 selected
| #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
Pin 6 selected
| #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
Pin 6 selected
| #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
Pin 6 selected
| #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
Pin 6 selected
| #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
Pin 6 selected
| #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
Pin 6 selected
| #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
Pin 6 selected
| #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
Pin 6 selected
| #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
Pin 6 selected
| #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
Pin 6 selected
| #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
Pin 6 selected
| #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) |
Pin 6 selected
| #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
Pin 7 selected
| #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
Pin 7 selected
| #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
Pin 7 selected
| #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
Pin 7 selected
| #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
Pin 7 selected
| #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
Pin 7 selected
| #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
Pin 7 selected
| #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
Pin 7 selected
| #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
Pin 7 selected
| #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
Pin 7 selected
| #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
Pin 7 selected
| #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
Pin 7 selected
| #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
Pin 7 selected
| #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) |
Pin 7 selected
| #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
Pin 8 selected
| #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
Pin 8 selected
| #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
Pin 8 selected
| #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
Pin 8 selected
| #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
Pin 8 selected
| #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
Pin 8 selected
| #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
Pin 8 selected
| #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
Pin 8 selected
| #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
Pin 8 selected
| #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
Pin 8 selected
| #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
Pin 8 selected
| #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
Pin 8 selected
| #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
Pin 8 selected
| #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) |
Pin 8 selected
| #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
Pin 9 selected
| #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
Pin 9 selected
| #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
Pin 9 selected
| #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
Pin 9 selected
| #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
Pin 9 selected
| #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
Pin 9 selected
| #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
Pin 9 selected
| #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
Pin 9 selected
| #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
Pin 9 selected
| #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
Pin 9 selected
| #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
Pin 9 selected
| #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
Pin 9 selected
| #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
Pin 9 selected
| #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) |
Pin 9 selected
| #define AFIO_EVCR_PORT ((uint32_t)0x00000070) |
PORT[2:0] bits (Port selection)
| #define AFIO_EVCR_PORT ((uint32_t)0x00000070) |
PORT[2:0] bits (Port selection)
| #define AFIO_EVCR_PORT ((uint32_t)0x00000070) |
PORT[2:0] bits (Port selection)
| #define AFIO_EVCR_PORT ((uint32_t)0x00000070) |
PORT[2:0] bits (Port selection)
| #define AFIO_EVCR_PORT ((uint32_t)0x00000070) |
PORT[2:0] bits (Port selection)
| #define AFIO_EVCR_PORT ((uint32_t)0x00000070) |
PORT[2:0] bits (Port selection)
| #define AFIO_EVCR_PORT ((uint32_t)0x00000070) |
PORT[2:0] bits (Port selection)
| #define AFIO_EVCR_PORT ((uint32_t)0x00000070) |
PORT[2:0] bits (Port selection)
| #define AFIO_EVCR_PORT ((uint32_t)0x00000070) |
PORT[2:0] bits (Port selection)
| #define AFIO_EVCR_PORT ((uint32_t)0x00000070) |
PORT[2:0] bits (Port selection)
| #define AFIO_EVCR_PORT ((uint32_t)0x00000070) |
PORT[2:0] bits (Port selection)
| #define AFIO_EVCR_PORT ((uint32_t)0x00000070) |
PORT[2:0] bits (Port selection)
| #define AFIO_EVCR_PORT ((uint32_t)0x00000070) |
PORT[2:0] bits (Port selection)
| #define AFIO_EVCR_PORT ((uint32_t)0x00000070) |
PORT[2:0] bits (Port selection)
| #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
Bit 2 PORT configuration
| #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
Bit 2 PORT configuration
| #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
Bit 2 PORT configuration
| #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
Bit 2 PORT configuration
| #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
Bit 2 PORT configuration
| #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
Bit 2 PORT configuration
| #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
Bit 2 PORT configuration
| #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
Bit 2 PORT configuration
| #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
Bit 2 PORT configuration
| #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
Bit 2 PORT configuration
| #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
Bit 2 PORT configuration
| #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
Bit 2 PORT configuration
| #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
Bit 2 PORT configuration
| #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) |
Bit 2 PORT configuration
| #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
Port A selected
| #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
Port A selected
| #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
Port A selected
| #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
Port A selected
| #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
Port A selected
| #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
Port A selected
| #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
Port A selected
| #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
Port A selected
| #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
Port A selected
| #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
Port A selected
| #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
Port A selected
| #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
Port A selected
| #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
Port A selected
| #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) |
Port A selected
| #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
Port B selected
| #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
Port B selected
| #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
Port B selected
| #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
Port B selected
| #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
Port B selected
| #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
Port B selected
| #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
Port B selected
| #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
Port B selected
| #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
Port B selected
| #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
Port B selected
| #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
Port B selected
| #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
Port B selected
| #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
Port B selected
| #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) |
Port B selected
| #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
Port C selected
| #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
Port C selected
| #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
Port C selected
| #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
Port C selected
| #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
Port C selected
| #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
Port C selected
| #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
Port C selected
| #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
Port C selected
| #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
Port C selected
| #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
Port C selected
| #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
Port C selected
| #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
Port C selected
| #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
Port C selected
| #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) |
Port C selected
| #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
Port D selected
| #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
Port D selected
| #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
Port D selected
| #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
Port D selected
| #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
Port D selected
| #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
Port D selected
| #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
Port D selected
| #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
Port D selected
| #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
Port D selected
| #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
Port D selected
| #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
Port D selected
| #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
Port D selected
| #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
Port D selected
| #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) |
Port D selected
| #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
Port E selected
| #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
Port E selected
| #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
Port E selected
| #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
Port E selected
| #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
Port E selected
| #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
Port E selected
| #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
Port E selected
| #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
Port E selected
| #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
Port E selected
| #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
Port E selected
| #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
Port E selected
| #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
Port E selected
| #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
Port E selected
| #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) |
Port E selected
| #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
EXTI 0 configuration
| #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
EXTI 0 configuration
| #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
EXTI 0 configuration
| #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
EXTI 0 configuration
| #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
EXTI 0 configuration
| #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
EXTI 0 configuration
| #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
EXTI 0 configuration
| #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
EXTI 0 configuration
| #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
EXTI 0 configuration
| #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
EXTI 0 configuration
| #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
EXTI 0 configuration
| #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
EXTI 0 configuration
| #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
EXTI 0 configuration
| #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) |
EXTI 0 configuration
| #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
PA[0] pin
| #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
PA[0] pin
| #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
PA[0] pin
| #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
PA[0] pin
| #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
PA[0] pin
| #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
PA[0] pin
| #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
PA[0] pin
| #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
PA[0] pin
| #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
PA[0] pin
| #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
PA[0] pin
| #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
PA[0] pin
| #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
PA[0] pin
| #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
PA[0] pin
| #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) |
PA[0] pin
| #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
PB[0] pin
| #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
PB[0] pin
| #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
PB[0] pin
| #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
PB[0] pin
| #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
PB[0] pin
| #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
PB[0] pin
| #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
PB[0] pin
| #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
PB[0] pin
| #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
PB[0] pin
| #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
PB[0] pin
| #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
PB[0] pin
| #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
PB[0] pin
| #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
PB[0] pin
| #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) |
PB[0] pin
| #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
PC[0] pin
| #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
PC[0] pin
| #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
PC[0] pin
| #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
PC[0] pin
| #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
PC[0] pin
| #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
PC[0] pin
| #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
PC[0] pin
| #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
PC[0] pin
| #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
PC[0] pin
| #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
PC[0] pin
| #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
PC[0] pin
| #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
PC[0] pin
| #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
PC[0] pin
| #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) |
PC[0] pin
| #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
PD[0] pin
| #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
PD[0] pin
| #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
PD[0] pin
| #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
PD[0] pin
| #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
PD[0] pin
| #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
PD[0] pin
| #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
PD[0] pin
| #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
PD[0] pin
| #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
PD[0] pin
| #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
PD[0] pin
| #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
PD[0] pin
| #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
PD[0] pin
| #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
PD[0] pin
| #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) |
PD[0] pin
| #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
PE[0] pin
| #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
PE[0] pin
| #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
PE[0] pin
| #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
PE[0] pin
| #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
PE[0] pin
| #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
PE[0] pin
| #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
PE[0] pin
| #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
PE[0] pin
| #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
PE[0] pin
| #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
PE[0] pin
| #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
PE[0] pin
| #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
PE[0] pin
| #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
PE[0] pin
| #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) |
PE[0] pin
| #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
PF[0] pin
| #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
PF[0] pin
| #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
PF[0] pin
| #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
PF[0] pin
| #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
PF[0] pin
| #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
PF[0] pin
| #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
PF[0] pin
| #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
PF[0] pin
| #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
PF[0] pin
| #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
PF[0] pin
| #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
PF[0] pin
| #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
PF[0] pin
| #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
PF[0] pin
| #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) |
PF[0] pin
| #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
PG[0] pin EXTI1 configuration
| #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
PG[0] pin EXTI1 configuration
| #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
PG[0] pin EXTI1 configuration
| #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
PG[0] pin EXTI1 configuration
| #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
PG[0] pin EXTI1 configuration
| #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
PG[0] pin EXTI1 configuration
| #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
PG[0] pin EXTI1 configuration
| #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
PG[0] pin EXTI1 configuration
| #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
PG[0] pin EXTI1 configuration
| #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
PG[0] pin EXTI1 configuration
| #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
PG[0] pin EXTI1 configuration
| #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
PG[0] pin EXTI1 configuration
| #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
PG[0] pin EXTI1 configuration
| #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) |
PG[0] pin EXTI1 configuration
| #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
EXTI 1 configuration
| #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
EXTI 1 configuration
| #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
EXTI 1 configuration
| #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
EXTI 1 configuration
| #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
EXTI 1 configuration
| #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
EXTI 1 configuration
| #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
EXTI 1 configuration
| #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
EXTI 1 configuration
| #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
EXTI 1 configuration
| #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
EXTI 1 configuration
| #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
EXTI 1 configuration
| #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
EXTI 1 configuration
| #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
EXTI 1 configuration
| #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) |
EXTI 1 configuration
| #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
PA[1] pin
| #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
PA[1] pin
| #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
PA[1] pin
| #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
PA[1] pin
| #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
PA[1] pin
| #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
PA[1] pin
| #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
PA[1] pin
| #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
PA[1] pin
| #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
PA[1] pin
| #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
PA[1] pin
| #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
PA[1] pin
| #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
PA[1] pin
| #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
PA[1] pin
| #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) |
PA[1] pin
| #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
PB[1] pin
| #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
PB[1] pin
| #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
PB[1] pin
| #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
PB[1] pin
| #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
PB[1] pin
| #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
PB[1] pin
| #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
PB[1] pin
| #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
PB[1] pin
| #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
PB[1] pin
| #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
PB[1] pin
| #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
PB[1] pin
| #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
PB[1] pin
| #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
PB[1] pin
| #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) |
PB[1] pin
| #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
PC[1] pin
| #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
PC[1] pin
| #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
PC[1] pin
| #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
PC[1] pin
| #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
PC[1] pin
| #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
PC[1] pin
| #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
PC[1] pin
| #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
PC[1] pin
| #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
PC[1] pin
| #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
PC[1] pin
| #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
PC[1] pin
| #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
PC[1] pin
| #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
PC[1] pin
| #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) |
PC[1] pin
| #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
PD[1] pin
| #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
PD[1] pin
| #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
PD[1] pin
| #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
PD[1] pin
| #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
PD[1] pin
| #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
PD[1] pin
| #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
PD[1] pin
| #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
PD[1] pin
| #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
PD[1] pin
| #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
PD[1] pin
| #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
PD[1] pin
| #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
PD[1] pin
| #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
PD[1] pin
| #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) |
PD[1] pin
| #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
PE[1] pin
| #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
PE[1] pin
| #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
PE[1] pin
| #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
PE[1] pin
| #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
PE[1] pin
| #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
PE[1] pin
| #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
PE[1] pin
| #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
PE[1] pin
| #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
PE[1] pin
| #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
PE[1] pin
| #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
PE[1] pin
| #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
PE[1] pin
| #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
PE[1] pin
| #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) |
PE[1] pin
| #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
PF[1] pin
| #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
PF[1] pin
| #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
PF[1] pin
| #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
PF[1] pin
| #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
PF[1] pin
| #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
PF[1] pin
| #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
PF[1] pin
| #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
PF[1] pin
| #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
PF[1] pin
| #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
PF[1] pin
| #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
PF[1] pin
| #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
PF[1] pin
| #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
PF[1] pin
| #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) |
PF[1] pin
| #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
PG[1] pin EXTI2 configuration
| #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
PG[1] pin EXTI2 configuration
| #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
PG[1] pin EXTI2 configuration
| #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
PG[1] pin EXTI2 configuration
| #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
PG[1] pin EXTI2 configuration
| #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
PG[1] pin EXTI2 configuration
| #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
PG[1] pin EXTI2 configuration
| #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
PG[1] pin EXTI2 configuration
| #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
PG[1] pin EXTI2 configuration
| #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
PG[1] pin EXTI2 configuration
| #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
PG[1] pin EXTI2 configuration
| #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
PG[1] pin EXTI2 configuration
| #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
PG[1] pin EXTI2 configuration
| #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) |
PG[1] pin EXTI2 configuration
| #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
EXTI 2 configuration
| #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
EXTI 2 configuration
| #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
EXTI 2 configuration
| #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
EXTI 2 configuration
| #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
EXTI 2 configuration
| #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
EXTI 2 configuration
| #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
EXTI 2 configuration
| #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
EXTI 2 configuration
| #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
EXTI 2 configuration
| #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
EXTI 2 configuration
| #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
EXTI 2 configuration
| #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
EXTI 2 configuration
| #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
EXTI 2 configuration
| #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) |
EXTI 2 configuration
| #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
PA[2] pin
| #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
PA[2] pin
| #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
PA[2] pin
| #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
PA[2] pin
| #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
PA[2] pin
| #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
PA[2] pin
| #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
PA[2] pin
| #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
PA[2] pin
| #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
PA[2] pin
| #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
PA[2] pin
| #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
PA[2] pin
| #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
PA[2] pin
| #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
PA[2] pin
| #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) |
PA[2] pin
| #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
PB[2] pin
| #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
PB[2] pin
| #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
PB[2] pin
| #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
PB[2] pin
| #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
PB[2] pin
| #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
PB[2] pin
| #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
PB[2] pin
| #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
PB[2] pin
| #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
PB[2] pin
| #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
PB[2] pin
| #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
PB[2] pin
| #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
PB[2] pin
| #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
PB[2] pin
| #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) |
PB[2] pin
| #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
PC[2] pin
| #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
PC[2] pin
| #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
PC[2] pin
| #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
PC[2] pin
| #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
PC[2] pin
| #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
PC[2] pin
| #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
PC[2] pin
| #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
PC[2] pin
| #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
PC[2] pin
| #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
PC[2] pin
| #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
PC[2] pin
| #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
PC[2] pin
| #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
PC[2] pin
| #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) |
PC[2] pin
| #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
PD[2] pin
| #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
PD[2] pin
| #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
PD[2] pin
| #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
PD[2] pin
| #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
PD[2] pin
| #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
PD[2] pin
| #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
PD[2] pin
| #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
PD[2] pin
| #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
PD[2] pin
| #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
PD[2] pin
| #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
PD[2] pin
| #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
PD[2] pin
| #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
PD[2] pin
| #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) |
PD[2] pin
| #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
PE[2] pin
| #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
PE[2] pin
| #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
PE[2] pin
| #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
PE[2] pin
| #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
PE[2] pin
| #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
PE[2] pin
| #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
PE[2] pin
| #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
PE[2] pin
| #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
PE[2] pin
| #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
PE[2] pin
| #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
PE[2] pin
| #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
PE[2] pin
| #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
PE[2] pin
| #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) |
PE[2] pin
| #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
PF[2] pin
| #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
PF[2] pin
| #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
PF[2] pin
| #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
PF[2] pin
| #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
PF[2] pin
| #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
PF[2] pin
| #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
PF[2] pin
| #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
PF[2] pin
| #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
PF[2] pin
| #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
PF[2] pin
| #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
PF[2] pin
| #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
PF[2] pin
| #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
PF[2] pin
| #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) |
PF[2] pin
| #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
PG[2] pin EXTI3 configuration
| #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
PG[2] pin EXTI3 configuration
| #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
PG[2] pin EXTI3 configuration
| #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
PG[2] pin EXTI3 configuration
| #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
PG[2] pin EXTI3 configuration
| #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
PG[2] pin EXTI3 configuration
| #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
PG[2] pin EXTI3 configuration
| #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
PG[2] pin EXTI3 configuration
| #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
PG[2] pin EXTI3 configuration
| #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
PG[2] pin EXTI3 configuration
| #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
PG[2] pin EXTI3 configuration
| #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
PG[2] pin EXTI3 configuration
| #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
PG[2] pin EXTI3 configuration
| #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) |
PG[2] pin EXTI3 configuration
| #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
EXTI 3 configuration EXTI0 configuration
| #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
EXTI 3 configuration EXTI0 configuration
| #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
EXTI 3 configuration EXTI0 configuration
| #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
EXTI 3 configuration EXTI0 configuration
| #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
EXTI 3 configuration EXTI0 configuration
| #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
EXTI 3 configuration EXTI0 configuration
| #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
EXTI 3 configuration EXTI0 configuration
| #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
EXTI 3 configuration EXTI0 configuration
| #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
EXTI 3 configuration EXTI0 configuration
| #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
EXTI 3 configuration EXTI0 configuration
| #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
EXTI 3 configuration EXTI0 configuration
| #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
EXTI 3 configuration EXTI0 configuration
| #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
EXTI 3 configuration EXTI0 configuration
| #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) |
EXTI 3 configuration EXTI0 configuration
| #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
PA[3] pin
| #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
PA[3] pin
| #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
PA[3] pin
| #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
PA[3] pin
| #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
PA[3] pin
| #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
PA[3] pin
| #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
PA[3] pin
| #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
PA[3] pin
| #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
PA[3] pin
| #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
PA[3] pin
| #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
PA[3] pin
| #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
PA[3] pin
| #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
PA[3] pin
| #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) |
PA[3] pin
| #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
PB[3] pin
| #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
PB[3] pin
| #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
PB[3] pin
| #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
PB[3] pin
| #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
PB[3] pin
| #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
PB[3] pin
| #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
PB[3] pin
| #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
PB[3] pin
| #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
PB[3] pin
| #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
PB[3] pin
| #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
PB[3] pin
| #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
PB[3] pin
| #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
PB[3] pin
| #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) |
PB[3] pin
| #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
PC[3] pin
| #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
PC[3] pin
| #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
PC[3] pin
| #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
PC[3] pin
| #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
PC[3] pin
| #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
PC[3] pin
| #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
PC[3] pin
| #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
PC[3] pin
| #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
PC[3] pin
| #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
PC[3] pin
| #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
PC[3] pin
| #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
PC[3] pin
| #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
PC[3] pin
| #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) |
PC[3] pin
| #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
PD[3] pin
| #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
PD[3] pin
| #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
PD[3] pin
| #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
PD[3] pin
| #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
PD[3] pin
| #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
PD[3] pin
| #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
PD[3] pin
| #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
PD[3] pin
| #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
PD[3] pin
| #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
PD[3] pin
| #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
PD[3] pin
| #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
PD[3] pin
| #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
PD[3] pin
| #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) |
PD[3] pin
| #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
PE[3] pin
| #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
PE[3] pin
| #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
PE[3] pin
| #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
PE[3] pin
| #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
PE[3] pin
| #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
PE[3] pin
| #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
PE[3] pin
| #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
PE[3] pin
| #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
PE[3] pin
| #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
PE[3] pin
| #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
PE[3] pin
| #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
PE[3] pin
| #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
PE[3] pin
| #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) |
PE[3] pin
| #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
PF[3] pin
| #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
PF[3] pin
| #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
PF[3] pin
| #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
PF[3] pin
| #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
PF[3] pin
| #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
PF[3] pin
| #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
PF[3] pin
| #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
PF[3] pin
| #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
PF[3] pin
| #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
PF[3] pin
| #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
PF[3] pin
| #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
PF[3] pin
| #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
PF[3] pin
| #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) |
PF[3] pin
| #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
PG[3] pin
| #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
PG[3] pin
| #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
PG[3] pin
| #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
PG[3] pin
| #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
PG[3] pin
| #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
PG[3] pin
| #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
PG[3] pin
| #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
PG[3] pin
| #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
PG[3] pin
| #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
PG[3] pin
| #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
PG[3] pin
| #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
PG[3] pin
| #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
PG[3] pin
| #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) |
PG[3] pin
| #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
EXTI 4 configuration
| #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
EXTI 4 configuration
| #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
EXTI 4 configuration
| #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
EXTI 4 configuration
| #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
EXTI 4 configuration
| #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
EXTI 4 configuration
| #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
EXTI 4 configuration
| #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
EXTI 4 configuration
| #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
EXTI 4 configuration
| #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
EXTI 4 configuration
| #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
EXTI 4 configuration
| #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
EXTI 4 configuration
| #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
EXTI 4 configuration
| #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) |
EXTI 4 configuration
| #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
PA[4] pin
| #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
PA[4] pin
| #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
PA[4] pin
| #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
PA[4] pin
| #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
PA[4] pin
| #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
PA[4] pin
| #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
PA[4] pin
| #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
PA[4] pin
| #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
PA[4] pin
| #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
PA[4] pin
| #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
PA[4] pin
| #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
PA[4] pin
| #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
PA[4] pin
| #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) |
PA[4] pin
| #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
PB[4] pin
| #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
PB[4] pin
| #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
PB[4] pin
| #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
PB[4] pin
| #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
PB[4] pin
| #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
PB[4] pin
| #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
PB[4] pin
| #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
PB[4] pin
| #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
PB[4] pin
| #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
PB[4] pin
| #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
PB[4] pin
| #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
PB[4] pin
| #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
PB[4] pin
| #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) |
PB[4] pin
| #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
PC[4] pin
| #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
PC[4] pin
| #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
PC[4] pin
| #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
PC[4] pin
| #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
PC[4] pin
| #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
PC[4] pin
| #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
PC[4] pin
| #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
PC[4] pin
| #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
PC[4] pin
| #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
PC[4] pin
| #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
PC[4] pin
| #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
PC[4] pin
| #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
PC[4] pin
| #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) |
PC[4] pin
| #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
PD[4] pin
| #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
PD[4] pin
| #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
PD[4] pin
| #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
PD[4] pin
| #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
PD[4] pin
| #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
PD[4] pin
| #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
PD[4] pin
| #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
PD[4] pin
| #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
PD[4] pin
| #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
PD[4] pin
| #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
PD[4] pin
| #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
PD[4] pin
| #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
PD[4] pin
| #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) |
PD[4] pin
| #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
PE[4] pin
| #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
PE[4] pin
| #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
PE[4] pin
| #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
PE[4] pin
| #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
PE[4] pin
| #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
PE[4] pin
| #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
PE[4] pin
| #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
PE[4] pin
| #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
PE[4] pin
| #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
PE[4] pin
| #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
PE[4] pin
| #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
PE[4] pin
| #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
PE[4] pin
| #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) |
PE[4] pin
| #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
PF[4] pin
| #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
PF[4] pin
| #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
PF[4] pin
| #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
PF[4] pin
| #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
PF[4] pin
| #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
PF[4] pin
| #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
PF[4] pin
| #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
PF[4] pin
| #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
PF[4] pin
| #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
PF[4] pin
| #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
PF[4] pin
| #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
PF[4] pin
| #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
PF[4] pin
| #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) |
PF[4] pin
| #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
PG[4] pin
| #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
PG[4] pin
| #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
PG[4] pin
| #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
PG[4] pin
| #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
PG[4] pin
| #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
PG[4] pin
| #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
PG[4] pin
| #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
PG[4] pin
| #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
PG[4] pin
| #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
PG[4] pin
| #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
PG[4] pin
| #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
PG[4] pin
| #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
PG[4] pin
| #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) |
PG[4] pin
| #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
EXTI 5 configuration
| #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
EXTI 5 configuration
| #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
EXTI 5 configuration
| #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
EXTI 5 configuration
| #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
EXTI 5 configuration
| #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
EXTI 5 configuration
| #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
EXTI 5 configuration
| #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
EXTI 5 configuration
| #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
EXTI 5 configuration
| #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
EXTI 5 configuration
| #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
EXTI 5 configuration
| #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
EXTI 5 configuration
| #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
EXTI 5 configuration
| #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) |
EXTI 5 configuration
| #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
PA[5] pin
| #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
PA[5] pin
| #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
PA[5] pin
| #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
PA[5] pin
| #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
PA[5] pin
| #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
PA[5] pin
| #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
PA[5] pin
| #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
PA[5] pin
| #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
PA[5] pin
| #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
PA[5] pin
| #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
PA[5] pin
| #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
PA[5] pin
| #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
PA[5] pin
| #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) |
PA[5] pin
| #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
PB[5] pin
| #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
PB[5] pin
| #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
PB[5] pin
| #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
PB[5] pin
| #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
PB[5] pin
| #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
PB[5] pin
| #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
PB[5] pin
| #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
PB[5] pin
| #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
PB[5] pin
| #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
PB[5] pin
| #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
PB[5] pin
| #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
PB[5] pin
| #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
PB[5] pin
| #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) |
PB[5] pin
| #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
PC[5] pin
| #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
PC[5] pin
| #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
PC[5] pin
| #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
PC[5] pin
| #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
PC[5] pin
| #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
PC[5] pin
| #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
PC[5] pin
| #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
PC[5] pin
| #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
PC[5] pin
| #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
PC[5] pin
| #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
PC[5] pin
| #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
PC[5] pin
| #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
PC[5] pin
| #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) |
PC[5] pin
| #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
PD[5] pin
| #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
PD[5] pin
| #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
PD[5] pin
| #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
PD[5] pin
| #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
PD[5] pin
| #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
PD[5] pin
| #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
PD[5] pin
| #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
PD[5] pin
| #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
PD[5] pin
| #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
PD[5] pin
| #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
PD[5] pin
| #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
PD[5] pin
| #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
PD[5] pin
| #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) |
PD[5] pin
| #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
PE[5] pin
| #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
PE[5] pin
| #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
PE[5] pin
| #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
PE[5] pin
| #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
PE[5] pin
| #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
PE[5] pin
| #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
PE[5] pin
| #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
PE[5] pin
| #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
PE[5] pin
| #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
PE[5] pin
| #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
PE[5] pin
| #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
PE[5] pin
| #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
PE[5] pin
| #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) |
PE[5] pin
| #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
PF[5] pin
| #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
PF[5] pin
| #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
PF[5] pin
| #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
PF[5] pin
| #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
PF[5] pin
| #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
PF[5] pin
| #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
PF[5] pin
| #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
PF[5] pin
| #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
PF[5] pin
| #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
PF[5] pin
| #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
PF[5] pin
| #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
PF[5] pin
| #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
PF[5] pin
| #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) |
PF[5] pin
| #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
PG[5] pin EXTI6 configuration
| #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
PG[5] pin EXTI6 configuration
| #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
PG[5] pin EXTI6 configuration
| #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
PG[5] pin EXTI6 configuration
| #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
PG[5] pin EXTI6 configuration
| #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
PG[5] pin EXTI6 configuration
| #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
PG[5] pin EXTI6 configuration
| #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
PG[5] pin EXTI6 configuration
| #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
PG[5] pin EXTI6 configuration
| #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
PG[5] pin EXTI6 configuration
| #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
PG[5] pin EXTI6 configuration
| #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
PG[5] pin EXTI6 configuration
| #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
PG[5] pin EXTI6 configuration
| #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) |
PG[5] pin EXTI6 configuration
| #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
EXTI 6 configuration
| #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
EXTI 6 configuration
| #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
EXTI 6 configuration
| #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
EXTI 6 configuration
| #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
EXTI 6 configuration
| #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
EXTI 6 configuration
| #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
EXTI 6 configuration
| #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
EXTI 6 configuration
| #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
EXTI 6 configuration
| #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
EXTI 6 configuration
| #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
EXTI 6 configuration
| #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
EXTI 6 configuration
| #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
EXTI 6 configuration
| #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) |
EXTI 6 configuration
| #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
PA[6] pin
| #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
PA[6] pin
| #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
PA[6] pin
| #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
PA[6] pin
| #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
PA[6] pin
| #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
PA[6] pin
| #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
PA[6] pin
| #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
PA[6] pin
| #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
PA[6] pin
| #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
PA[6] pin
| #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
PA[6] pin
| #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
PA[6] pin
| #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
PA[6] pin
| #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) |
PA[6] pin
| #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
PB[6] pin
| #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
PB[6] pin
| #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
PB[6] pin
| #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
PB[6] pin
| #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
PB[6] pin
| #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
PB[6] pin
| #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
PB[6] pin
| #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
PB[6] pin
| #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
PB[6] pin
| #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
PB[6] pin
| #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
PB[6] pin
| #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
PB[6] pin
| #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
PB[6] pin
| #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) |
PB[6] pin
| #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
PC[6] pin
| #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
PC[6] pin
| #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
PC[6] pin
| #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
PC[6] pin
| #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
PC[6] pin
| #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
PC[6] pin
| #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
PC[6] pin
| #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
PC[6] pin
| #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
PC[6] pin
| #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
PC[6] pin
| #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
PC[6] pin
| #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
PC[6] pin
| #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
PC[6] pin
| #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) |
PC[6] pin
| #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
PD[6] pin
| #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
PD[6] pin
| #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
PD[6] pin
| #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
PD[6] pin
| #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
PD[6] pin
| #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
PD[6] pin
| #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
PD[6] pin
| #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
PD[6] pin
| #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
PD[6] pin
| #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
PD[6] pin
| #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
PD[6] pin
| #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
PD[6] pin
| #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
PD[6] pin
| #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) |
PD[6] pin
| #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
PE[6] pin
| #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
PE[6] pin
| #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
PE[6] pin
| #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
PE[6] pin
| #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
PE[6] pin
| #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
PE[6] pin
| #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
PE[6] pin
| #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
PE[6] pin
| #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
PE[6] pin
| #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
PE[6] pin
| #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
PE[6] pin
| #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
PE[6] pin
| #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
PE[6] pin
| #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) |
PE[6] pin
| #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
PF[6] pin
| #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
PF[6] pin
| #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
PF[6] pin
| #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
PF[6] pin
| #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
PF[6] pin
| #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
PF[6] pin
| #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
PF[6] pin
| #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
PF[6] pin
| #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
PF[6] pin
| #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
PF[6] pin
| #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
PF[6] pin
| #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
PF[6] pin
| #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
PF[6] pin
| #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) |
PF[6] pin
| #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
PG[6] pin EXTI7 configuration
| #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
PG[6] pin EXTI7 configuration
| #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
PG[6] pin EXTI7 configuration
| #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
PG[6] pin EXTI7 configuration
| #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
PG[6] pin EXTI7 configuration
| #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
PG[6] pin EXTI7 configuration
| #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
PG[6] pin EXTI7 configuration
| #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
PG[6] pin EXTI7 configuration
| #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
PG[6] pin EXTI7 configuration
| #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
PG[6] pin EXTI7 configuration
| #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
PG[6] pin EXTI7 configuration
| #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
PG[6] pin EXTI7 configuration
| #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
PG[6] pin EXTI7 configuration
| #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) |
PG[6] pin EXTI7 configuration
| #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
EXTI 7 configuration EXTI4 configuration
| #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
EXTI 7 configuration EXTI4 configuration
| #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
EXTI 7 configuration EXTI4 configuration
| #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
EXTI 7 configuration EXTI4 configuration
| #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
EXTI 7 configuration EXTI4 configuration
| #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
EXTI 7 configuration EXTI4 configuration
| #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
EXTI 7 configuration EXTI4 configuration
| #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
EXTI 7 configuration EXTI4 configuration
| #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
EXTI 7 configuration EXTI4 configuration
| #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
EXTI 7 configuration EXTI4 configuration
| #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
EXTI 7 configuration EXTI4 configuration
| #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
EXTI 7 configuration EXTI4 configuration
| #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
EXTI 7 configuration EXTI4 configuration
| #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) |
EXTI 7 configuration EXTI4 configuration
| #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
PA[7] pin
| #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
PA[7] pin
| #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
PA[7] pin
| #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
PA[7] pin
| #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
PA[7] pin
| #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
PA[7] pin
| #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
PA[7] pin
| #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
PA[7] pin
| #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
PA[7] pin
| #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
PA[7] pin
| #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
PA[7] pin
| #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
PA[7] pin
| #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
PA[7] pin
| #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) |
PA[7] pin
| #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
PB[7] pin
| #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
PB[7] pin
| #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
PB[7] pin
| #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
PB[7] pin
| #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
PB[7] pin
| #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
PB[7] pin
| #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
PB[7] pin
| #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
PB[7] pin
| #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
PB[7] pin
| #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
PB[7] pin
| #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
PB[7] pin
| #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
PB[7] pin
| #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
PB[7] pin
| #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) |
PB[7] pin
| #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
PC[7] pin
| #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
PC[7] pin
| #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
PC[7] pin
| #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
PC[7] pin
| #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
PC[7] pin
| #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
PC[7] pin
| #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
PC[7] pin
| #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
PC[7] pin
| #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
PC[7] pin
| #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
PC[7] pin
| #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
PC[7] pin
| #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
PC[7] pin
| #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
PC[7] pin
| #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) |
PC[7] pin
| #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
PD[7] pin
| #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
PD[7] pin
| #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
PD[7] pin
| #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
PD[7] pin
| #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
PD[7] pin
| #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
PD[7] pin
| #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
PD[7] pin
| #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
PD[7] pin
| #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
PD[7] pin
| #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
PD[7] pin
| #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
PD[7] pin
| #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
PD[7] pin
| #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
PD[7] pin
| #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) |
PD[7] pin
| #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
PE[7] pin
| #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
PE[7] pin
| #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
PE[7] pin
| #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
PE[7] pin
| #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
PE[7] pin
| #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
PE[7] pin
| #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
PE[7] pin
| #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
PE[7] pin
| #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
PE[7] pin
| #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
PE[7] pin
| #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
PE[7] pin
| #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
PE[7] pin
| #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
PE[7] pin
| #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) |
PE[7] pin
| #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
PF[7] pin
| #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
PF[7] pin
| #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
PF[7] pin
| #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
PF[7] pin
| #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
PF[7] pin
| #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
PF[7] pin
| #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
PF[7] pin
| #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
PF[7] pin
| #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
PF[7] pin
| #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
PF[7] pin
| #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
PF[7] pin
| #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
PF[7] pin
| #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
PF[7] pin
| #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) |
PF[7] pin
| #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
PG[7] pin
| #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
PG[7] pin
| #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
PG[7] pin
| #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
PG[7] pin
| #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
PG[7] pin
| #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
PG[7] pin
| #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
PG[7] pin
| #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
PG[7] pin
| #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
PG[7] pin
| #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
PG[7] pin
| #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
PG[7] pin
| #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
PG[7] pin
| #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
PG[7] pin
| #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) |
PG[7] pin
| #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
EXTI 10 configuration
| #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
EXTI 10 configuration
| #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
EXTI 10 configuration
| #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
EXTI 10 configuration
| #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
EXTI 10 configuration
| #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
EXTI 10 configuration
| #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
EXTI 10 configuration
| #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
EXTI 10 configuration
| #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
EXTI 10 configuration
| #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
EXTI 10 configuration
| #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
EXTI 10 configuration
| #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
EXTI 10 configuration
| #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
EXTI 10 configuration
| #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) |
EXTI 10 configuration
| #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
PA[10] pin
| #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
PA[10] pin
| #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
PA[10] pin
| #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
PA[10] pin
| #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
PA[10] pin
| #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
PA[10] pin
| #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
PA[10] pin
| #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
PA[10] pin
| #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
PA[10] pin
| #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
PA[10] pin
| #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
PA[10] pin
| #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
PA[10] pin
| #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
PA[10] pin
| #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) |
PA[10] pin
| #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
PB[10] pin
| #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
PB[10] pin
| #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
PB[10] pin
| #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
PB[10] pin
| #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
PB[10] pin
| #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
PB[10] pin
| #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
PB[10] pin
| #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
PB[10] pin
| #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
PB[10] pin
| #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
PB[10] pin
| #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
PB[10] pin
| #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
PB[10] pin
| #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
PB[10] pin
| #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) |
PB[10] pin
| #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
PC[10] pin
| #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
PC[10] pin
| #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
PC[10] pin
| #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
PC[10] pin
| #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
PC[10] pin
| #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
PC[10] pin
| #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
PC[10] pin
| #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
PC[10] pin
| #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
PC[10] pin
| #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
PC[10] pin
| #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
PC[10] pin
| #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
PC[10] pin
| #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
PC[10] pin
| #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) |
PC[10] pin
| #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
PD[10] pin
| #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
PD[10] pin
| #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
PD[10] pin
| #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
PD[10] pin
| #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
PD[10] pin
| #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
PD[10] pin
| #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
PD[10] pin
| #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
PD[10] pin
| #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
PD[10] pin
| #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
PD[10] pin
| #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
PD[10] pin
| #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
PD[10] pin
| #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
PD[10] pin
| #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) |
PD[10] pin
| #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
PE[10] pin
| #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
PE[10] pin
| #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
PE[10] pin
| #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
PE[10] pin
| #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
PE[10] pin
| #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
PE[10] pin
| #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
PE[10] pin
| #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
PE[10] pin
| #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
PE[10] pin
| #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
PE[10] pin
| #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
PE[10] pin
| #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
PE[10] pin
| #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
PE[10] pin
| #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) |
PE[10] pin
| #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
PF[10] pin
| #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
PF[10] pin
| #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
PF[10] pin
| #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
PF[10] pin
| #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
PF[10] pin
| #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
PF[10] pin
| #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
PF[10] pin
| #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
PF[10] pin
| #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
PF[10] pin
| #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
PF[10] pin
| #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
PF[10] pin
| #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
PF[10] pin
| #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
PF[10] pin
| #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) |
PF[10] pin
| #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
PG[10] pin EXTI11 configuration
| #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
PG[10] pin EXTI11 configuration
| #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
PG[10] pin EXTI11 configuration
| #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
PG[10] pin EXTI11 configuration
| #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
PG[10] pin EXTI11 configuration
| #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
PG[10] pin EXTI11 configuration
| #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
PG[10] pin EXTI11 configuration
| #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
PG[10] pin EXTI11 configuration
| #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
PG[10] pin EXTI11 configuration
| #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
PG[10] pin EXTI11 configuration
| #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
PG[10] pin EXTI11 configuration
| #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
PG[10] pin EXTI11 configuration
| #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
PG[10] pin EXTI11 configuration
| #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) |
PG[10] pin EXTI11 configuration
| #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
EXTI 11 configuration EXTI8 configuration
| #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
EXTI 11 configuration EXTI8 configuration
| #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
EXTI 11 configuration EXTI8 configuration
| #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
EXTI 11 configuration EXTI8 configuration
| #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
EXTI 11 configuration EXTI8 configuration
| #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
EXTI 11 configuration EXTI8 configuration
| #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
EXTI 11 configuration EXTI8 configuration
| #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
EXTI 11 configuration EXTI8 configuration
| #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
EXTI 11 configuration EXTI8 configuration
| #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
EXTI 11 configuration EXTI8 configuration
| #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
EXTI 11 configuration EXTI8 configuration
| #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
EXTI 11 configuration EXTI8 configuration
| #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
EXTI 11 configuration EXTI8 configuration
| #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) |
EXTI 11 configuration EXTI8 configuration
| #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
PA[11] pin
| #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
PA[11] pin
| #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
PA[11] pin
| #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
PA[11] pin
| #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
PA[11] pin
| #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
PA[11] pin
| #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
PA[11] pin
| #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
PA[11] pin
| #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
PA[11] pin
| #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
PA[11] pin
| #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
PA[11] pin
| #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
PA[11] pin
| #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
PA[11] pin
| #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) |
PA[11] pin
| #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
PB[11] pin
| #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
PB[11] pin
| #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
PB[11] pin
| #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
PB[11] pin
| #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
PB[11] pin
| #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
PB[11] pin
| #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
PB[11] pin
| #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
PB[11] pin
| #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
PB[11] pin
| #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
PB[11] pin
| #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
PB[11] pin
| #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
PB[11] pin
| #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
PB[11] pin
| #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) |
PB[11] pin
| #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
PC[11] pin
| #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
PC[11] pin
| #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
PC[11] pin
| #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
PC[11] pin
| #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
PC[11] pin
| #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
PC[11] pin
| #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
PC[11] pin
| #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
PC[11] pin
| #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
PC[11] pin
| #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
PC[11] pin
| #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
PC[11] pin
| #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
PC[11] pin
| #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
PC[11] pin
| #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) |
PC[11] pin
| #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
PD[11] pin
| #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
PD[11] pin
| #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
PD[11] pin
| #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
PD[11] pin
| #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
PD[11] pin
| #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
PD[11] pin
| #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
PD[11] pin
| #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
PD[11] pin
| #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
PD[11] pin
| #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
PD[11] pin
| #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
PD[11] pin
| #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
PD[11] pin
| #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
PD[11] pin
| #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) |
PD[11] pin
| #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
PE[11] pin
| #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
PE[11] pin
| #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
PE[11] pin
| #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
PE[11] pin
| #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
PE[11] pin
| #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
PE[11] pin
| #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
PE[11] pin
| #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
PE[11] pin
| #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
PE[11] pin
| #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
PE[11] pin
| #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
PE[11] pin
| #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
PE[11] pin
| #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
PE[11] pin
| #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) |
PE[11] pin
| #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
PF[11] pin
| #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
PF[11] pin
| #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
PF[11] pin
| #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
PF[11] pin
| #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
PF[11] pin
| #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
PF[11] pin
| #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
PF[11] pin
| #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
PF[11] pin
| #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
PF[11] pin
| #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
PF[11] pin
| #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
PF[11] pin
| #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
PF[11] pin
| #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
PF[11] pin
| #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) |
PF[11] pin
| #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
PG[11] pin
| #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
PG[11] pin
| #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
PG[11] pin
| #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
PG[11] pin
| #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
PG[11] pin
| #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
PG[11] pin
| #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
PG[11] pin
| #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
PG[11] pin
| #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
PG[11] pin
| #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
PG[11] pin
| #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
PG[11] pin
| #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
PG[11] pin
| #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
PG[11] pin
| #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) |
PG[11] pin
| #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
EXTI 8 configuration
| #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
EXTI 8 configuration
| #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
EXTI 8 configuration
| #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
EXTI 8 configuration
| #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
EXTI 8 configuration
| #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
EXTI 8 configuration
| #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
EXTI 8 configuration
| #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
EXTI 8 configuration
| #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
EXTI 8 configuration
| #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
EXTI 8 configuration
| #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
EXTI 8 configuration
| #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
EXTI 8 configuration
| #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
EXTI 8 configuration
| #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) |
EXTI 8 configuration
| #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
PA[8] pin
| #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
PA[8] pin
| #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
PA[8] pin
| #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
PA[8] pin
| #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
PA[8] pin
| #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
PA[8] pin
| #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
PA[8] pin
| #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
PA[8] pin
| #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
PA[8] pin
| #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
PA[8] pin
| #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
PA[8] pin
| #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
PA[8] pin
| #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
PA[8] pin
| #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) |
PA[8] pin
| #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
PB[8] pin
| #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
PB[8] pin
| #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
PB[8] pin
| #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
PB[8] pin
| #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
PB[8] pin
| #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
PB[8] pin
| #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
PB[8] pin
| #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
PB[8] pin
| #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
PB[8] pin
| #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
PB[8] pin
| #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
PB[8] pin
| #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
PB[8] pin
| #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
PB[8] pin
| #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) |
PB[8] pin
| #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
PC[8] pin
| #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
PC[8] pin
| #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
PC[8] pin
| #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
PC[8] pin
| #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
PC[8] pin
| #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
PC[8] pin
| #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
PC[8] pin
| #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
PC[8] pin
| #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
PC[8] pin
| #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
PC[8] pin
| #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
PC[8] pin
| #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
PC[8] pin
| #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
PC[8] pin
| #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) |
PC[8] pin
| #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
PD[8] pin
| #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
PD[8] pin
| #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
PD[8] pin
| #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
PD[8] pin
| #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
PD[8] pin
| #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
PD[8] pin
| #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
PD[8] pin
| #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
PD[8] pin
| #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
PD[8] pin
| #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
PD[8] pin
| #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
PD[8] pin
| #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
PD[8] pin
| #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
PD[8] pin
| #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) |
PD[8] pin
| #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
PE[8] pin
| #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
PE[8] pin
| #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
PE[8] pin
| #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
PE[8] pin
| #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
PE[8] pin
| #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
PE[8] pin
| #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
PE[8] pin
| #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
PE[8] pin
| #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
PE[8] pin
| #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
PE[8] pin
| #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
PE[8] pin
| #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
PE[8] pin
| #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
PE[8] pin
| #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) |
PE[8] pin
| #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
PF[8] pin
| #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
PF[8] pin
| #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
PF[8] pin
| #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
PF[8] pin
| #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
PF[8] pin
| #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
PF[8] pin
| #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
PF[8] pin
| #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
PF[8] pin
| #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
PF[8] pin
| #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
PF[8] pin
| #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
PF[8] pin
| #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
PF[8] pin
| #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
PF[8] pin
| #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) |
PF[8] pin
| #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
PG[8] pin EXTI9 configuration
| #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
PG[8] pin EXTI9 configuration
| #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
PG[8] pin EXTI9 configuration
| #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
PG[8] pin EXTI9 configuration
| #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
PG[8] pin EXTI9 configuration
| #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
PG[8] pin EXTI9 configuration
| #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
PG[8] pin EXTI9 configuration
| #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
PG[8] pin EXTI9 configuration
| #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
PG[8] pin EXTI9 configuration
| #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
PG[8] pin EXTI9 configuration
| #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
PG[8] pin EXTI9 configuration
| #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
PG[8] pin EXTI9 configuration
| #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
PG[8] pin EXTI9 configuration
| #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) |
PG[8] pin EXTI9 configuration
| #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
EXTI 9 configuration
| #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
EXTI 9 configuration
| #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
EXTI 9 configuration
| #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
EXTI 9 configuration
| #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
EXTI 9 configuration
| #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
EXTI 9 configuration
| #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
EXTI 9 configuration
| #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
EXTI 9 configuration
| #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
EXTI 9 configuration
| #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
EXTI 9 configuration
| #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
EXTI 9 configuration
| #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
EXTI 9 configuration
| #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
EXTI 9 configuration
| #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) |
EXTI 9 configuration
| #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
PA[9] pin
| #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
PA[9] pin
| #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
PA[9] pin
| #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
PA[9] pin
| #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
PA[9] pin
| #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
PA[9] pin
| #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
PA[9] pin
| #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
PA[9] pin
| #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
PA[9] pin
| #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
PA[9] pin
| #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
PA[9] pin
| #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
PA[9] pin
| #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
PA[9] pin
| #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) |
PA[9] pin
| #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
PB[9] pin
| #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
PB[9] pin
| #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
PB[9] pin
| #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
PB[9] pin
| #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
PB[9] pin
| #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
PB[9] pin
| #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
PB[9] pin
| #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
PB[9] pin
| #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
PB[9] pin
| #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
PB[9] pin
| #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
PB[9] pin
| #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
PB[9] pin
| #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
PB[9] pin
| #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) |
PB[9] pin
| #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
PC[9] pin
| #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
PC[9] pin
| #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
PC[9] pin
| #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
PC[9] pin
| #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
PC[9] pin
| #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
PC[9] pin
| #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
PC[9] pin
| #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
PC[9] pin
| #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
PC[9] pin
| #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
PC[9] pin
| #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
PC[9] pin
| #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
PC[9] pin
| #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
PC[9] pin
| #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) |
PC[9] pin
| #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
PD[9] pin
| #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
PD[9] pin
| #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
PD[9] pin
| #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
PD[9] pin
| #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
PD[9] pin
| #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
PD[9] pin
| #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
PD[9] pin
| #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
PD[9] pin
| #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
PD[9] pin
| #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
PD[9] pin
| #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
PD[9] pin
| #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
PD[9] pin
| #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
PD[9] pin
| #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) |
PD[9] pin
| #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
PE[9] pin
| #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
PE[9] pin
| #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
PE[9] pin
| #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
PE[9] pin
| #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
PE[9] pin
| #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
PE[9] pin
| #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
PE[9] pin
| #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
PE[9] pin
| #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
PE[9] pin
| #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
PE[9] pin
| #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
PE[9] pin
| #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
PE[9] pin
| #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
PE[9] pin
| #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) |
PE[9] pin
| #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
PF[9] pin
| #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
PF[9] pin
| #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
PF[9] pin
| #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
PF[9] pin
| #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
PF[9] pin
| #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
PF[9] pin
| #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
PF[9] pin
| #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
PF[9] pin
| #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
PF[9] pin
| #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
PF[9] pin
| #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
PF[9] pin
| #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
PF[9] pin
| #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
PF[9] pin
| #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) |
PF[9] pin
| #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
PG[9] pin EXTI10 configuration
| #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
PG[9] pin EXTI10 configuration
| #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
PG[9] pin EXTI10 configuration
| #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
PG[9] pin EXTI10 configuration
| #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
PG[9] pin EXTI10 configuration
| #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
PG[9] pin EXTI10 configuration
| #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
PG[9] pin EXTI10 configuration
| #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
PG[9] pin EXTI10 configuration
| #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
PG[9] pin EXTI10 configuration
| #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
PG[9] pin EXTI10 configuration
| #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
PG[9] pin EXTI10 configuration
| #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
PG[9] pin EXTI10 configuration
| #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
PG[9] pin EXTI10 configuration
| #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) |
PG[9] pin EXTI10 configuration
| #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
EXTI 12 configuration
| #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
EXTI 12 configuration
| #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
EXTI 12 configuration
| #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
EXTI 12 configuration
| #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
EXTI 12 configuration
| #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
EXTI 12 configuration
| #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
EXTI 12 configuration
| #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
EXTI 12 configuration
| #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
EXTI 12 configuration
| #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
EXTI 12 configuration
| #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
EXTI 12 configuration
| #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
EXTI 12 configuration
| #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
EXTI 12 configuration
| #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) |
EXTI 12 configuration
| #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
PA[12] pin
| #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
PA[12] pin
| #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
PA[12] pin
| #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
PA[12] pin
| #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
PA[12] pin
| #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
PA[12] pin
| #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
PA[12] pin
| #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
PA[12] pin
| #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
PA[12] pin
| #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
PA[12] pin
| #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
PA[12] pin
| #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
PA[12] pin
| #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
PA[12] pin
| #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) |
PA[12] pin
| #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
PB[12] pin
| #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
PB[12] pin
| #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
PB[12] pin
| #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
PB[12] pin
| #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
PB[12] pin
| #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
PB[12] pin
| #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
PB[12] pin
| #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
PB[12] pin
| #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
PB[12] pin
| #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
PB[12] pin
| #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
PB[12] pin
| #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
PB[12] pin
| #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
PB[12] pin
| #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) |
PB[12] pin
| #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
PC[12] pin
| #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
PC[12] pin
| #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
PC[12] pin
| #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
PC[12] pin
| #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
PC[12] pin
| #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
PC[12] pin
| #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
PC[12] pin
| #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
PC[12] pin
| #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
PC[12] pin
| #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
PC[12] pin
| #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
PC[12] pin
| #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
PC[12] pin
| #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
PC[12] pin
| #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) |
PC[12] pin
| #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
PD[12] pin
| #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
PD[12] pin
| #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
PD[12] pin
| #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
PD[12] pin
| #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
PD[12] pin
| #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
PD[12] pin
| #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
PD[12] pin
| #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
PD[12] pin
| #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
PD[12] pin
| #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
PD[12] pin
| #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
PD[12] pin
| #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
PD[12] pin
| #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
PD[12] pin
| #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) |
PD[12] pin
| #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
PE[12] pin
| #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
PE[12] pin
| #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
PE[12] pin
| #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
PE[12] pin
| #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
PE[12] pin
| #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
PE[12] pin
| #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
PE[12] pin
| #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
PE[12] pin
| #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
PE[12] pin
| #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
PE[12] pin
| #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
PE[12] pin
| #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
PE[12] pin
| #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
PE[12] pin
| #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) |
PE[12] pin
| #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
PF[12] pin
| #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
PF[12] pin
| #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
PF[12] pin
| #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
PF[12] pin
| #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
PF[12] pin
| #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
PF[12] pin
| #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
PF[12] pin
| #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
PF[12] pin
| #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
PF[12] pin
| #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
PF[12] pin
| #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
PF[12] pin
| #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
PF[12] pin
| #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
PF[12] pin
| #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) |
PF[12] pin
| #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
PG[12] pin
| #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
PG[12] pin
| #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
PG[12] pin
| #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
PG[12] pin
| #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
PG[12] pin
| #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
PG[12] pin
| #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
PG[12] pin
| #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
PG[12] pin
| #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
PG[12] pin
| #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
PG[12] pin
| #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
PG[12] pin
| #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
PG[12] pin
| #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
PG[12] pin
| #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) |
PG[12] pin
| #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
EXTI 13 configuration
| #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
EXTI 13 configuration
| #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
EXTI 13 configuration
| #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
EXTI 13 configuration
| #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
EXTI 13 configuration
| #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
EXTI 13 configuration
| #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
EXTI 13 configuration
| #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
EXTI 13 configuration
| #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
EXTI 13 configuration
| #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
EXTI 13 configuration
| #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
EXTI 13 configuration
| #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
EXTI 13 configuration
| #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
EXTI 13 configuration
| #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) |
EXTI 13 configuration
| #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
PA[13] pin
| #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
PA[13] pin
| #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
PA[13] pin
| #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
PA[13] pin
| #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
PA[13] pin
| #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
PA[13] pin
| #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
PA[13] pin
| #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
PA[13] pin
| #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
PA[13] pin
| #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
PA[13] pin
| #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
PA[13] pin
| #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
PA[13] pin
| #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
PA[13] pin
| #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) |
PA[13] pin
| #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
PB[13] pin
| #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
PB[13] pin
| #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
PB[13] pin
| #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
PB[13] pin
| #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
PB[13] pin
| #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
PB[13] pin
| #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
PB[13] pin
| #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
PB[13] pin
| #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
PB[13] pin
| #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
PB[13] pin
| #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
PB[13] pin
| #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
PB[13] pin
| #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
PB[13] pin
| #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) |
PB[13] pin
| #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
PC[13] pin
| #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
PC[13] pin
| #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
PC[13] pin
| #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
PC[13] pin
| #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
PC[13] pin
| #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
PC[13] pin
| #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
PC[13] pin
| #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
PC[13] pin
| #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
PC[13] pin
| #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
PC[13] pin
| #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
PC[13] pin
| #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
PC[13] pin
| #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
PC[13] pin
| #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) |
PC[13] pin
| #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
PD[13] pin
| #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
PD[13] pin
| #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
PD[13] pin
| #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
PD[13] pin
| #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
PD[13] pin
| #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
PD[13] pin
| #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
PD[13] pin
| #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
PD[13] pin
| #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
PD[13] pin
| #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
PD[13] pin
| #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
PD[13] pin
| #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
PD[13] pin
| #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
PD[13] pin
| #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) |
PD[13] pin
| #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
PE[13] pin
| #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
PE[13] pin
| #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
PE[13] pin
| #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
PE[13] pin
| #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
PE[13] pin
| #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
PE[13] pin
| #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
PE[13] pin
| #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
PE[13] pin
| #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
PE[13] pin
| #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
PE[13] pin
| #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
PE[13] pin
| #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
PE[13] pin
| #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
PE[13] pin
| #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) |
PE[13] pin
| #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
PF[13] pin
| #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
PF[13] pin
| #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
PF[13] pin
| #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
PF[13] pin
| #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
PF[13] pin
| #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
PF[13] pin
| #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
PF[13] pin
| #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
PF[13] pin
| #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
PF[13] pin
| #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
PF[13] pin
| #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
PF[13] pin
| #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
PF[13] pin
| #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
PF[13] pin
| #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) |
PF[13] pin
| #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
PG[13] pin EXTI14 configuration
| #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
PG[13] pin EXTI14 configuration
| #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
PG[13] pin EXTI14 configuration
| #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
PG[13] pin EXTI14 configuration
| #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
PG[13] pin EXTI14 configuration
| #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
PG[13] pin EXTI14 configuration
| #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
PG[13] pin EXTI14 configuration
| #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
PG[13] pin EXTI14 configuration
| #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
PG[13] pin EXTI14 configuration
| #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
PG[13] pin EXTI14 configuration
| #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
PG[13] pin EXTI14 configuration
| #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
PG[13] pin EXTI14 configuration
| #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
PG[13] pin EXTI14 configuration
| #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) |
PG[13] pin EXTI14 configuration
| #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
EXTI 14 configuration
| #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
EXTI 14 configuration
| #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
EXTI 14 configuration
| #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
EXTI 14 configuration
| #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
EXTI 14 configuration
| #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
EXTI 14 configuration
| #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
EXTI 14 configuration
| #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
EXTI 14 configuration
| #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
EXTI 14 configuration
| #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
EXTI 14 configuration
| #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
EXTI 14 configuration
| #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
EXTI 14 configuration
| #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
EXTI 14 configuration
| #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) |
EXTI 14 configuration
| #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
PA[14] pin
| #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
PA[14] pin
| #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
PA[14] pin
| #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
PA[14] pin
| #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
PA[14] pin
| #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
PA[14] pin
| #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
PA[14] pin
| #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
PA[14] pin
| #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
PA[14] pin
| #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
PA[14] pin
| #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
PA[14] pin
| #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
PA[14] pin
| #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
PA[14] pin
| #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) |
PA[14] pin
| #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
PB[14] pin
| #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
PB[14] pin
| #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
PB[14] pin
| #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
PB[14] pin
| #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
PB[14] pin
| #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
PB[14] pin
| #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
PB[14] pin
| #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
PB[14] pin
| #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
PB[14] pin
| #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
PB[14] pin
| #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
PB[14] pin
| #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
PB[14] pin
| #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
PB[14] pin
| #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) |
PB[14] pin
| #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
PC[14] pin
| #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
PC[14] pin
| #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
PC[14] pin
| #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
PC[14] pin
| #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
PC[14] pin
| #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
PC[14] pin
| #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
PC[14] pin
| #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
PC[14] pin
| #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
PC[14] pin
| #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
PC[14] pin
| #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
PC[14] pin
| #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
PC[14] pin
| #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
PC[14] pin
| #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) |
PC[14] pin
| #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
PD[14] pin
| #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
PD[14] pin
| #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
PD[14] pin
| #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
PD[14] pin
| #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
PD[14] pin
| #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
PD[14] pin
| #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
PD[14] pin
| #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
PD[14] pin
| #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
PD[14] pin
| #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
PD[14] pin
| #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
PD[14] pin
| #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
PD[14] pin
| #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
PD[14] pin
| #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) |
PD[14] pin
| #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
PE[14] pin
| #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
PE[14] pin
| #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
PE[14] pin
| #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
PE[14] pin
| #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
PE[14] pin
| #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
PE[14] pin
| #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
PE[14] pin
| #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
PE[14] pin
| #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
PE[14] pin
| #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
PE[14] pin
| #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
PE[14] pin
| #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
PE[14] pin
| #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
PE[14] pin
| #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) |
PE[14] pin
| #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
PF[14] pin
| #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
PF[14] pin
| #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
PF[14] pin
| #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
PF[14] pin
| #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
PF[14] pin
| #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
PF[14] pin
| #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
PF[14] pin
| #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
PF[14] pin
| #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
PF[14] pin
| #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
PF[14] pin
| #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
PF[14] pin
| #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
PF[14] pin
| #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
PF[14] pin
| #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) |
PF[14] pin
| #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
PG[14] pin EXTI15 configuration
| #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
PG[14] pin EXTI15 configuration
| #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
PG[14] pin EXTI15 configuration
| #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
PG[14] pin EXTI15 configuration
| #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
PG[14] pin EXTI15 configuration
| #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
PG[14] pin EXTI15 configuration
| #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
PG[14] pin EXTI15 configuration
| #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
PG[14] pin EXTI15 configuration
| #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
PG[14] pin EXTI15 configuration
| #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
PG[14] pin EXTI15 configuration
| #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
PG[14] pin EXTI15 configuration
| #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
PG[14] pin EXTI15 configuration
| #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
PG[14] pin EXTI15 configuration
| #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) |
PG[14] pin EXTI15 configuration
| #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
EXTI 15 configuration
| #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
EXTI 15 configuration
| #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
EXTI 15 configuration
| #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
EXTI 15 configuration
| #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
EXTI 15 configuration
| #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
EXTI 15 configuration
| #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
EXTI 15 configuration
| #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
EXTI 15 configuration
| #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
EXTI 15 configuration
| #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
EXTI 15 configuration
| #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
EXTI 15 configuration
| #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
EXTI 15 configuration
| #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
EXTI 15 configuration
| #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) |
EXTI 15 configuration
| #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
PA[15] pin
| #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
PA[15] pin
| #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
PA[15] pin
| #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
PA[15] pin
| #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
PA[15] pin
| #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
PA[15] pin
| #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
PA[15] pin
| #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
PA[15] pin
| #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
PA[15] pin
| #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
PA[15] pin
| #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
PA[15] pin
| #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
PA[15] pin
| #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
PA[15] pin
| #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) |
PA[15] pin
| #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
PB[15] pin
| #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
PB[15] pin
| #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
PB[15] pin
| #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
PB[15] pin
| #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
PB[15] pin
| #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
PB[15] pin
| #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
PB[15] pin
| #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
PB[15] pin
| #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
PB[15] pin
| #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
PB[15] pin
| #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
PB[15] pin
| #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
PB[15] pin
| #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
PB[15] pin
| #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) |
PB[15] pin
| #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
PC[15] pin
| #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
PC[15] pin
| #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
PC[15] pin
| #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
PC[15] pin
| #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
PC[15] pin
| #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
PC[15] pin
| #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
PC[15] pin
| #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
PC[15] pin
| #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
PC[15] pin
| #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
PC[15] pin
| #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
PC[15] pin
| #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
PC[15] pin
| #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
PC[15] pin
| #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) |
PC[15] pin
| #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
PD[15] pin
| #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
PD[15] pin
| #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
PD[15] pin
| #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
PD[15] pin
| #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
PD[15] pin
| #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
PD[15] pin
| #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
PD[15] pin
| #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
PD[15] pin
| #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
PD[15] pin
| #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
PD[15] pin
| #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
PD[15] pin
| #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
PD[15] pin
| #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
PD[15] pin
| #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) |
PD[15] pin
| #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
PE[15] pin
| #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
PE[15] pin
| #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
PE[15] pin
| #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
PE[15] pin
| #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
PE[15] pin
| #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
PE[15] pin
| #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
PE[15] pin
| #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
PE[15] pin
| #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
PE[15] pin
| #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
PE[15] pin
| #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
PE[15] pin
| #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
PE[15] pin
| #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
PE[15] pin
| #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) |
PE[15] pin
| #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
PF[15] pin
| #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
PF[15] pin
| #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
PF[15] pin
| #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
PF[15] pin
| #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
PF[15] pin
| #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
PF[15] pin
| #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
PF[15] pin
| #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
PF[15] pin
| #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
PF[15] pin
| #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
PF[15] pin
| #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
PF[15] pin
| #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
PF[15] pin
| #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
PF[15] pin
| #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) |
PF[15] pin
| #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
PG[15] pin
| #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
PG[15] pin
| #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
PG[15] pin
| #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
PG[15] pin
| #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
PG[15] pin
| #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
PG[15] pin
| #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
PG[15] pin
| #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
PG[15] pin
| #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
PG[15] pin
| #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
PG[15] pin
| #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
PG[15] pin
| #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
PG[15] pin
| #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
PG[15] pin
| #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) |
PG[15] pin
| #define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) |
CEC remapping
| #define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) |
CEC remapping
| #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) |
FSMC NADV remapping
| #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) |
FSMC NADV remapping
| #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) |
FSMC NADV remapping
| #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) |
FSMC NADV remapping
| #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) |
FSMC NADV remapping
| #define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) |
Miscellaneous remapping
| #define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) |
TIM10 remapping
| #define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) |
TIM10 remapping
| #define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) |
TIM11 remapping
| #define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) |
TIM11 remapping
| #define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) |
TIM12 remapping
| #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) |
TIM13 remapping
| #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) |
TIM13 remapping
| #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) |
TIM13 remapping
| #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) |
TIM14 remapping
| #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) |
TIM14 remapping
| #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) |
TIM14 remapping
| #define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) |
TIM15 remapping
| #define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) |
TIM15 remapping
| #define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) |
TIM16 remapping
| #define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) |
TIM16 remapping
| #define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) |
TIM17 remapping
| #define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) |
TIM17 remapping
| #define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) |
TIM1_DMA remapping
| #define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) |
TIM1_DMA remapping
| #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) |
TIM6/TIM7 and DAC DMA remapping
| #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) |
TIM6/TIM7 and DAC DMA remapping
| #define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) |
TIM9 remapping
| #define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) |
TIM9 remapping
| #define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) |
ADC 1 External Trigger Injected Conversion remapping
| #define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) |
ADC 1 External Trigger Injected Conversion remapping
| #define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) |
ADC 1 External Trigger Regular Conversion remapping
| #define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) |
ADC 1 External Trigger Regular Conversion remapping
| #define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) |
ADC 2 External Trigger Injected Conversion remapping
| #define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) |
ADC 2 External Trigger Injected Conversion remapping
| #define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) |
ADC 2 External Trigger Regular Conversion remapping SWJ_CFG configuration
| #define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) |
ADC 2 External Trigger Regular Conversion remapping SWJ_CFG configuration
| #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) |
CAN2_REMAP bit (CAN2 I/O remapping) MII_RMII_SEL configuration
| #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) |
CAN2_REMAP bit (CAN2 I/O remapping) MII_RMII_SEL configuration
| #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) |
CAN_REMAP[1:0] bits (CAN Alternate function remapping)
| #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) |
CAN_REMAP[1:0] bits (CAN Alternate function remapping)
| #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) |
CAN_REMAP[1:0] bits (CAN Alternate function remapping)
| #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) |
CAN_REMAP[1:0] bits (CAN Alternate function remapping)
| #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) |
CAN_REMAP[1:0] bits (CAN Alternate function remapping)
| #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) |
CAN_REMAP[1:0] bits (CAN Alternate function remapping)
| #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) |
Bit 0
| #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) |
Bit 0
| #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) |
Bit 0
| #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) |
Bit 0
| #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) |
Bit 0
| #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) |
Bit 0
| #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) |
Bit 1 CAN_REMAP configuration
| #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) |
Bit 1 CAN_REMAP configuration
| #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) |
Bit 1 CAN_REMAP configuration
| #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) |
Bit 1 CAN_REMAP configuration
| #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) |
Bit 1 CAN_REMAP configuration
| #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) |
Bit 1 CAN_REMAP configuration
| #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) |
CANRX mapped to PA11, CANTX mapped to PA12
| #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) |
CANRX mapped to PA11, CANTX mapped to PA12
| #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) |
CANRX mapped to PA11, CANTX mapped to PA12
| #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) |
CANRX mapped to PA11, CANTX mapped to PA12
| #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) |
CANRX mapped to PA11, CANTX mapped to PA12
| #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) |
CANRX mapped to PA11, CANTX mapped to PA12
| #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) |
CANRX mapped to PB8, CANTX mapped to PB9
| #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) |
CANRX mapped to PB8, CANTX mapped to PB9
| #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) |
CANRX mapped to PB8, CANTX mapped to PB9
| #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) |
CANRX mapped to PB8, CANTX mapped to PB9
| #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) |
CANRX mapped to PB8, CANTX mapped to PB9
| #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) |
CANRX mapped to PB8, CANTX mapped to PB9
| #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) |
CANRX mapped to PD0, CANTX mapped to PD1
| #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) |
CANRX mapped to PD0, CANTX mapped to PD1
| #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) |
CANRX mapped to PD0, CANTX mapped to PD1
| #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) |
CANRX mapped to PD0, CANTX mapped to PD1
| #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) |
CANRX mapped to PD0, CANTX mapped to PD1
| #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) |
CANRX mapped to PD0, CANTX mapped to PD1
| #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) |
SPI3_REMAP bit (Ethernet MAC I/O remapping) CAN2_REMAP configuration
| #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) |
SPI3_REMAP bit (Ethernet MAC I/O remapping) CAN2_REMAP configuration
| #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
I2C1 remapping
| #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
I2C1 remapping
| #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
I2C1 remapping
| #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
I2C1 remapping
| #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
I2C1 remapping
| #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
I2C1 remapping
| #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
I2C1 remapping
| #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
I2C1 remapping
| #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
I2C1 remapping
| #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
I2C1 remapping
| #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
I2C1 remapping
| #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
I2C1 remapping
| #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
I2C1 remapping
| #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
I2C1 remapping
| #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) |
MII_RMII_SEL bit (Ethernet MII or RMII selection) SPI3_REMAP configuration
| #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) |
MII_RMII_SEL bit (Ethernet MII or RMII selection) SPI3_REMAP configuration
| #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
Port D0/Port D1 mapping on OSC_IN/OSC_OUT SWJ_CFG configuration
| #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
Port D0/Port D1 mapping on OSC_IN/OSC_OUT SWJ_CFG configuration
| #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
Port D0/Port D1 mapping on OSC_IN/OSC_OUT SWJ_CFG configuration
| #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
Port D0/Port D1 mapping on OSC_IN/OSC_OUT SWJ_CFG configuration
| #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
Port D0/Port D1 mapping on OSC_IN/OSC_OUT SWJ_CFG configuration
| #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
Port D0/Port D1 mapping on OSC_IN/OSC_OUT SWJ_CFG configuration
| #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
Port D0/Port D1 mapping on OSC_IN/OSC_OUT SWJ_CFG configuration
| #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
Port D0/Port D1 mapping on OSC_IN/OSC_OUT
| #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
Port D0/Port D1 mapping on OSC_IN/OSC_OUT
| #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
Port D0/Port D1 mapping on OSC_IN/OSC_OUT
| #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
Port D0/Port D1 mapping on OSC_IN/OSC_OUT
| #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
Port D0/Port D1 mapping on OSC_IN/OSC_OUT
| #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
Port D0/Port D1 mapping on OSC_IN/OSC_OUT
| #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
Port D0/Port D1 mapping on OSC_IN/OSC_OUT
| #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) |
PTP_PPS_REMAP bit (Ethernet PTP PPS remapping)
| #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) |
PTP_PPS_REMAP bit (Ethernet PTP PPS remapping)
| #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
SPI1 remapping
| #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
SPI1 remapping
| #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
SPI1 remapping
| #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
SPI1 remapping
| #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
SPI1 remapping
| #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
SPI1 remapping
| #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
SPI1 remapping
| #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
SPI1 remapping
| #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
SPI1 remapping
| #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
SPI1 remapping
| #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
SPI1 remapping
| #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
SPI1 remapping
| #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
SPI1 remapping
| #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
SPI1 remapping
| #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) |
SPI3_REMAP bit (SPI3 remapping) TIM2ITR1_IREMAP configuration
| #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) |
SPI3_REMAP bit (SPI3 remapping) TIM2ITR1_IREMAP configuration
| #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
| #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
| #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
| #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
| #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
| #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
| #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
| #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
| #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
| #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
| #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
| #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
| #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
| #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)
| #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
Bit 0
| #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
Bit 0
| #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
Bit 0
| #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
Bit 0
| #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
Bit 0
| #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
Bit 0
| #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
Bit 0
| #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
Bit 0
| #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
Bit 0
| #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
Bit 0
| #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
Bit 0
| #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
Bit 0
| #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
Bit 0
| #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
Bit 0
| #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
Bit 1
| #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
Bit 1
| #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
Bit 1
| #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
Bit 1
| #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
Bit 1
| #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
Bit 1
| #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
Bit 1
| #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
Bit 1
| #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
Bit 1
| #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
Bit 1
| #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
Bit 1
| #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
Bit 1
| #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
Bit 1
| #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
Bit 1
| #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
Bit 2
| #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
Bit 2
| #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
Bit 2
| #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
Bit 2
| #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
Bit 2
| #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
Bit 2
| #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
Bit 2
| #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
Bit 2
| #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
Bit 2
| #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
Bit 2
| #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
Bit 2
| #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
Bit 2
| #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
Bit 2
| #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
Bit 2
| #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
JTAG-DP Disabled and SW-DP Disabled
| #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
JTAG-DP Disabled and SW-DP Disabled
| #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
JTAG-DP Disabled and SW-DP Disabled
| #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
JTAG-DP Disabled and SW-DP Disabled
| #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
JTAG-DP Disabled and SW-DP Disabled
| #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
JTAG-DP Disabled and SW-DP Disabled
| #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
JTAG-DP Disabled and SW-DP Disabled
| #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
JTAG-DP Disabled and SW-DP Disabled
| #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
JTAG-DP Disabled and SW-DP Disabled
| #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
JTAG-DP Disabled and SW-DP Disabled
| #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
JTAG-DP Disabled and SW-DP Disabled
| #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
JTAG-DP Disabled and SW-DP Disabled
| #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
JTAG-DP Disabled and SW-DP Disabled ETH_REMAP configuration
| #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
JTAG-DP Disabled and SW-DP Disabled ETH_REMAP configuration
| #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
JTAG-DP Disabled and SW-DP Enabled
| #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
JTAG-DP Disabled and SW-DP Enabled
| #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
JTAG-DP Disabled and SW-DP Enabled
| #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
JTAG-DP Disabled and SW-DP Enabled
| #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
JTAG-DP Disabled and SW-DP Enabled
| #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
JTAG-DP Disabled and SW-DP Enabled
| #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
JTAG-DP Disabled and SW-DP Enabled
| #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
JTAG-DP Disabled and SW-DP Enabled
| #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
JTAG-DP Disabled and SW-DP Enabled
| #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
JTAG-DP Disabled and SW-DP Enabled
| #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
JTAG-DP Disabled and SW-DP Enabled
| #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
JTAG-DP Disabled and SW-DP Enabled
| #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
JTAG-DP Disabled and SW-DP Enabled
| #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
JTAG-DP Disabled and SW-DP Enabled
| #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
Full SWJ (JTAG-DP + SW-DP) but without JNTRST
| #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
Full SWJ (JTAG-DP + SW-DP) but without JNTRST
| #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
Full SWJ (JTAG-DP + SW-DP) but without JNTRST
| #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
Full SWJ (JTAG-DP + SW-DP) but without JNTRST
| #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
Full SWJ (JTAG-DP + SW-DP) but without JNTRST
| #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
Full SWJ (JTAG-DP + SW-DP) but without JNTRST
| #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
Full SWJ (JTAG-DP + SW-DP) but without JNTRST
| #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
Full SWJ (JTAG-DP + SW-DP) but without JNTRST
| #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
Full SWJ (JTAG-DP + SW-DP) but without JNTRST
| #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
Full SWJ (JTAG-DP + SW-DP) but without JNTRST
| #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
Full SWJ (JTAG-DP + SW-DP) but without JNTRST
| #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
Full SWJ (JTAG-DP + SW-DP) but without JNTRST
| #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
Full SWJ (JTAG-DP + SW-DP) but without JNTRST
| #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
Full SWJ (JTAG-DP + SW-DP) but without JNTRST
| #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
Full SWJ (JTAG-DP + SW-DP) : Reset State
| #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
Full SWJ (JTAG-DP + SW-DP) : Reset State
| #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
Full SWJ (JTAG-DP + SW-DP) : Reset State
| #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
Full SWJ (JTAG-DP + SW-DP) : Reset State
| #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
Full SWJ (JTAG-DP + SW-DP) : Reset State
| #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
Full SWJ (JTAG-DP + SW-DP) : Reset State
| #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
Full SWJ (JTAG-DP + SW-DP) : Reset State
| #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
Full SWJ (JTAG-DP + SW-DP) : Reset State
| #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
Full SWJ (JTAG-DP + SW-DP) : Reset State
| #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
Full SWJ (JTAG-DP + SW-DP) : Reset State
| #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
Full SWJ (JTAG-DP + SW-DP) : Reset State
| #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
Full SWJ (JTAG-DP + SW-DP) : Reset State
| #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
Full SWJ (JTAG-DP + SW-DP) : Reset State
| #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
Full SWJ (JTAG-DP + SW-DP) : Reset State
| #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
TIM1_REMAP[1:0] bits (TIM1 remapping)
| #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
TIM1_REMAP[1:0] bits (TIM1 remapping)
| #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
TIM1_REMAP[1:0] bits (TIM1 remapping)
| #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
TIM1_REMAP[1:0] bits (TIM1 remapping)
| #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
TIM1_REMAP[1:0] bits (TIM1 remapping)
| #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
TIM1_REMAP[1:0] bits (TIM1 remapping)
| #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
TIM1_REMAP[1:0] bits (TIM1 remapping)
| #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
TIM1_REMAP[1:0] bits (TIM1 remapping)
| #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
TIM1_REMAP[1:0] bits (TIM1 remapping)
| #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
TIM1_REMAP[1:0] bits (TIM1 remapping)
| #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
TIM1_REMAP[1:0] bits (TIM1 remapping)
| #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
TIM1_REMAP[1:0] bits (TIM1 remapping)
| #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
TIM1_REMAP[1:0] bits (TIM1 remapping)
| #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
TIM1_REMAP[1:0] bits (TIM1 remapping)
| #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
Bit 0
| #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
Bit 0
| #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
Bit 0
| #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
Bit 0
| #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
Bit 0
| #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
Bit 0
| #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
Bit 0
| #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
Bit 0
| #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
Bit 0
| #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
Bit 0
| #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
Bit 0
| #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
Bit 0
| #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
Bit 0
| #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
Bit 0
| #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
Bit 1 TIM1_REMAP configuration
| #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
Bit 1 TIM1_REMAP configuration
| #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
Bit 1 TIM1_REMAP configuration
| #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
Bit 1 TIM1_REMAP configuration
| #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
Bit 1 TIM1_REMAP configuration
| #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
Bit 1 TIM1_REMAP configuration
| #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
Bit 1 TIM1_REMAP configuration
| #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
Bit 1 TIM1_REMAP configuration
| #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
Bit 1 TIM1_REMAP configuration
| #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
Bit 1 TIM1_REMAP configuration
| #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
Bit 1 TIM1_REMAP configuration
| #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
Bit 1 TIM1_REMAP configuration
| #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
Bit 1 TIM1_REMAP configuration
| #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
Bit 1 TIM1_REMAP configuration
| #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
| #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
| #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
| #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
| #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
| #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
| #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
| #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
| #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
| #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
| #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
| #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
| #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
| #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
| #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
| #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
| #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
| #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
| #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
| #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
| #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
| #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
| #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
| #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
| #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
| #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
| #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
| #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
| #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
| #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
| #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
| #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
| #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
| #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
| #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
| #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
| #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
| #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
| #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
| #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
| #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
| #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
| #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
TIM2_REMAP[1:0] bits (TIM2 remapping)
| #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
TIM2_REMAP[1:0] bits (TIM2 remapping)
| #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
TIM2_REMAP[1:0] bits (TIM2 remapping)
| #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
TIM2_REMAP[1:0] bits (TIM2 remapping)
| #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
TIM2_REMAP[1:0] bits (TIM2 remapping)
| #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
TIM2_REMAP[1:0] bits (TIM2 remapping)
| #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
TIM2_REMAP[1:0] bits (TIM2 remapping)
| #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
TIM2_REMAP[1:0] bits (TIM2 remapping)
| #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
TIM2_REMAP[1:0] bits (TIM2 remapping)
| #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
TIM2_REMAP[1:0] bits (TIM2 remapping)
| #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
TIM2_REMAP[1:0] bits (TIM2 remapping)
| #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
TIM2_REMAP[1:0] bits (TIM2 remapping)
| #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
TIM2_REMAP[1:0] bits (TIM2 remapping)
| #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
TIM2_REMAP[1:0] bits (TIM2 remapping)
| #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
Bit 0
| #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
Bit 0
| #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
Bit 0
| #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
Bit 0
| #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
Bit 0
| #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
Bit 0
| #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
Bit 0
| #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
Bit 0
| #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
Bit 0
| #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
Bit 0
| #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
Bit 0
| #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
Bit 0
| #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
Bit 0
| #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
Bit 0
| #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
Bit 1 TIM2_REMAP configuration
| #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
Bit 1 TIM2_REMAP configuration
| #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
Bit 1 TIM2_REMAP configuration
| #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
Bit 1 TIM2_REMAP configuration
| #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
Bit 1 TIM2_REMAP configuration
| #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
Bit 1 TIM2_REMAP configuration
| #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
Bit 1 TIM2_REMAP configuration
| #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
Bit 1 TIM2_REMAP configuration
| #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
Bit 1 TIM2_REMAP configuration
| #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
Bit 1 TIM2_REMAP configuration
| #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
Bit 1 TIM2_REMAP configuration
| #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
Bit 1 TIM2_REMAP configuration
| #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
Bit 1 TIM2_REMAP configuration
| #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
Bit 1 TIM2_REMAP configuration
| #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
| #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) |
TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) PTP_PPS_REMAP configuration
| #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) |
TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) PTP_PPS_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
TIM3_REMAP[1:0] bits (TIM3 remapping)
| #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
TIM3_REMAP[1:0] bits (TIM3 remapping)
| #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
TIM3_REMAP[1:0] bits (TIM3 remapping)
| #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
TIM3_REMAP[1:0] bits (TIM3 remapping)
| #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
TIM3_REMAP[1:0] bits (TIM3 remapping)
| #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
TIM3_REMAP[1:0] bits (TIM3 remapping)
| #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
TIM3_REMAP[1:0] bits (TIM3 remapping)
| #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
TIM3_REMAP[1:0] bits (TIM3 remapping)
| #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
TIM3_REMAP[1:0] bits (TIM3 remapping)
| #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
TIM3_REMAP[1:0] bits (TIM3 remapping)
| #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
TIM3_REMAP[1:0] bits (TIM3 remapping)
| #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
TIM3_REMAP[1:0] bits (TIM3 remapping)
| #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
TIM3_REMAP[1:0] bits (TIM3 remapping)
| #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
TIM3_REMAP[1:0] bits (TIM3 remapping)
| #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
Bit 0
| #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
Bit 0
| #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
Bit 0
| #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
Bit 0
| #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
Bit 0
| #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
Bit 0
| #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
Bit 0
| #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
Bit 0
| #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
Bit 0
| #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
Bit 0
| #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
Bit 0
| #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
Bit 0
| #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
Bit 0
| #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
Bit 0
| #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
Bit 1 TIM3_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
Bit 1 TIM3_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
Bit 1 TIM3_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
Bit 1 TIM3_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
Bit 1 TIM3_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
Bit 1 TIM3_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
Bit 1 TIM3_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
Bit 1 TIM3_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
Bit 1 TIM3_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
Bit 1 TIM3_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
Bit 1 TIM3_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
Bit 1 TIM3_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
Bit 1 TIM3_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
Bit 1 TIM3_REMAP configuration
| #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
| #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
| #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
| #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
| #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
| #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
| #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
| #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
| #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
| #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
| #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
| #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
| #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
| #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
| #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
| #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
TIM4_REMAP bit (TIM4 remapping)
| #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
TIM4_REMAP bit (TIM4 remapping)
| #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
TIM4_REMAP bit (TIM4 remapping)
| #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
TIM4_REMAP bit (TIM4 remapping)
| #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
TIM4_REMAP bit (TIM4 remapping)
| #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
TIM4_REMAP bit (TIM4 remapping)
| #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
TIM4_REMAP bit (TIM4 remapping)
| #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
TIM4_REMAP bit (TIM4 remapping)
| #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
TIM4_REMAP bit (TIM4 remapping)
| #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
TIM4_REMAP bit (TIM4 remapping)
| #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
TIM4_REMAP bit (TIM4 remapping)
| #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
TIM5 Channel4 Internal Remap SWJ_CFG configuration
| #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
TIM5 Channel4 Internal Remap SWJ_CFG configuration
| #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
TIM5 Channel4 Internal Remap SWJ_CFG configuration
| #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
TIM5 Channel4 Internal Remap
| #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
TIM5 Channel4 Internal Remap
| #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
TIM5 Channel4 Internal Remap SWJ_CFG configuration
| #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
TIM5 Channel4 Internal Remap SWJ_CFG configuration
| #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
USART1 remapping
| #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
USART1 remapping
| #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
USART1 remapping
| #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
USART1 remapping
| #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
USART1 remapping
| #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
USART1 remapping
| #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
USART1 remapping
| #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
USART1 remapping
| #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
USART1 remapping
| #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
USART1 remapping
| #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
USART1 remapping
| #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
USART1 remapping
| #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
USART1 remapping
| #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
USART1 remapping
| #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
USART2 remapping
| #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
USART2 remapping
| #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
USART2 remapping
| #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
USART2 remapping
| #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
USART2 remapping
| #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
USART2 remapping
| #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
USART2 remapping
| #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
USART2 remapping
| #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
USART2 remapping
| #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
USART2 remapping
| #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
USART2 remapping
| #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
USART2 remapping
| #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
USART2 remapping
| #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
USART2 remapping
| #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
USART3_REMAP[1:0] bits (USART3 remapping)
| #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
USART3_REMAP[1:0] bits (USART3 remapping)
| #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
USART3_REMAP[1:0] bits (USART3 remapping)
| #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
USART3_REMAP[1:0] bits (USART3 remapping)
| #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
USART3_REMAP[1:0] bits (USART3 remapping)
| #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
USART3_REMAP[1:0] bits (USART3 remapping)
| #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
USART3_REMAP[1:0] bits (USART3 remapping)
| #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
USART3_REMAP[1:0] bits (USART3 remapping)
| #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
USART3_REMAP[1:0] bits (USART3 remapping)
| #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
USART3_REMAP[1:0] bits (USART3 remapping)
| #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
USART3_REMAP[1:0] bits (USART3 remapping)
| #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
Bit 0
| #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
Bit 1
| #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
| #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
| #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
| #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
| #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
| #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
| #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
| #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
| #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
| #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
| #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
| #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
| #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
| #define BKP_CR_TPAL ((uint32_t)0x00000002) |
TAMPER pin active level
| #define BKP_CR_TPAL ((uint32_t)0x00000002) |
TAMPER pin active level
| #define BKP_CR_TPAL ((uint32_t)0x00000002) |
TAMPER pin active level
| #define BKP_CR_TPAL ((uint32_t)0x00000002) |
TAMPER pin active level
| #define BKP_CR_TPAL ((uint32_t)0x00000002) |
TAMPER pin active level
| #define BKP_CR_TPAL ((uint32_t)0x00000002) |
TAMPER pin active level
| #define BKP_CR_TPAL ((uint32_t)0x00000002) |
TAMPER pin active level
| #define BKP_CR_TPAL ((uint32_t)0x00000002) |
TAMPER pin active level
| #define BKP_CR_TPAL ((uint32_t)0x00000002) |
TAMPER pin active level
| #define BKP_CR_TPAL ((uint32_t)0x00000002) |
TAMPER pin active level
| #define BKP_CR_TPAL ((uint32_t)0x00000002) |
TAMPER pin active level
| #define BKP_CR_TPAL ((uint32_t)0x00000002) |
TAMPER pin active level
| #define BKP_CR_TPAL ((uint32_t)0x00000002) |
TAMPER pin active level
| #define BKP_CR_TPAL ((uint32_t)0x00000002) |
TAMPER pin active level
| #define BKP_CR_TPE ((uint32_t)0x00000001) |
TAMPER pin enable
| #define BKP_CR_TPE ((uint32_t)0x00000001) |
TAMPER pin enable
| #define BKP_CR_TPE ((uint32_t)0x00000001) |
TAMPER pin enable
| #define BKP_CR_TPE ((uint32_t)0x00000001) |
TAMPER pin enable
| #define BKP_CR_TPE ((uint32_t)0x00000001) |
TAMPER pin enable
| #define BKP_CR_TPE ((uint32_t)0x00000001) |
TAMPER pin enable
| #define BKP_CR_TPE ((uint32_t)0x00000001) |
TAMPER pin enable
| #define BKP_CR_TPE ((uint32_t)0x00000001) |
TAMPER pin enable
| #define BKP_CR_TPE ((uint32_t)0x00000001) |
TAMPER pin enable
| #define BKP_CR_TPE ((uint32_t)0x00000001) |
TAMPER pin enable
| #define BKP_CR_TPE ((uint32_t)0x00000001) |
TAMPER pin enable
| #define BKP_CR_TPE ((uint32_t)0x00000001) |
TAMPER pin enable
| #define BKP_CR_TPE ((uint32_t)0x00000001) |
TAMPER pin enable
| #define BKP_CR_TPE ((uint32_t)0x00000001) |
TAMPER pin enable
| #define BKP_CSR_CTE ((uint32_t)0x00000001) |
Clear Tamper event
| #define BKP_CSR_CTE ((uint32_t)0x00000001) |
Clear Tamper event
| #define BKP_CSR_CTE ((uint32_t)0x00000001) |
Clear Tamper event
| #define BKP_CSR_CTE ((uint32_t)0x00000001) |
Clear Tamper event
| #define BKP_CSR_CTE ((uint32_t)0x00000001) |
Clear Tamper event
| #define BKP_CSR_CTE ((uint32_t)0x00000001) |
Clear Tamper event
| #define BKP_CSR_CTE ((uint32_t)0x00000001) |
Clear Tamper event
| #define BKP_CSR_CTE ((uint32_t)0x00000001) |
Clear Tamper event
| #define BKP_CSR_CTE ((uint32_t)0x00000001) |
Clear Tamper event
| #define BKP_CSR_CTE ((uint32_t)0x00000001) |
Clear Tamper event
| #define BKP_CSR_CTE ((uint32_t)0x00000001) |
Clear Tamper event
| #define BKP_CSR_CTE ((uint32_t)0x00000001) |
Clear Tamper event
| #define BKP_CSR_CTE ((uint32_t)0x00000001) |
Clear Tamper event
| #define BKP_CSR_CTE ((uint32_t)0x00000001) |
Clear Tamper event
| #define BKP_CSR_CTI ((uint32_t)0x00000002) |
Clear Tamper Interrupt
| #define BKP_CSR_CTI ((uint32_t)0x00000002) |
Clear Tamper Interrupt
| #define BKP_CSR_CTI ((uint32_t)0x00000002) |
Clear Tamper Interrupt
| #define BKP_CSR_CTI ((uint32_t)0x00000002) |
Clear Tamper Interrupt
| #define BKP_CSR_CTI ((uint32_t)0x00000002) |
Clear Tamper Interrupt
| #define BKP_CSR_CTI ((uint32_t)0x00000002) |
Clear Tamper Interrupt
| #define BKP_CSR_CTI ((uint32_t)0x00000002) |
Clear Tamper Interrupt
| #define BKP_CSR_CTI ((uint32_t)0x00000002) |
Clear Tamper Interrupt
| #define BKP_CSR_CTI ((uint32_t)0x00000002) |
Clear Tamper Interrupt
| #define BKP_CSR_CTI ((uint32_t)0x00000002) |
Clear Tamper Interrupt
| #define BKP_CSR_CTI ((uint32_t)0x00000002) |
Clear Tamper Interrupt
| #define BKP_CSR_CTI ((uint32_t)0x00000002) |
Clear Tamper Interrupt
| #define BKP_CSR_CTI ((uint32_t)0x00000002) |
Clear Tamper Interrupt
| #define BKP_CSR_CTI ((uint32_t)0x00000002) |
Clear Tamper Interrupt
| #define BKP_CSR_TEF ((uint32_t)0x00000100) |
Tamper Event Flag
| #define BKP_CSR_TEF ((uint32_t)0x00000100) |
Tamper Event Flag
| #define BKP_CSR_TEF ((uint32_t)0x00000100) |
Tamper Event Flag
| #define BKP_CSR_TEF ((uint32_t)0x00000100) |
Tamper Event Flag
| #define BKP_CSR_TEF ((uint32_t)0x00000100) |
Tamper Event Flag
| #define BKP_CSR_TEF ((uint32_t)0x00000100) |
Tamper Event Flag
| #define BKP_CSR_TEF ((uint32_t)0x00000100) |
Tamper Event Flag
| #define BKP_CSR_TEF ((uint32_t)0x00000100) |
Tamper Event Flag
| #define BKP_CSR_TEF ((uint32_t)0x00000100) |
Tamper Event Flag
| #define BKP_CSR_TEF ((uint32_t)0x00000100) |
Tamper Event Flag
| #define BKP_CSR_TEF ((uint32_t)0x00000100) |
Tamper Event Flag
| #define BKP_CSR_TEF ((uint32_t)0x00000100) |
Tamper Event Flag
| #define BKP_CSR_TEF ((uint32_t)0x00000100) |
Tamper Event Flag
| #define BKP_CSR_TEF ((uint32_t)0x00000100) |
Tamper Event Flag
| #define BKP_CSR_TIF ((uint32_t)0x00000200) |
Tamper Interrupt Flag
| #define BKP_CSR_TIF ((uint32_t)0x00000200) |
Tamper Interrupt Flag
| #define BKP_CSR_TIF ((uint32_t)0x00000200) |
Tamper Interrupt Flag
| #define BKP_CSR_TIF ((uint32_t)0x00000200) |
Tamper Interrupt Flag
| #define BKP_CSR_TIF ((uint32_t)0x00000200) |
Tamper Interrupt Flag
| #define BKP_CSR_TIF ((uint32_t)0x00000200) |
Tamper Interrupt Flag
| #define BKP_CSR_TIF ((uint32_t)0x00000200) |
Tamper Interrupt Flag
| #define BKP_CSR_TIF ((uint32_t)0x00000200) |
Tamper Interrupt Flag
| #define BKP_CSR_TIF ((uint32_t)0x00000200) |
Tamper Interrupt Flag
| #define BKP_CSR_TIF ((uint32_t)0x00000200) |
Tamper Interrupt Flag
| #define BKP_CSR_TIF ((uint32_t)0x00000200) |
Tamper Interrupt Flag
| #define BKP_CSR_TIF ((uint32_t)0x00000200) |
Tamper Interrupt Flag
| #define BKP_CSR_TIF ((uint32_t)0x00000200) |
Tamper Interrupt Flag
| #define BKP_CSR_TIF ((uint32_t)0x00000200) |
Tamper Interrupt Flag
| #define BKP_CSR_TPIE ((uint32_t)0x00000004) |
TAMPER Pin interrupt enable
| #define BKP_CSR_TPIE ((uint32_t)0x00000004) |
TAMPER Pin interrupt enable
| #define BKP_CSR_TPIE ((uint32_t)0x00000004) |
TAMPER Pin interrupt enable
| #define BKP_CSR_TPIE ((uint32_t)0x00000004) |
TAMPER Pin interrupt enable
| #define BKP_CSR_TPIE ((uint32_t)0x00000004) |
TAMPER Pin interrupt enable
| #define BKP_CSR_TPIE ((uint32_t)0x00000004) |
TAMPER Pin interrupt enable
| #define BKP_CSR_TPIE ((uint32_t)0x00000004) |
TAMPER Pin interrupt enable
| #define BKP_CSR_TPIE ((uint32_t)0x00000004) |
TAMPER Pin interrupt enable
| #define BKP_CSR_TPIE ((uint32_t)0x00000004) |
TAMPER Pin interrupt enable
| #define BKP_CSR_TPIE ((uint32_t)0x00000004) |
TAMPER Pin interrupt enable
| #define BKP_CSR_TPIE ((uint32_t)0x00000004) |
TAMPER Pin interrupt enable
| #define BKP_CSR_TPIE ((uint32_t)0x00000004) |
TAMPER Pin interrupt enable
| #define BKP_CSR_TPIE ((uint32_t)0x00000004) |
TAMPER Pin interrupt enable
| #define BKP_CSR_TPIE ((uint32_t)0x00000004) |
TAMPER Pin interrupt enable
| #define BKP_DR10_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR10_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR10_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR10_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR10_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR10_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR10_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR10_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR10_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR10_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR10_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR10_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR10_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR10_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR11_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR11_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR11_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR11_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR11_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR11_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR11_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR12_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR12_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR12_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR12_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR12_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR12_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR12_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR13_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR13_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR13_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR13_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR13_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR13_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR13_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR14_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR14_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR14_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR14_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR14_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR14_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR14_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR15_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR15_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR15_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR15_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR15_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR15_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR15_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR16_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR16_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR16_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR16_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR16_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR16_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR16_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR17_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR17_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR17_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR17_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR17_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR17_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR17_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR18_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR18_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR18_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR18_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR18_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR18_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR18_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR19_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR19_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR19_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR19_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR19_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR19_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR19_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR1_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR1_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR1_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR1_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR1_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR1_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR1_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR1_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR1_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR1_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR1_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR1_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR1_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR1_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR20_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR20_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR20_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR20_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR20_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR20_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR20_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR21_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR21_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR21_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR21_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR21_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR21_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR21_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR22_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR22_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR22_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR22_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR22_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR22_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR22_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR23_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR23_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR23_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR23_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR23_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR23_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR23_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR24_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR24_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR24_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR24_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR24_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR24_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR24_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR25_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR25_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR25_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR25_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR25_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR25_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR25_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR26_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR26_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR26_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR26_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR26_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR26_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR26_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR27_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR27_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR27_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR27_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR27_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR27_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR27_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR28_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR28_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR28_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR28_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR28_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR28_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR28_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR29_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR29_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR29_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR29_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR29_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR29_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR29_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR2_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR2_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR2_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR2_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR2_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR2_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR2_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR2_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR2_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR2_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR2_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR2_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR2_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR2_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR30_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR30_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR30_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR30_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR30_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR30_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR30_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR31_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR31_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR31_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR31_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR31_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR31_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR31_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR32_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR32_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR32_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR32_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR32_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR32_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR32_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR33_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR33_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR33_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR33_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR33_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR33_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR33_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR34_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR34_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR34_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR34_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR34_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR34_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR34_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR35_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR35_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR35_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR35_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR35_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR35_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR35_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR36_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR36_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR36_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR36_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR36_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR36_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR36_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR37_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR37_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR37_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR37_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR37_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR37_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR37_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR38_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR38_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR38_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR38_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR38_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR38_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR38_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR39_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR39_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR39_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR39_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR39_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR39_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR39_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR3_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR3_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR3_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR3_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR3_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR3_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR3_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR3_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR3_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR3_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR3_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR3_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR3_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR3_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR40_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR40_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR40_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR40_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR40_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR40_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR40_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR41_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR41_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR41_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR41_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR41_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR41_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR41_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR42_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR42_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR42_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR42_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR42_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR42_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR42_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR4_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR4_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR4_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR4_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR4_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR4_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR4_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR4_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR4_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR4_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR4_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR4_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR4_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR4_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR5_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR5_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR5_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR5_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR5_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR5_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR5_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR5_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR5_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR5_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR5_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR5_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR5_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR5_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR6_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR6_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR6_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR6_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR6_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR6_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR6_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR6_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR6_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR6_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR6_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR6_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR6_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR6_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR7_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR7_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR7_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR7_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR7_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR7_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR7_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR7_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR7_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR7_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR7_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR7_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR7_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR7_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR8_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR8_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR8_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR8_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR8_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR8_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR8_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR8_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR8_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR8_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR8_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR8_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR8_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR8_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR9_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR9_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR9_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR9_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR9_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR9_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR9_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR9_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR9_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR9_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR9_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR9_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR9_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_DR9_D ((uint32_t)0x0000FFFF) |
Backup data
| #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
Alarm or Second Output Enable
| #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
Alarm or Second Output Enable
| #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
Alarm or Second Output Enable
| #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
Alarm or Second Output Enable
| #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
Alarm or Second Output Enable
| #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
Alarm or Second Output Enable
| #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
Alarm or Second Output Enable
| #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
Alarm or Second Output Enable
| #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
Alarm or Second Output Enable
| #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
Alarm or Second Output Enable
| #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
Alarm or Second Output Enable
| #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
Alarm or Second Output Enable
| #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
Alarm or Second Output Enable
| #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) |
Alarm or Second Output Enable
| #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
Alarm or Second Output Selection
| #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
Alarm or Second Output Selection
| #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
Alarm or Second Output Selection
| #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
Alarm or Second Output Selection
| #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
Alarm or Second Output Selection
| #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
Alarm or Second Output Selection
| #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
Alarm or Second Output Selection
| #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
Alarm or Second Output Selection
| #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
Alarm or Second Output Selection
| #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
Alarm or Second Output Selection
| #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
Alarm or Second Output Selection
| #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
Alarm or Second Output Selection
| #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
Alarm or Second Output Selection
| #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) |
Alarm or Second Output Selection
| #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
Calibration value
| #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
Calibration value
| #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
Calibration value
| #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
Calibration value
| #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
Calibration value
| #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
Calibration value
| #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
Calibration value
| #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
Calibration value
| #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
Calibration value
| #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
Calibration value
| #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
Calibration value
| #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
Calibration value
| #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
Calibration value
| #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) |
Calibration value
| #define BKP_RTCCR_CCO ((uint32_t)0x00000080) |
Calibration Clock Output
| #define BKP_RTCCR_CCO ((uint32_t)0x00000080) |
Calibration Clock Output
| #define BKP_RTCCR_CCO ((uint32_t)0x00000080) |
Calibration Clock Output
| #define BKP_RTCCR_CCO ((uint32_t)0x00000080) |
Calibration Clock Output
| #define BKP_RTCCR_CCO ((uint32_t)0x00000080) |
Calibration Clock Output
| #define BKP_RTCCR_CCO ((uint32_t)0x00000080) |
Calibration Clock Output
| #define BKP_RTCCR_CCO ((uint32_t)0x00000080) |
Calibration Clock Output
| #define BKP_RTCCR_CCO ((uint32_t)0x00000080) |
Calibration Clock Output
| #define BKP_RTCCR_CCO ((uint32_t)0x00000080) |
Calibration Clock Output
| #define BKP_RTCCR_CCO ((uint32_t)0x00000080) |
Calibration Clock Output
| #define BKP_RTCCR_CCO ((uint32_t)0x00000080) |
Calibration Clock Output
| #define BKP_RTCCR_CCO ((uint32_t)0x00000080) |
Calibration Clock Output
| #define BKP_RTCCR_CCO ((uint32_t)0x00000080) |
Calibration Clock Output
| #define BKP_RTCCR_CCO ((uint32_t)0x00000080) |
Calibration Clock Output
| #define CAN_BTR_BRP ((uint32_t)0x000003FF) |
Baud Rate Prescaler
| #define CAN_BTR_BRP ((uint32_t)0x000003FF) |
Baud Rate Prescaler
| #define CAN_BTR_BRP ((uint32_t)0x000003FF) |
Baud Rate Prescaler
| #define CAN_BTR_BRP ((uint32_t)0x000003FF) |
Baud Rate Prescaler
| #define CAN_BTR_BRP ((uint32_t)0x000003FF) |
Baud Rate Prescaler
| #define CAN_BTR_BRP ((uint32_t)0x000003FF) |
Baud Rate Prescaler
| #define CAN_BTR_LBKM ((uint32_t)0x40000000) |
Loop Back Mode (Debug)
| #define CAN_BTR_LBKM ((uint32_t)0x40000000) |
Loop Back Mode (Debug)
| #define CAN_BTR_LBKM ((uint32_t)0x40000000) |
Loop Back Mode (Debug)
| #define CAN_BTR_LBKM ((uint32_t)0x40000000) |
Loop Back Mode (Debug)
| #define CAN_BTR_LBKM ((uint32_t)0x40000000) |
Loop Back Mode (Debug)
| #define CAN_BTR_LBKM ((uint32_t)0x40000000) |
Loop Back Mode (Debug)
| #define CAN_BTR_SILM ((uint32_t)0x80000000) |
Silent Mode Mailbox registers
| #define CAN_BTR_SILM ((uint32_t)0x80000000) |
Silent Mode Mailbox registers
| #define CAN_BTR_SILM ((uint32_t)0x80000000) |
Silent Mode Mailbox registers
| #define CAN_BTR_SILM ((uint32_t)0x80000000) |
Silent Mode Mailbox registers
| #define CAN_BTR_SILM ((uint32_t)0x80000000) |
Silent Mode Mailbox registers
| #define CAN_BTR_SILM ((uint32_t)0x80000000) |
Silent Mode Mailbox registers
| #define CAN_BTR_SJW ((uint32_t)0x03000000) |
Resynchronization Jump Width
| #define CAN_BTR_SJW ((uint32_t)0x03000000) |
Resynchronization Jump Width
| #define CAN_BTR_SJW ((uint32_t)0x03000000) |
Resynchronization Jump Width
| #define CAN_BTR_SJW ((uint32_t)0x03000000) |
Resynchronization Jump Width
| #define CAN_BTR_SJW ((uint32_t)0x03000000) |
Resynchronization Jump Width
| #define CAN_BTR_SJW ((uint32_t)0x03000000) |
Resynchronization Jump Width
| #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) |
Resynchronization Jump Width (Bit 0)
| #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) |
Resynchronization Jump Width (Bit 0)
| #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) |
Resynchronization Jump Width (Bit 0)
| #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) |
Resynchronization Jump Width (Bit 0)
| #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) |
Resynchronization Jump Width (Bit 0)
| #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) |
Resynchronization Jump Width (Bit 0)
| #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) |
Resynchronization Jump Width (Bit 1)
| #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) |
Resynchronization Jump Width (Bit 1)
| #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) |
Resynchronization Jump Width (Bit 1)
| #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) |
Resynchronization Jump Width (Bit 1)
| #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) |
Resynchronization Jump Width (Bit 1)
| #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) |
Resynchronization Jump Width (Bit 1)
| #define CAN_BTR_TS1 ((uint32_t)0x000F0000) |
Time Segment 1
| #define CAN_BTR_TS1 ((uint32_t)0x000F0000) |
Time Segment 1
| #define CAN_BTR_TS1 ((uint32_t)0x000F0000) |
Time Segment 1
| #define CAN_BTR_TS1 ((uint32_t)0x000F0000) |
Time Segment 1
| #define CAN_BTR_TS1 ((uint32_t)0x000F0000) |
Time Segment 1
| #define CAN_BTR_TS1 ((uint32_t)0x000F0000) |
Time Segment 1
| #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) |
Time Segment 1 (Bit 0)
| #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) |
Time Segment 1 (Bit 0)
| #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) |
Time Segment 1 (Bit 0)
| #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) |
Time Segment 1 (Bit 0)
| #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) |
Time Segment 1 (Bit 0)
| #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) |
Time Segment 1 (Bit 0)
| #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) |
Time Segment 1 (Bit 1)
| #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) |
Time Segment 1 (Bit 1)
| #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) |
Time Segment 1 (Bit 1)
| #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) |
Time Segment 1 (Bit 1)
| #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) |
Time Segment 1 (Bit 1)
| #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) |
Time Segment 1 (Bit 1)
| #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) |
Time Segment 1 (Bit 2)
| #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) |
Time Segment 1 (Bit 2)
| #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) |
Time Segment 1 (Bit 2)
| #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) |
Time Segment 1 (Bit 2)
| #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) |
Time Segment 1 (Bit 2)
| #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) |
Time Segment 1 (Bit 2)
| #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) |
Time Segment 1 (Bit 3)
| #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) |
Time Segment 1 (Bit 3)
| #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) |
Time Segment 1 (Bit 3)
| #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) |
Time Segment 1 (Bit 3)
| #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) |
Time Segment 1 (Bit 3)
| #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) |
Time Segment 1 (Bit 3)
| #define CAN_BTR_TS2 ((uint32_t)0x00700000) |
Time Segment 2
| #define CAN_BTR_TS2 ((uint32_t)0x00700000) |
Time Segment 2
| #define CAN_BTR_TS2 ((uint32_t)0x00700000) |
Time Segment 2
| #define CAN_BTR_TS2 ((uint32_t)0x00700000) |
Time Segment 2
| #define CAN_BTR_TS2 ((uint32_t)0x00700000) |
Time Segment 2
| #define CAN_BTR_TS2 ((uint32_t)0x00700000) |
Time Segment 2
| #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) |
Time Segment 2 (Bit 0)
| #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) |
Time Segment 2 (Bit 0)
| #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) |
Time Segment 2 (Bit 0)
| #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) |
Time Segment 2 (Bit 0)
| #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) |
Time Segment 2 (Bit 0)
| #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) |
Time Segment 2 (Bit 0)
| #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) |
Time Segment 2 (Bit 1)
| #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) |
Time Segment 2 (Bit 1)
| #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) |
Time Segment 2 (Bit 1)
| #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) |
Time Segment 2 (Bit 1)
| #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) |
Time Segment 2 (Bit 1)
| #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) |
Time Segment 2 (Bit 1)
| #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) |
Time Segment 2 (Bit 2)
| #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) |
Time Segment 2 (Bit 2)
| #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) |
Time Segment 2 (Bit 2)
| #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) |
Time Segment 2 (Bit 2)
| #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) |
Time Segment 2 (Bit 2)
| #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) |
Time Segment 2 (Bit 2)
| #define CAN_ESR_BOFF ((uint32_t)0x00000004) |
Bus-Off Flag
| #define CAN_ESR_BOFF ((uint32_t)0x00000004) |
Bus-Off Flag
| #define CAN_ESR_BOFF ((uint32_t)0x00000004) |
Bus-Off Flag
| #define CAN_ESR_BOFF ((uint32_t)0x00000004) |
Bus-Off Flag
| #define CAN_ESR_BOFF ((uint32_t)0x00000004) |
Bus-Off Flag
| #define CAN_ESR_BOFF ((uint32_t)0x00000004) |
Bus-Off Flag
| #define CAN_ESR_EPVF ((uint32_t)0x00000002) |
Error Passive Flag
| #define CAN_ESR_EPVF ((uint32_t)0x00000002) |
Error Passive Flag
| #define CAN_ESR_EPVF ((uint32_t)0x00000002) |
Error Passive Flag
| #define CAN_ESR_EPVF ((uint32_t)0x00000002) |
Error Passive Flag
| #define CAN_ESR_EPVF ((uint32_t)0x00000002) |
Error Passive Flag
| #define CAN_ESR_EPVF ((uint32_t)0x00000002) |
Error Passive Flag
| #define CAN_ESR_EWGF ((uint32_t)0x00000001) |
Error Warning Flag
| #define CAN_ESR_EWGF ((uint32_t)0x00000001) |
Error Warning Flag
| #define CAN_ESR_EWGF ((uint32_t)0x00000001) |
Error Warning Flag
| #define CAN_ESR_EWGF ((uint32_t)0x00000001) |
Error Warning Flag
| #define CAN_ESR_EWGF ((uint32_t)0x00000001) |
Error Warning Flag
| #define CAN_ESR_EWGF ((uint32_t)0x00000001) |
Error Warning Flag
| #define CAN_ESR_LEC ((uint32_t)0x00000070) |
LEC[2:0] bits (Last Error Code)
| #define CAN_ESR_LEC ((uint32_t)0x00000070) |
LEC[2:0] bits (Last Error Code)
| #define CAN_ESR_LEC ((uint32_t)0x00000070) |
LEC[2:0] bits (Last Error Code)
| #define CAN_ESR_LEC ((uint32_t)0x00000070) |
LEC[2:0] bits (Last Error Code)
| #define CAN_ESR_LEC ((uint32_t)0x00000070) |
LEC[2:0] bits (Last Error Code)
| #define CAN_ESR_LEC ((uint32_t)0x00000070) |
LEC[2:0] bits (Last Error Code)
| #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
Bit 0
| #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
Bit 0
| #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
Bit 0
| #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
Bit 0
| #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
Bit 0
| #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
Bit 0
| #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
Bit 1
| #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
Bit 1
| #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
Bit 1
| #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
Bit 1
| #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
Bit 1
| #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
Bit 1
| #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
Bit 2
| #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
Bit 2
| #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
Bit 2
| #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
Bit 2
| #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
Bit 2
| #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
Bit 2
| #define CAN_ESR_REC ((uint32_t)0xFF000000) |
Receive Error Counter
| #define CAN_ESR_REC ((uint32_t)0xFF000000) |
Receive Error Counter
| #define CAN_ESR_REC ((uint32_t)0xFF000000) |
Receive Error Counter
| #define CAN_ESR_REC ((uint32_t)0xFF000000) |
Receive Error Counter
| #define CAN_ESR_REC ((uint32_t)0xFF000000) |
Receive Error Counter
| #define CAN_ESR_REC ((uint32_t)0xFF000000) |
Receive Error Counter
| #define CAN_ESR_TEC ((uint32_t)0x00FF0000) |
Least significant byte of the 9-bit Transmit Error Counter
| #define CAN_ESR_TEC ((uint32_t)0x00FF0000) |
Least significant byte of the 9-bit Transmit Error Counter
| #define CAN_ESR_TEC ((uint32_t)0x00FF0000) |
Least significant byte of the 9-bit Transmit Error Counter
| #define CAN_ESR_TEC ((uint32_t)0x00FF0000) |
Least significant byte of the 9-bit Transmit Error Counter
| #define CAN_ESR_TEC ((uint32_t)0x00FF0000) |
Least significant byte of the 9-bit Transmit Error Counter
| #define CAN_ESR_TEC ((uint32_t)0x00FF0000) |
Least significant byte of the 9-bit Transmit Error Counter
| #define CAN_F0R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F0R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F0R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F0R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F0R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F0R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F0R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F0R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F0R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F0R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F0R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F0R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F0R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F0R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F0R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F0R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F0R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F0R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F0R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F0R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F0R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F0R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F0R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F0R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F0R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F0R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F0R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F0R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F0R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F0R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F0R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F0R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F0R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F0R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F0R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F0R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F0R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F0R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F0R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F0R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F0R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F0R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F0R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F0R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F0R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F0R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F0R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F0R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F0R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F0R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F0R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F0R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F0R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F0R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F0R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F0R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F0R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F0R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F0R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F0R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F0R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F0R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F0R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F0R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F0R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F0R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F0R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F0R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F0R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F0R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F0R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F0R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F0R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F0R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F0R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F0R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F0R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F0R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F0R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F0R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F0R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F0R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F0R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F0R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F0R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F0R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F0R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F0R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F0R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F0R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F0R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F0R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F0R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F0R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F0R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F0R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F0R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F0R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F0R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F0R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F0R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F0R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F0R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F0R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F0R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F0R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F0R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F0R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F0R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F0R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F0R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F0R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F0R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F0R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F0R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F0R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F0R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F0R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F0R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F0R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F0R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F0R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F0R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F0R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F0R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F0R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F0R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F0R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F0R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F0R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F0R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F0R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F0R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F0R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F0R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F0R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F0R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F0R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F0R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F0R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F0R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F0R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F0R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F0R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F0R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F0R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F0R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F0R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F0R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F0R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F0R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F0R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F0R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F0R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F0R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F0R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F0R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F0R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F0R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F0R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F0R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F0R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F0R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F0R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F0R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F0R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F0R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F0R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F0R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F0R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F0R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F0R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F0R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F0R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F0R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F0R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F0R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F0R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F0R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F0R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F0R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F0R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F0R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F0R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F0R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F0R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F0R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F0R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F0R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F0R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F0R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F0R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F0R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F0R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F0R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F0R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F0R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F0R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F0R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F0R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F0R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F0R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F0R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F0R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F0R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F0R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F0R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F0R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F0R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F0R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F0R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F0R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F0R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F0R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F0R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F0R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F0R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F0R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F0R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F0R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F0R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F0R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F0R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F0R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F0R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F0R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F0R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F0R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F0R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F0R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F0R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F0R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F0R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F0R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F0R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F0R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F0R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F0R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F0R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F0R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F0R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F0R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F0R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F0R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F0R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F0R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F0R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F0R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F0R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F0R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F0R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F0R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F0R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F0R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F0R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F0R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F0R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F0R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F0R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F0R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F0R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F0R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F0R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F0R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F0R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F0R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F0R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F0R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F0R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F0R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F0R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F0R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F0R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F0R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F0R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F0R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F0R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F0R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F0R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F0R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F0R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F0R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F0R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F0R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F0R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F0R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F0R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F0R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F0R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F0R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F0R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F0R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F0R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F0R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F0R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F0R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F0R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F0R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F0R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F0R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F0R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F0R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F0R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F0R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F0R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F0R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F0R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F0R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F0R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F0R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F0R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F0R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F0R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F0R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F0R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F0R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F0R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F0R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F0R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F0R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F0R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F0R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F0R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F0R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F0R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F0R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F0R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F0R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F0R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F0R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F0R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F0R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F0R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F0R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F0R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F0R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F0R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F0R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F0R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F0R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F0R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F0R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F0R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F0R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F0R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F0R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F0R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F0R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F0R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F0R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F0R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F0R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F0R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F0R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F0R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F0R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F0R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F0R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F0R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F0R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F0R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F0R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F0R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F0R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F0R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F0R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F0R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F0R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F0R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F0R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F0R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F0R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F0R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F0R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F0R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F0R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F0R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F0R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F0R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F0R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F0R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F0R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F0R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F0R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F10R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F10R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F10R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F10R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F10R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F10R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F10R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F10R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F10R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F10R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F10R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F10R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F10R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F10R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F10R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F10R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F10R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F10R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F10R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F10R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F10R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F10R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F10R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F10R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F10R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F10R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F10R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F10R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F10R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F10R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F10R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F10R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F10R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F10R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F10R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F10R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F10R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F10R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F10R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F10R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F10R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F10R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F10R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F10R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F10R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F10R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F10R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F10R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F10R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F10R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F10R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F10R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F10R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F10R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F10R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F10R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F10R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F10R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F10R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F10R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F10R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F10R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F10R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F10R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F10R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F10R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F10R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F10R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F10R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F10R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F10R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F10R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F10R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F10R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F10R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F10R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F10R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F10R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F10R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F10R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F10R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F10R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F10R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F10R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F10R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F10R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F10R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F10R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F10R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F10R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F10R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F10R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F10R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F10R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F10R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F10R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F10R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F10R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F10R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F10R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F10R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F10R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F10R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F10R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F10R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F10R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F10R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F10R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F10R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F10R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F10R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F10R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F10R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F10R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F10R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F10R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F10R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F10R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F10R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F10R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F10R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F10R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F10R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F10R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F10R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F10R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F10R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F10R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F10R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F10R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F10R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F10R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F10R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F10R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F10R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F10R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F10R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F10R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F10R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F10R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F10R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F10R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F10R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F10R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F10R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F10R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F10R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F10R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F10R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F10R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F10R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F10R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F10R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F10R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F10R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F10R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F10R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F10R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F10R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F10R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F10R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F10R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F10R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F10R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F10R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F10R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F10R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F10R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F10R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F10R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F10R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F10R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F10R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F10R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F10R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F10R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F10R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F10R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F10R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F10R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F10R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F10R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F10R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F10R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F10R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F10R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F10R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F10R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F10R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F10R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F10R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F10R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F10R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F10R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F10R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F10R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F10R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F10R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F10R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F10R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F10R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F10R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F10R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F10R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F10R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F10R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F10R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F10R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F10R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F10R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F10R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F10R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F10R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F10R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F10R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F10R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F10R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F10R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F10R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F10R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F10R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F10R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F10R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F10R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F10R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F10R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F10R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F10R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F10R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F10R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F10R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F10R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F10R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F10R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F10R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F10R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F10R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F10R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F10R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F10R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F10R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F10R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F10R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F10R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F10R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F10R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F10R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F10R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F10R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F10R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F10R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F10R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F10R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F10R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F10R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F10R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F10R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F10R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F10R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F10R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F10R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F10R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F10R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F10R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F10R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F10R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F10R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F10R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F10R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F10R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F10R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F10R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F10R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F10R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F10R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F10R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F10R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F10R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F10R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F10R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F10R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F10R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F10R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F10R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F10R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F10R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F10R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F10R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F10R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F10R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F10R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F10R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F10R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F10R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F10R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F10R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F10R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F10R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F10R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F10R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F10R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F10R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F10R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F10R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F10R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F10R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F10R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F10R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F10R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F10R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F10R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F10R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F10R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F10R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F10R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F10R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F10R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F10R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F10R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F10R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F10R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F10R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F10R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F10R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F10R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F10R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F10R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F10R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F10R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F10R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F10R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F10R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F10R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F10R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F10R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F10R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F10R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F10R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F10R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F10R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F10R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F10R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F10R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F10R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F10R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F10R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F10R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F10R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F10R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F10R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F10R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F10R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F10R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F10R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F10R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F10R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F10R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F10R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F10R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F10R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F10R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F10R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F10R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F10R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F10R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F10R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F10R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F10R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F10R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F10R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F10R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F10R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F10R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F10R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F10R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F10R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F10R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F10R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F10R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F10R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F10R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F10R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F10R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F10R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F11R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F11R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F11R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F11R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F11R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F11R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F11R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F11R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F11R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F11R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F11R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F11R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F11R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F11R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F11R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F11R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F11R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F11R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F11R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F11R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F11R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F11R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F11R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F11R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F11R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F11R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F11R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F11R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F11R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F11R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F11R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F11R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F11R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F11R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F11R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F11R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F11R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F11R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F11R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F11R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F11R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F11R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F11R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F11R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F11R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F11R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F11R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F11R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F11R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F11R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F11R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F11R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F11R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F11R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F11R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F11R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F11R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F11R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F11R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F11R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F11R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F11R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F11R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F11R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F11R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F11R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F11R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F11R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F11R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F11R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F11R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F11R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F11R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F11R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F11R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F11R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F11R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F11R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F11R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F11R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F11R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F11R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F11R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F11R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F11R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F11R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F11R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F11R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F11R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F11R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F11R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F11R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F11R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F11R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F11R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F11R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F11R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F11R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F11R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F11R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F11R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F11R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F11R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F11R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F11R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F11R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F11R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F11R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F11R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F11R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F11R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F11R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F11R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F11R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F11R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F11R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F11R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F11R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F11R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F11R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F11R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F11R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F11R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F11R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F11R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F11R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F11R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F11R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F11R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F11R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F11R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F11R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F11R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F11R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F11R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F11R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F11R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F11R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F11R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F11R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F11R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F11R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F11R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F11R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F11R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F11R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F11R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F11R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F11R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F11R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F11R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F11R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F11R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F11R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F11R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F11R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F11R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F11R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F11R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F11R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F11R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F11R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F11R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F11R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F11R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F11R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F11R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F11R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F11R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F11R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F11R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F11R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F11R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F11R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F11R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F11R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F11R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F11R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F11R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F11R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F11R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F11R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F11R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F11R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F11R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F11R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F11R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F11R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F11R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F11R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F11R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F11R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F11R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F11R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F11R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F11R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F11R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F11R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F11R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F11R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F11R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F11R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F11R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F11R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F11R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F11R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F11R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F11R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F11R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F11R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F11R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F11R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F11R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F11R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F11R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F11R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F11R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F11R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F11R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F11R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F11R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F11R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F11R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F11R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F11R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F11R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F11R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F11R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F11R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F11R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F11R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F11R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F11R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F11R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F11R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F11R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F11R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F11R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F11R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F11R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F11R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F11R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F11R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F11R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F11R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F11R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F11R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F11R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F11R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F11R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F11R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F11R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F11R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F11R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F11R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F11R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F11R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F11R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F11R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F11R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F11R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F11R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F11R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F11R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F11R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F11R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F11R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F11R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F11R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F11R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F11R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F11R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F11R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F11R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F11R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F11R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F11R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F11R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F11R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F11R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F11R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F11R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F11R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F11R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F11R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F11R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F11R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F11R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F11R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F11R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F11R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F11R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F11R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F11R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F11R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F11R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F11R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F11R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F11R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F11R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F11R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F11R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F11R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F11R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F11R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F11R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F11R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F11R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F11R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F11R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F11R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F11R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F11R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F11R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F11R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F11R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F11R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F11R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F11R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F11R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F11R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F11R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F11R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F11R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F11R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F11R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F11R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F11R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F11R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F11R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F11R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F11R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F11R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F11R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F11R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F11R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F11R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F11R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F11R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F11R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F11R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F11R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F11R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F11R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F11R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F11R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F11R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F11R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F11R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F11R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F11R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F11R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F11R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F11R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F11R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F11R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F11R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F11R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F11R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F11R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F11R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F11R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F11R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F11R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F11R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F11R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F11R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F11R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F11R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F11R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F11R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F11R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F11R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F11R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F11R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F11R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F11R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F11R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F11R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F11R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F11R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F11R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F11R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F11R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F12R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F12R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F12R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F12R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F12R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F12R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F12R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F12R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F12R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F12R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F12R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F12R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F12R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F12R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F12R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F12R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F12R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F12R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F12R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F12R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F12R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F12R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F12R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F12R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F12R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F12R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F12R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F12R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F12R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F12R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F12R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F12R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F12R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F12R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F12R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F12R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F12R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F12R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F12R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F12R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F12R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F12R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F12R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F12R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F12R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F12R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F12R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F12R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F12R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F12R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F12R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F12R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F12R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F12R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F12R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F12R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F12R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F12R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F12R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F12R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F12R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F12R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F12R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F12R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F12R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F12R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F12R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F12R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F12R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F12R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F12R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F12R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F12R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F12R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F12R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F12R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F12R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F12R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F12R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F12R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F12R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F12R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F12R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F12R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F12R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F12R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F12R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F12R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F12R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F12R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F12R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F12R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F12R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F12R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F12R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F12R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F12R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F12R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F12R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F12R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F12R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F12R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F12R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F12R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F12R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F12R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F12R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F12R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F12R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F12R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F12R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F12R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F12R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F12R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F12R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F12R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F12R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F12R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F12R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F12R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F12R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F12R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F12R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F12R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F12R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F12R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F12R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F12R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F12R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F12R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F12R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F12R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F12R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F12R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F12R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F12R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F12R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F12R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F12R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F12R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F12R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F12R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F12R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F12R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F12R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F12R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F12R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F12R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F12R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F12R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F12R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F12R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F12R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F12R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F12R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F12R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F12R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F12R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F12R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F12R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F12R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F12R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F12R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F12R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F12R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F12R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F12R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F12R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F12R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F12R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F12R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F12R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F12R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F12R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F12R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F12R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F12R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F12R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F12R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F12R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F12R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F12R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F12R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F12R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F12R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F12R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F12R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F12R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F12R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F12R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F12R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F12R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F12R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F12R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F12R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F12R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F12R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F12R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F12R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F12R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F12R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F12R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F12R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F12R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F12R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F12R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F12R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F12R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F12R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F12R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F12R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F12R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F12R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F12R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F12R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F12R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F12R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F12R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F12R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F12R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F12R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F12R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F12R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F12R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F12R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F12R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F12R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F12R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F12R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F12R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F12R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F12R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F12R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F12R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F12R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F12R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F12R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F12R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F12R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F12R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F12R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F12R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F12R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F12R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F12R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F12R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F12R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F12R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F12R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F12R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F12R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F12R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F12R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F12R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F12R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F12R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F12R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F12R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F12R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F12R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F12R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F12R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F12R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F12R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F12R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F12R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F12R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F12R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F12R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F12R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F12R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F12R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F12R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F12R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F12R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F12R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F12R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F12R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F12R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F12R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F12R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F12R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F12R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F12R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F12R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F12R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F12R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F12R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F12R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F12R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F12R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F12R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F12R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F12R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F12R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F12R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F12R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F12R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F12R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F12R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F12R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F12R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F12R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F12R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F12R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F12R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F12R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F12R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F12R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F12R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F12R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F12R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F12R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F12R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F12R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F12R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F12R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F12R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F12R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F12R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F12R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F12R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F12R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F12R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F12R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F12R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F12R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F12R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F12R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F12R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F12R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F12R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F12R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F12R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F12R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F12R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F12R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F12R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F12R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F12R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F12R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F12R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F12R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F12R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F12R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F12R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F12R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F12R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F12R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F12R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F12R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F12R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F12R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F12R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F12R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F12R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F12R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F12R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F12R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F12R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F12R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F12R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F12R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F12R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F12R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F12R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F12R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F12R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F12R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F12R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F12R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F12R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F12R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F12R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F12R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F12R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F12R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F12R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F12R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F12R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F12R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F12R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F12R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F12R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F13R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F13R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F13R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F13R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F13R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F13R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F13R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F13R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F13R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F13R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F13R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F13R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F13R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F13R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F13R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F13R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F13R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F13R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F13R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F13R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F13R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F13R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F13R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F13R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F13R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F13R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F13R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F13R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F13R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F13R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F13R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F13R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F13R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F13R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F13R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F13R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F13R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F13R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F13R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F13R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F13R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F13R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F13R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F13R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F13R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F13R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F13R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F13R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F13R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F13R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F13R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F13R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F13R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F13R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F13R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F13R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F13R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F13R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F13R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F13R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F13R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F13R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F13R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F13R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F13R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F13R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F13R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F13R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F13R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F13R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F13R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F13R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F13R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F13R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F13R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F13R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F13R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F13R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F13R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F13R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F13R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F13R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F13R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F13R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F13R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F13R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F13R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F13R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F13R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F13R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F13R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F13R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F13R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F13R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F13R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F13R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F13R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F13R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F13R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F13R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F13R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F13R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F13R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F13R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F13R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F13R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F13R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F13R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F13R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F13R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F13R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F13R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F13R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F13R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F13R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F13R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F13R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F13R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F13R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F13R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F13R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F13R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F13R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F13R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F13R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F13R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F13R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F13R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F13R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F13R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F13R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F13R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F13R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F13R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F13R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F13R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F13R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F13R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F13R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F13R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F13R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F13R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F13R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F13R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F13R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F13R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F13R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F13R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F13R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F13R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F13R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F13R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F13R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F13R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F13R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F13R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F13R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F13R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F13R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F13R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F13R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F13R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F13R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F13R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F13R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F13R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F13R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F13R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F13R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F13R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F13R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F13R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F13R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F13R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F13R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F13R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F13R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F13R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F13R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F13R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F13R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F13R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F13R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F13R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F13R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F13R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F13R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F13R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F13R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F13R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F13R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F13R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F13R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F13R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F13R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F13R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F13R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F13R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F13R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F13R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F13R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F13R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F13R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F13R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F13R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F13R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F13R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F13R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F13R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F13R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F13R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F13R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F13R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F13R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F13R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F13R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F13R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F13R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F13R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F13R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F13R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F13R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F13R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F13R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F13R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F13R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F13R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F13R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F13R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F13R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F13R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F13R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F13R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F13R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F13R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F13R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F13R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F13R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F13R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F13R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F13R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F13R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F13R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F13R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F13R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F13R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F13R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F13R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F13R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F13R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F13R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F13R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F13R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F13R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F13R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F13R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F13R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F13R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F13R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F13R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F13R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F13R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F13R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F13R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F13R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F13R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F13R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F13R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F13R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F13R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F13R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F13R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F13R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F13R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F13R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F13R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F13R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F13R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F13R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F13R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F13R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F13R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F13R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F13R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F13R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F13R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F13R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F13R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F13R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F13R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F13R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F13R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F13R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F13R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F13R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F13R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F13R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F13R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F13R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F13R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F13R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F13R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F13R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F13R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F13R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F13R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F13R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F13R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F13R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F13R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F13R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F13R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F13R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F13R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F13R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F13R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F13R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F13R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F13R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F13R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F13R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F13R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F13R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F13R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F13R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F13R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F13R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F13R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F13R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F13R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F13R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F13R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F13R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F13R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F13R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F13R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F13R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F13R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F13R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F13R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F13R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F13R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F13R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F13R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F13R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F13R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F13R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F13R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F13R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F13R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F13R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F13R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F13R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F13R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F13R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F13R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F13R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F13R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F13R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F13R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F13R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F13R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F13R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F13R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F13R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F13R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F13R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F13R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F13R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F13R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F13R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F13R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F13R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F13R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F13R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F13R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F13R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F13R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F13R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F13R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F13R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F13R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F13R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F13R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F14R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F14R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F14R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F14R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F14R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F14R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F14R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F14R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F14R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F14R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F14R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F14R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F14R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F14R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F14R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F14R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F14R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F14R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F14R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F14R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F14R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F14R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F14R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F14R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F14R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F14R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F14R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F14R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F14R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F14R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F14R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F14R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F14R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F14R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F14R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F14R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F14R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F14R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F14R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F14R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F14R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F14R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F14R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F14R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F14R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F14R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F14R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F14R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F14R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F14R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F14R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F14R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F14R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F14R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F14R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F14R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F14R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F14R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F14R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F14R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F14R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F14R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F14R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F14R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F14R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F14R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F14R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F14R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F14R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F14R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F14R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F14R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F14R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F14R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F14R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F14R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F14R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F14R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F14R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F14R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F14R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F14R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F14R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F14R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F14R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F14R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F14R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F14R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F14R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F14R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F14R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F14R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F14R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F14R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F14R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F14R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F14R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F14R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F14R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F14R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F14R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F14R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F14R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F14R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F14R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F14R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F14R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F14R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F14R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F14R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F14R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F14R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F14R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F14R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F14R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F14R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F14R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F14R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F14R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F14R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F14R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F14R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F14R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F14R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F14R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F14R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F14R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F14R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F15R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F15R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F15R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F15R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F15R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F15R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F15R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F15R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F15R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F15R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F15R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F15R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F15R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F15R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F15R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F15R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F15R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F15R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F15R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F15R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F15R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F15R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F15R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F15R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F15R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F15R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F15R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F15R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F15R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F15R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F15R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F15R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F15R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F15R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F15R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F15R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F15R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F15R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F15R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F15R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F15R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F15R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F15R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F15R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F15R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F15R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F15R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F15R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F15R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F15R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F15R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F15R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F15R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F15R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F15R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F15R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F15R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F15R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F15R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F15R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F15R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F15R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F15R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F15R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F15R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F15R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F15R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F15R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F15R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F15R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F15R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F15R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F15R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F15R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F15R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F15R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F15R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F15R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F15R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F15R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F15R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F15R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F15R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F15R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F15R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F15R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F15R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F15R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F15R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F15R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F15R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F15R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F15R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F15R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F15R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F15R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F15R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F15R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F15R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F15R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F15R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F15R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F15R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F15R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F15R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F15R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F15R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F15R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F15R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F15R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F15R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F15R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F15R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F15R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F15R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F15R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F15R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F15R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F15R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F15R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F15R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F15R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F15R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F15R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F15R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F15R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F15R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F15R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F16R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F16R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F16R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F16R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F16R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F16R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F16R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F16R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F16R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F16R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F16R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F16R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F16R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F16R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F16R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F16R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F16R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F16R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F16R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F16R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F16R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F16R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F16R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F16R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F16R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F16R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F16R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F16R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F16R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F16R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F16R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F16R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F16R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F16R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F16R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F16R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F16R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F16R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F16R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F16R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F16R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F16R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F16R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F16R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F16R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F16R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F16R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F16R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F16R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F16R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F16R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F16R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F16R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F16R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F16R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F16R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F16R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F16R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F16R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F16R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F16R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F16R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F16R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F16R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F16R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F16R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F16R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F16R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F16R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F16R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F16R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F16R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F16R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F16R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F16R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F16R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F16R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F16R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F16R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F16R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F16R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F16R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F16R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F16R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F16R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F16R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F16R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F16R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F16R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F16R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F16R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F16R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F16R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F16R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F16R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F16R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F16R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F16R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F16R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F16R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F16R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F16R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F16R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F16R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F16R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F16R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F16R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F16R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F16R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F16R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F16R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F16R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F16R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F16R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F16R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F16R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F16R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F16R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F16R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F16R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F16R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F16R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F16R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F16R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F16R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F16R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F16R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F16R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F17R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F17R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F17R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F17R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F17R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F17R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F17R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F17R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F17R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F17R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F17R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F17R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F17R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F17R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F17R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F17R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F17R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F17R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F17R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F17R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F17R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F17R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F17R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F17R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F17R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F17R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F17R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F17R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F17R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F17R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F17R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F17R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F17R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F17R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F17R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F17R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F17R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F17R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F17R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F17R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F17R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F17R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F17R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F17R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F17R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F17R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F17R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F17R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F17R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F17R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F17R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F17R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F17R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F17R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F17R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F17R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F17R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F17R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F17R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F17R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F17R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F17R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F17R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F17R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F17R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F17R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F17R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F17R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F17R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F17R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F17R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F17R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F17R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F17R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F17R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F17R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F17R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F17R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F17R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F17R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F17R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F17R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F17R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F17R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F17R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F17R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F17R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F17R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F17R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F17R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F17R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F17R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F17R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F17R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F17R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F17R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F17R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F17R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F17R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F17R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F17R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F17R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F17R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F17R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F17R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F17R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F17R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F17R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F17R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F17R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F17R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F17R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F17R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F17R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F17R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F17R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F17R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F17R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F17R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F17R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F17R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F17R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F17R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F17R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F17R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F17R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F17R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F17R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F18R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F18R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F18R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F18R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F18R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F18R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F18R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F18R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F18R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F18R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F18R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F18R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F18R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F18R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F18R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F18R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F18R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F18R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F18R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F18R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F18R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F18R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F18R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F18R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F18R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F18R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F18R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F18R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F18R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F18R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F18R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F18R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F18R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F18R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F18R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F18R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F18R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F18R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F18R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F18R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F18R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F18R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F18R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F18R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F18R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F18R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F18R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F18R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F18R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F18R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F18R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F18R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F18R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F18R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F18R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F18R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F18R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F18R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F18R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F18R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F18R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F18R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F18R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F18R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F18R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F18R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F18R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F18R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F18R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F18R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F18R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F18R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F18R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F18R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F18R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F18R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F18R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F18R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F18R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F18R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F18R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F18R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F18R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F18R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F18R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F18R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F18R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F18R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F18R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F18R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F18R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F18R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F18R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F18R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F18R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F18R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F18R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F18R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F18R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F18R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F18R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F18R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F18R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F18R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F18R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F18R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F18R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F18R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F18R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F18R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F18R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F18R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F18R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F18R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F18R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F18R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F18R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F18R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F18R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F18R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F18R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F18R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F18R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F18R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F18R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F18R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F18R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F18R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F19R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F19R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F19R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F19R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F19R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F19R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F19R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F19R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F19R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F19R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F19R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F19R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F19R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F19R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F19R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F19R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F19R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F19R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F19R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F19R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F19R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F19R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F19R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F19R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F19R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F19R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F19R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F19R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F19R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F19R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F19R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F19R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F19R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F19R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F19R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F19R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F19R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F19R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F19R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F19R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F19R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F19R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F19R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F19R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F19R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F19R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F19R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F19R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F19R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F19R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F19R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F19R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F19R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F19R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F19R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F19R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F19R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F19R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F19R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F19R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F19R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F19R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F19R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F19R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F19R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F19R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F19R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F19R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F19R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F19R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F19R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F19R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F19R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F19R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F19R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F19R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F19R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F19R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F19R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F19R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F19R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F19R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F19R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F19R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F19R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F19R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F19R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F19R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F19R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F19R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F19R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F19R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F19R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F19R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F19R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F19R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F19R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F19R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F19R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F19R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F19R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F19R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F19R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F19R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F19R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F19R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F19R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F19R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F19R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F19R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F19R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F19R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F19R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F19R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F19R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F19R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F19R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F19R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F19R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F19R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F19R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F19R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F19R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F19R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F19R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F19R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F19R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F19R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F1R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F1R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F1R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F1R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F1R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F1R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F1R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F1R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F1R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F1R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F1R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F1R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F1R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F1R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F1R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F1R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F1R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F1R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F1R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F1R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F1R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F1R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F1R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F1R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F1R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F1R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F1R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F1R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F1R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F1R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F1R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F1R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F1R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F1R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F1R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F1R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F1R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F1R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F1R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F1R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F1R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F1R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F1R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F1R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F1R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F1R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F1R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F1R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F1R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F1R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F1R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F1R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F1R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F1R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F1R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F1R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F1R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F1R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F1R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F1R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F1R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F1R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F1R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F1R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F1R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F1R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F1R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F1R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F1R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F1R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F1R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F1R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F1R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F1R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F1R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F1R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F1R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F1R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F1R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F1R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F1R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F1R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F1R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F1R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F1R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F1R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F1R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F1R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F1R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F1R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F1R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F1R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F1R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F1R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F1R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F1R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F1R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F1R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F1R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F1R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F1R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F1R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F1R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F1R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F1R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F1R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F1R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F1R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F1R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F1R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F1R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F1R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F1R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F1R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F1R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F1R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F1R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F1R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F1R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F1R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F1R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F1R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F1R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F1R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F1R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F1R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F1R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F1R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F1R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F1R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F1R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F1R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F1R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F1R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F1R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F1R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F1R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F1R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F1R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F1R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F1R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F1R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F1R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F1R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F1R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F1R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F1R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F1R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F1R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F1R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F1R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F1R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F1R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F1R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F1R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F1R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F1R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F1R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F1R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F1R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F1R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F1R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F1R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F1R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F1R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F1R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F1R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F1R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F1R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F1R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F1R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F1R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F1R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F1R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F1R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F1R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F1R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F1R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F1R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F1R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F1R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F1R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F1R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F1R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F1R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F1R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F1R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F1R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F1R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F1R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F1R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F1R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F1R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F1R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F1R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F1R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F1R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F1R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F1R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F1R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F1R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F1R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F1R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F1R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F1R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F1R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F1R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F1R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F1R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F1R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F1R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F1R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F1R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F1R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F1R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F1R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F1R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F1R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F1R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F1R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F1R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F1R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F1R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F1R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F1R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F1R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F1R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F1R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F1R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F1R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F1R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F1R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F1R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F1R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F1R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F1R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F1R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F1R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F1R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F1R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F1R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F1R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F1R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F1R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F1R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F1R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F1R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F1R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F1R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F1R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F1R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F1R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F1R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F1R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F1R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F1R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F1R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F1R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F1R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F1R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F1R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F1R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F1R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F1R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F1R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F1R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F1R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F1R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F1R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F1R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F1R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F1R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F1R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F1R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F1R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F1R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F1R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F1R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F1R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F1R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F1R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F1R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F1R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F1R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F1R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F1R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F1R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F1R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F1R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F1R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F1R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F1R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F1R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F1R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F1R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F1R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F1R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F1R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F1R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F1R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F1R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F1R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F1R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F1R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F1R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F1R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F1R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F1R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F1R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F1R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F1R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F1R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F1R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F1R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F1R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F1R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F1R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F1R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F1R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F1R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F1R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F1R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F1R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F1R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F1R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F1R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F1R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F1R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F1R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F1R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F1R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F1R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F1R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F1R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F1R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F1R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F1R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F1R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F1R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F1R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F1R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F1R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F1R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F1R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F1R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F1R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F1R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F1R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F1R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F1R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F1R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F1R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F1R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F1R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F1R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F1R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F1R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F1R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F1R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F1R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F1R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F1R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F1R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F1R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F1R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F1R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F1R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F1R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F1R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F1R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F1R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F1R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F1R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F1R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F1R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F1R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F1R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F1R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F1R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F1R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F1R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F1R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F1R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F1R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F20R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F20R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F20R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F20R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F20R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F20R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F20R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F20R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F20R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F20R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F20R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F20R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F20R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F20R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F20R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F20R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F20R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F20R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F20R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F20R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F20R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F20R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F20R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F20R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F20R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F20R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F20R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F20R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F20R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F20R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F20R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F20R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F20R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F20R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F20R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F20R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F20R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F20R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F20R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F20R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F20R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F20R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F20R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F20R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F20R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F20R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F20R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F20R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F20R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F20R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F20R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F20R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F20R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F20R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F20R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F20R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F20R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F20R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F20R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F20R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F20R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F20R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F20R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F20R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F20R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F20R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F20R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F20R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F20R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F20R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F20R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F20R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F20R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F20R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F20R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F20R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F20R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F20R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F20R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F20R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F20R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F20R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F20R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F20R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F20R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F20R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F20R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F20R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F20R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F20R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F20R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F20R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F20R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F20R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F20R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F20R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F20R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F20R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F20R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F20R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F20R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F20R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F20R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F20R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F20R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F20R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F20R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F20R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F20R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F20R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F20R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F20R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F20R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F20R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F20R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F20R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F20R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F20R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F20R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F20R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F20R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F20R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F20R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F20R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F20R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F20R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F20R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F20R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F21R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F21R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F21R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F21R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F21R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F21R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F21R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F21R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F21R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F21R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F21R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F21R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F21R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F21R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F21R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F21R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F21R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F21R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F21R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F21R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F21R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F21R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F21R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F21R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F21R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F21R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F21R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F21R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F21R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F21R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F21R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F21R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F21R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F21R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F21R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F21R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F21R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F21R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F21R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F21R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F21R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F21R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F21R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F21R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F21R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F21R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F21R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F21R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F21R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F21R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F21R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F21R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F21R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F21R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F21R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F21R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F21R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F21R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F21R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F21R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F21R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F21R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F21R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F21R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F21R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F21R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F21R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F21R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F21R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F21R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F21R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F21R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F21R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F21R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F21R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F21R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F21R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F21R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F21R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F21R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F21R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F21R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F21R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F21R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F21R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F21R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F21R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F21R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F21R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F21R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F21R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F21R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F21R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F21R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F21R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F21R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F21R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F21R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F21R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F21R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F21R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F21R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F21R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F21R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F21R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F21R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F21R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F21R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F21R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F21R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F21R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F21R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F21R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F21R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F21R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F21R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F21R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F21R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F21R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F21R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F21R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F21R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F21R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F21R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F21R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F21R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F21R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F21R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F22R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F22R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F22R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F22R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F22R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F22R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F22R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F22R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F22R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F22R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F22R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F22R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F22R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F22R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F22R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F22R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F22R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F22R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F22R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F22R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F22R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F22R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F22R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F22R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F22R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F22R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F22R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F22R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F22R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F22R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F22R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F22R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F22R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F22R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F22R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F22R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F22R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F22R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F22R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F22R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F22R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F22R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F22R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F22R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F22R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F22R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F22R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F22R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F22R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F22R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F22R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F22R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F22R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F22R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F22R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F22R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F22R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F22R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F22R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F22R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F22R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F22R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F22R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F22R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F22R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F22R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F22R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F22R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F22R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F22R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F22R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F22R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F22R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F22R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F22R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F22R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F22R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F22R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F22R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F22R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F22R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F22R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F22R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F22R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F22R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F22R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F22R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F22R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F22R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F22R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F22R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F22R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F22R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F22R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F22R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F22R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F22R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F22R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F22R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F22R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F22R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F22R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F22R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F22R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F22R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F22R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F22R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F22R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F22R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F22R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F22R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F22R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F22R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F22R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F22R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F22R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F22R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F22R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F22R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F22R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F22R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F22R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F22R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F22R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F22R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F22R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F22R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F22R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F23R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F23R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F23R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F23R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F23R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F23R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F23R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F23R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F23R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F23R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F23R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F23R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F23R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F23R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F23R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F23R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F23R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F23R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F23R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F23R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F23R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F23R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F23R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F23R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F23R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F23R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F23R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F23R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F23R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F23R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F23R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F23R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F23R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F23R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F23R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F23R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F23R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F23R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F23R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F23R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F23R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F23R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F23R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F23R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F23R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F23R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F23R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F23R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F23R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F23R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F23R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F23R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F23R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F23R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F23R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F23R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F23R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F23R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F23R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F23R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F23R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F23R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F23R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F23R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F23R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F23R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F23R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F23R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F23R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F23R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F23R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F23R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F23R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F23R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F23R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F23R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F23R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F23R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F23R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F23R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F23R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F23R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F23R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F23R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F23R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F23R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F23R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F23R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F23R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F23R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F23R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F23R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F23R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F23R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F23R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F23R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F23R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F23R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F23R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F23R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F23R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F23R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F23R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F23R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F23R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F23R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F23R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F23R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F23R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F23R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F23R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F23R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F23R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F23R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F23R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F23R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F23R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F23R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F23R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F23R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F23R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F23R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F23R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F23R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F23R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F23R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F23R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F23R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F24R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F24R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F24R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F24R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F24R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F24R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F24R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F24R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F24R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F24R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F24R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F24R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F24R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F24R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F24R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F24R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F24R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F24R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F24R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F24R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F24R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F24R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F24R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F24R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F24R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F24R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F24R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F24R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F24R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F24R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F24R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F24R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F24R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F24R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F24R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F24R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F24R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F24R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F24R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F24R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F24R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F24R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F24R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F24R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F24R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F24R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F24R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F24R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F24R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F24R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F24R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F24R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F24R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F24R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F24R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F24R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F24R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F24R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F24R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F24R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F24R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F24R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F24R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F24R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F24R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F24R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F24R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F24R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F24R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F24R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F24R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F24R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F24R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F24R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F24R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F24R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F24R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F24R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F24R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F24R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F24R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F24R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F24R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F24R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F24R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F24R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F24R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F24R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F24R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F24R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F24R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F24R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F24R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F24R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F24R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F24R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F24R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F24R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F24R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F24R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F24R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F24R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F24R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F24R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F24R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F24R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F24R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F24R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F24R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F24R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F24R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F24R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F24R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F24R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F24R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F24R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F24R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F24R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F24R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F24R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F24R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F24R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F24R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F24R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F24R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F24R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F24R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F24R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F25R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F25R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F25R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F25R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F25R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F25R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F25R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F25R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F25R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F25R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F25R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F25R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F25R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F25R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F25R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F25R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F25R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F25R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F25R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F25R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F25R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F25R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F25R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F25R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F25R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F25R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F25R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F25R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F25R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F25R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F25R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F25R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F25R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F25R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F25R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F25R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F25R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F25R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F25R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F25R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F25R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F25R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F25R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F25R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F25R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F25R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F25R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F25R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F25R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F25R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F25R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F25R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F25R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F25R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F25R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F25R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F25R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F25R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F25R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F25R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F25R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F25R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F25R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F25R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F25R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F25R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F25R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F25R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F25R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F25R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F25R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F25R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F25R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F25R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F25R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F25R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F25R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F25R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F25R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F25R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F25R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F25R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F25R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F25R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F25R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F25R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F25R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F25R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F25R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F25R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F25R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F25R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F25R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F25R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F25R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F25R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F25R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F25R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F25R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F25R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F25R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F25R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F25R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F25R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F25R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F25R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F25R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F25R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F25R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F25R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F25R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F25R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F25R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F25R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F25R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F25R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F25R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F25R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F25R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F25R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F25R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F25R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F25R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F25R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F25R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F25R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F25R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F25R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F26R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F26R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F26R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F26R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F26R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F26R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F26R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F26R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F26R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F26R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F26R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F26R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F26R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F26R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F26R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F26R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F26R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F26R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F26R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F26R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F26R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F26R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F26R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F26R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F26R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F26R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F26R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F26R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F26R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F26R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F26R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F26R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F26R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F26R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F26R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F26R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F26R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F26R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F26R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F26R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F26R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F26R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F26R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F26R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F26R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F26R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F26R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F26R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F26R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F26R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F26R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F26R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F26R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F26R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F26R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F26R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F26R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F26R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F26R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F26R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F26R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F26R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F26R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F26R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F26R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F26R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F26R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F26R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F26R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F26R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F26R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F26R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F26R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F26R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F26R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F26R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F26R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F26R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F26R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F26R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F26R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F26R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F26R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F26R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F26R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F26R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F26R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F26R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F26R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F26R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F26R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F26R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F26R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F26R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F26R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F26R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F26R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F26R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F26R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F26R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F26R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F26R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F26R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F26R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F26R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F26R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F26R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F26R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F26R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F26R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F26R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F26R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F26R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F26R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F26R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F26R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F26R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F26R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F26R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F26R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F26R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F26R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F26R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F26R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F26R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F26R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F26R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F26R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F27R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F27R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F27R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F27R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F27R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F27R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F27R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F27R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F27R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F27R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F27R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F27R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F27R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F27R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F27R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F27R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F27R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F27R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F27R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F27R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F27R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F27R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F27R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F27R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F27R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F27R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F27R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F27R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F27R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F27R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F27R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F27R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F27R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F27R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F27R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F27R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F27R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F27R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F27R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F27R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F27R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F27R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F27R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F27R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F27R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F27R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F27R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F27R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F27R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F27R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F27R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F27R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F27R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F27R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F27R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F27R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F27R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F27R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F27R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F27R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F27R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F27R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F27R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F27R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F27R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F27R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F27R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F27R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F27R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F27R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F27R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F27R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F27R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F27R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F27R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F27R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F27R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F27R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F27R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F27R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F27R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F27R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F27R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F27R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F27R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F27R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F27R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F27R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F27R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F27R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F27R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F27R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F27R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F27R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F27R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F27R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F27R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F27R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F27R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F27R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F27R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F27R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F27R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F27R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F27R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F27R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F27R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F27R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F27R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F27R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F27R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F27R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F27R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F27R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F27R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F27R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F27R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F27R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F27R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F27R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F27R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F27R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F27R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F27R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F27R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F27R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F27R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F27R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F2R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F2R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F2R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F2R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F2R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F2R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F2R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F2R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F2R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F2R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F2R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F2R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F2R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F2R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F2R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F2R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F2R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F2R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F2R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F2R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F2R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F2R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F2R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F2R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F2R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F2R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F2R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F2R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F2R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F2R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F2R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F2R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F2R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F2R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F2R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F2R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F2R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F2R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F2R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F2R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F2R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F2R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F2R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F2R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F2R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F2R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F2R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F2R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F2R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F2R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F2R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F2R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F2R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F2R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F2R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F2R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F2R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F2R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F2R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F2R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F2R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F2R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F2R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F2R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F2R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F2R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F2R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F2R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F2R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F2R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F2R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F2R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F2R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F2R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F2R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F2R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F2R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F2R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F2R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F2R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F2R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F2R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F2R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F2R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F2R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F2R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F2R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F2R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F2R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F2R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F2R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F2R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F2R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F2R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F2R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F2R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F2R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F2R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F2R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F2R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F2R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F2R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F2R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F2R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F2R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F2R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F2R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F2R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F2R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F2R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F2R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F2R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F2R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F2R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F2R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F2R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F2R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F2R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F2R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F2R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F2R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F2R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F2R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F2R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F2R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F2R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F2R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F2R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F2R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F2R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F2R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F2R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F2R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F2R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F2R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F2R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F2R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F2R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F2R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F2R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F2R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F2R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F2R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F2R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F2R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F2R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F2R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F2R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F2R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F2R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F2R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F2R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F2R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F2R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F2R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F2R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F2R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F2R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F2R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F2R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F2R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F2R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F2R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F2R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F2R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F2R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F2R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F2R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F2R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F2R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F2R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F2R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F2R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F2R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F2R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F2R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F2R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F2R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F2R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F2R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F2R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F2R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F2R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F2R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F2R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F2R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F2R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F2R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F2R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F2R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F2R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F2R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F2R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F2R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F2R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F2R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F2R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F2R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F2R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F2R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F2R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F2R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F2R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F2R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F2R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F2R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F2R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F2R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F2R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F2R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F2R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F2R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F2R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F2R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F2R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F2R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F2R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F2R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F2R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F2R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F2R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F2R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F2R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F2R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F2R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F2R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F2R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F2R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F2R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F2R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F2R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F2R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F2R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F2R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F2R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F2R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F2R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F2R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F2R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F2R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F2R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F2R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F2R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F2R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F2R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F2R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F2R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F2R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F2R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F2R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F2R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F2R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F2R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F2R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F2R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F2R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F2R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F2R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F2R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F2R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F2R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F2R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F2R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F2R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F2R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F2R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F2R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F2R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F2R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F2R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F2R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F2R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F2R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F2R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F2R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F2R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F2R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F2R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F2R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F2R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F2R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F2R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F2R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F2R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F2R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F2R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F2R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F2R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F2R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F2R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F2R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F2R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F2R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F2R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F2R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F2R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F2R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F2R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F2R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F2R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F2R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F2R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F2R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F2R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F2R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F2R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F2R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F2R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F2R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F2R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F2R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F2R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F2R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F2R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F2R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F2R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F2R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F2R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F2R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F2R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F2R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F2R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F2R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F2R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F2R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F2R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F2R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F2R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F2R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F2R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F2R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F2R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F2R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F2R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F2R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F2R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F2R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F2R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F2R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F2R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F2R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F2R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F2R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F2R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F2R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F2R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F2R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F2R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F2R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F2R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F2R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F2R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F2R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F2R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F2R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F2R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F2R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F2R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F2R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F2R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F2R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F2R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F2R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F2R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F2R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F2R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F2R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F2R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F2R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F2R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F2R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F2R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F2R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F2R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F2R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F2R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F2R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F2R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F2R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F2R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F2R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F2R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F2R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F2R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F3R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F3R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F3R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F3R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F3R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F3R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F3R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F3R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F3R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F3R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F3R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F3R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F3R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F3R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F3R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F3R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F3R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F3R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F3R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F3R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F3R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F3R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F3R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F3R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F3R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F3R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F3R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F3R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F3R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F3R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F3R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F3R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F3R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F3R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F3R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F3R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F3R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F3R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F3R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F3R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F3R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F3R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F3R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F3R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F3R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F3R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F3R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F3R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F3R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F3R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F3R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F3R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F3R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F3R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F3R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F3R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F3R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F3R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F3R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F3R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F3R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F3R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F3R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F3R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F3R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F3R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F3R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F3R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F3R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F3R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F3R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F3R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F3R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F3R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F3R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F3R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F3R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F3R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F3R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F3R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F3R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F3R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F3R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F3R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F3R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F3R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F3R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F3R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F3R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F3R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F3R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F3R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F3R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F3R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F3R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F3R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F3R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F3R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F3R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F3R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F3R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F3R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F3R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F3R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F3R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F3R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F3R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F3R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F3R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F3R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F3R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F3R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F3R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F3R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F3R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F3R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F3R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F3R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F3R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F3R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F3R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F3R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F3R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F3R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F3R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F3R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F3R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F3R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F3R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F3R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F3R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F3R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F3R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F3R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F3R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F3R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F3R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F3R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F3R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F3R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F3R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F3R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F3R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F3R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F3R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F3R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F3R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F3R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F3R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F3R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F3R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F3R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F3R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F3R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F3R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F3R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F3R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F3R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F3R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F3R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F3R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F3R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F3R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F3R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F3R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F3R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F3R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F3R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F3R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F3R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F3R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F3R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F3R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F3R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F3R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F3R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F3R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F3R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F3R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F3R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F3R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F3R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F3R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F3R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F3R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F3R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F3R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F3R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F3R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F3R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F3R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F3R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F3R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F3R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F3R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F3R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F3R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F3R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
| #define CAN_F3R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F3R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F3R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F3R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F3R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F3R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
| #define CAN_F3R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F3R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F3R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F3R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F3R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F3R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
| #define CAN_F3R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F3R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F3R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F3R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F3R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F3R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
| #define CAN_F3R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F3R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F3R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F3R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F3R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F3R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
| #define CAN_F3R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F3R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F3R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F3R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F3R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F3R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
| #define CAN_F3R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F3R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F3R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F3R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F3R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F3R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
| #define CAN_F3R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F3R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F3R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F3R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F3R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F3R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
| #define CAN_F3R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F3R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F3R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F3R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F3R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F3R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
| #define CAN_F3R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F3R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F3R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F3R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F3R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F3R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
| #define CAN_F3R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F3R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F3R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F3R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F3R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F3R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
| #define CAN_F3R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F3R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F3R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F3R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F3R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F3R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
| #define CAN_F3R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F3R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F3R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F3R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F3R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F3R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
| #define CAN_F3R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F3R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F3R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F3R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F3R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F3R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
| #define CAN_F3R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F3R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F3R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F3R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F3R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F3R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
| #define CAN_F3R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F3R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F3R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F3R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F3R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F3R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
| #define CAN_F3R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F3R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F3R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F3R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F3R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F3R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
| #define CAN_F3R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F3R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F3R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F3R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F3R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F3R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
| #define CAN_F3R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F3R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F3R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F3R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F3R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F3R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
| #define CAN_F3R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F3R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F3R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F3R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F3R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F3R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
| #define CAN_F3R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F3R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F3R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F3R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F3R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F3R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
| #define CAN_F3R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F3R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F3R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F3R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F3R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F3R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
| #define CAN_F3R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F3R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F3R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F3R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F3R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F3R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
| #define CAN_F3R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F3R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F3R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F3R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F3R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F3R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
| #define CAN_F3R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F3R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F3R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F3R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F3R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F3R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
| #define CAN_F3R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F3R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F3R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F3R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F3R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F3R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
| #define CAN_F3R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F3R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F3R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F3R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F3R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F3R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
| #define CAN_F3R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F3R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F3R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F3R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F3R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F3R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
| #define CAN_F3R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F3R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F3R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F3R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F3R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F3R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
| #define CAN_F3R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F3R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F3R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F3R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F3R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F3R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
| #define CAN_F3R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F3R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F3R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F3R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F3R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F3R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
| #define CAN_F3R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F3R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F3R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F3R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F3R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F3R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
| #define CAN_F4R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0